EP1197131A1 - Connecteur de traversee et son procede de fabrication - Google Patents

Connecteur de traversee et son procede de fabrication

Info

Publication number
EP1197131A1
EP1197131A1 EP99914213A EP99914213A EP1197131A1 EP 1197131 A1 EP1197131 A1 EP 1197131A1 EP 99914213 A EP99914213 A EP 99914213A EP 99914213 A EP99914213 A EP 99914213A EP 1197131 A1 EP1197131 A1 EP 1197131A1
Authority
EP
European Patent Office
Prior art keywords
conductive material
pcb
conductive
depositing
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99914213A
Other languages
German (de)
English (en)
Other versions
EP1197131A4 (fr
Inventor
John Leroy Parker, Jr.
Pamela L. Miscikowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Viasystems Inc
Original Assignee
Viasystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Viasystems Inc filed Critical Viasystems Inc
Publication of EP1197131A1 publication Critical patent/EP1197131A1/fr
Publication of EP1197131A4 publication Critical patent/EP1197131A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/246—Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal

Definitions

  • the present invention relates in general to printed circuit boards and to methods for fabricating printed circuit boards. More particularly, the present invention relates to printed circuit boards with improved vias which provide electrical communication between wiring patterns formed on two opposing surfaces of a circuit board and/or within the internal strata of the circuit board, and to methods for making improved circuit boards having such vias .
  • a conventional printed wiring board carries ICs as well as other discrete electronic components and circuit elements, which are interconnected to provide the particular electronic circuit functions.
  • those ICs, discrete electronic components, and circuit elements are usually bonded to the printed wiring board using vias or through holes formed in the printed wiring board through which lead wires may be inserted and soldered to the board.
  • vias or through holes formed in the printed wiring board through which lead wires may be inserted and soldered to the board.
  • surface mounting technology widely employed in the printed wiring board manufacturing field. This technology permits an IC to be mounted together with its associated elements on the printed wiring board without forming any through holes or vias in the board.
  • ICs and other on-chip elements may be mounted on a surface mount land or chip land directly without using the through holes or vias .
  • the appropriate vias are often provided remotely from the surface mount land, and any wiring pattern required for interconnecting the elements by way of the vias must be formed on the surface of the base plate.
  • the surface mount land or chip land and the vias or through holes are provided at different locations on the printed wiring board.
  • a corresponding reduction in the size of the surface mount land is required so that required board space is minimized.
  • the wiring pattern that includes leads drawn out from the surface mount land and distributed across different locations must be accordingly fine, but technically, this is practically difficult to achieve. It is also difficult to secure the space required for wiring the leads. In particular, for double-sided high-density wiring pattern implementation, this space limitation poses a problem.
  • the vias formed in the printed wiring board are exposed on each of the opposite sides of the board.
  • surplus solder may flow through the vias, thereby reaching the components on the surface mount land.
  • vias or through holes are formed at desired positions after conductive layers are formed on the entire surface of the opposing major surfaces of the circuit board. Inner surfaces of the thus formed vias are coated with plated layers through the use of a chemical plating method or a chemical/electrical plating method, thereby providing electrical communication between the conductive layers formed on the two major surfaces or internal to the circuit board by way of the plated layers .
  • the vias are formed through the use of a drilling method or a punching method. Therefore, there is the possibility that the circuit board or the conductive layers become distorted during the formation of the through holes. The thus formed distortion will adversely influence the formation of the plated layers so that an effective electrical connection cannot be achieved between the two conductive layers. In addition, fine wiring patterns cannot be formed near the vias due to the distortion of the conductive layers. Thereafter, the conductive layers are shaped in a desired configuration to obtain wiring patterns formed on both of the major surfaces of the circuit board.
  • Another example of prior art via connectors is disclosed in U.S. Pat. No. 3,601,523 "THROUGH HOLE CONNECTORS" to Arndt , issued on Aug.
  • a conductive adhesive is disposed in the through holes or vias for providing electrical communication between the conductive layers formed on both of the major surfaces of the circuit board.
  • the vias are formed after the conductive layers are formed on both of the major surfaces of the circuit board and, therefore, there is a possibility that the conductive layers will become distorted near the vias.
  • electrical communication between the conductive layer and the conductive adhesive is achieved only through the use of the thickness of the conductive layer.
  • the conductive adhesive is exposed to the ambience. Therefore, the shaping of the wiring patterns must be conducted through the use of a dry film or a resist sheet .
  • the increased circuit and component density in the printed circuit boards makes the ability to locate either solder surface mount components or place additional circuitry layers directly above conductive vias highly desirable. This is especially the case when the density of the vias required to service the I/O's of the surface mount components is such that there is no surface area available for attachment pads interstitial to the through hole grid.
  • the problem is especially severe with fine pitch ball grid array components and flip chip attach integrated circuits. Soldering of these surface mount components to the surface pads, i.e., lands, of conventional vias is highly undesirable. This is because the solder used for assembly tends to wick down into the vias . The result is low volume, unreliable solder joints.
  • conductive vias provide an immediate connection from a surface mounted device to the core of a printed circuit board, thereby avoiding inefficient fan out routing patterns that consume space on the outer layers of the multilayer board.
  • These designs present significant assembly problems. Small vias act as entrapment sites for materials that can eventually re-deposit onto the host surface mount land and cause both assembly and reliability problems. Also, these vias act as unintended reservoirs for solder paste that is stenciled onto the surface mount land and used to attached an electronic device to the board. Consequently, an allowance must be made of the solder paste that will be captured by the via and will not be available for the solder joint formed between the device and the board.
  • the present invention is directed to a method of preparing a printed circuit board (PCB) comprising the steps of forming a hole in the PCB to form a via having sidewalls, depositing a first conductive material on the sidewalls of the via, filling the via with a second conductive material, and depositing a third conductive material on first conductive material on the PCB and on the exposed portions of the second conductive material in the via.
  • the via is formed by drilling, punching, laser drilling, or photo-definition, and is preferably formed at the same time as all other holes or openings in the board are formed. Simultaneous formation of all openings in the board lessens misregistration of subsequently applied wiring patterns with the openings as a result of tolerance build-ups.
  • the first and third conductive materials are copper and the first conductive material is preferably deposited to a substantially uniform thickness exceeding approximately 0.2 mils and the third conductive material is preferably deposited to a substantially uniform thickness of between about 0.4 mils and about 0.8 mils, and more preferably each conductive material is deposited to a thickness of about 0.5 mils.
  • the first conductive material is deposited by electrolytic plating and the third conductive material is deposited by feature plating or panel plating.
  • a mask is applied to the surface of the circuit board as a part of the step of filling the vias with the second conductive material. The mask allows only selected vias to be filled with the second conductive material, and protects the first conductive material from being damaged by the via-filling mechanism, such as a doctor or squeegee blade .
  • a method of preparing a PCB comprises the steps of forming a hole in the PCB to form a via extending at least partially through the PCB to an internal surface of the PCB, with the via having sidewalls extending therethrough, depositing a first conductive material on at least one side of the PCB and on the sidewalls of the via such that the via has an opening, filling the opening with a second conductive material, and depositing a third conductive material on the first conductive material on the at least one side of the PCB and on an end of the second conductive material in the opening.
  • a method of making a via connector in an insulator circuit board substrate adapted to carry wiring patterns on both major surfaces, or on one major surface and one of the internal strata, thereof comprises the steps of providing an insulator substrate, forming a via having sidewalls in the insulator substrate between the surfaces by penetrating the insulator substrate through the use of a penetrating means, depositing a first conductive layer on at least one of the major surfaces and on the sidewalls of the via in such a manner as to substantially completely cover the major surface of the insulator substrate and the sidewalls while leaving an opening, depositing a conductive material in the opening of the via to form a via connector, and forming a second conductive layer on the major surface of the insulator substrate subsequent to the formation of the via and the deposition of the conductive material therein in such a manner as to form a substantially flat surface extending across substantially the entirety of the major surface of the substrate and across the via so that an
  • the second conductive layer is etched to form wiring patterns on the major surface of the insulator substrate which is electrically connected to the other major surface or one of the internal strata through the via connector. Moreover, the conductive material is deposited so as to completely fill the via-through-hole .
  • a double-sided printed wiring board comprising an insulator substrate having a via having sidewalls extending therethrough, a first electrically conductive layer electrolytically disposed over both surfaces of the insulator substrate and through the via along the sidewalls between the opposite sides of the insulator substrate, and the first electrically conductive layer leaving a via-through-hole within the via and which via-through-hole extends between opposite sides of the insulator substrate, a mass of conductive material filling the via-through-hole and having opposite ends located at each of the opposite sides of the insulator substrate, respectively, and a second electrically conductive layer covering the first electrically conductive layer disposed over both surfaces of the insulator substrate and covering both ends of the mass of conductive material on both sides of the insulator substrate .
  • Figs. 1A through IE are sectional views of the fabrication steps of an exemplary via connector in accordance with the present invention.
  • Fig. 2 is a schematic representation showing a surface mount land in plan.
  • an insulator substrate or printed circuit board (PCB) having a filled and plated via is provided.
  • the plated via is filled with an electrically conductive fill composition.
  • a conductive cap layer is formed atop the ends of the filled via and can be bonded to a surface mount contact as a land or a pad.
  • Figs . 1A through IE show fabrication steps of one embodiment of the via connector in accordance with the present invention.
  • Fig. 1A shows an insulator substrate 12, such as a printed circuit board or a flexible thin-film substrate.
  • a through hole or via 10 is formed in the insulator substrate 12 at a desired position, as shown in Fig. IB.
  • the via 10 is formed through the use of a drilling method, but any conventional method, such as punching, laser drilling, or photo-definition, can be used.
  • the via 10 can be any diameter, but is preferably in the range between about 2 mils and about 25 mils.
  • all or substantially all of the openings or holes in the printed circuit board are formed at the same time, whether they are ultimately to be filled, as described below, or not.
  • a first conductive layer 14 of a first conductive material is deposited on the surfaces of the substrate 12 and on the sidewalls 16 of the via 10 to leave a via-through-hole 11 in the via 10.
  • the first conductive material is copper.
  • the first conductive material is preferably deposited to a thickness in the range between about 0.1 and about 0.8 mils, and more preferably deposited to a thickness of greater than approximately 0.2 mils, and most preferably to a thickness of approximately 0.5 mils.
  • the layer 14 on the sidewalls is preferably thick enough to provide a robust mechanical structure that will survive the thermal fluctuations and aggressive handling experienced by a PCB during subsequent component assembly and usage .
  • an electrolytic plating process is used to deposit the layer 14.
  • the electrolytic process follows a surface preparation step involving either a direct metallization process or an electroless process.
  • the surface preparation step includes depositing a thin conductive layer that sensitizes the surface and assists in the adhesion of the layer 14 to the sidewalls 16.
  • IBM does not use an electrolytic plating process and thus is limited to a conductive layer thickness typical of electroless depositions, which is limited to approximately 0.2 mils.
  • IBM does not use electrolytic plating because a surface preparation step involving depositing a thin conductive layer will either cover the entire pattern, thereby rendering the device inoperable, or involve additional processing steps leading to increased complexity and higher cost.
  • Direct metallization comprises depositing a thin conductive molecular layer (not shown) on the substrate surfaces and the via sidewalls prior to depositing the layer 14.
  • the conductive layer is preferably palladium or platinum. This process avoids the typical catalytically deposited copper, thereby rendering this device more economically feasible.
  • the electroless surface preparation process comprises depositing a thin conductive layer (not shown) , preferably copper, on the substrate surfaces and the via sidewalls prior to depositing the layer 14, to a thickness in the range between about 30 micro- inches and about 200 micro-inches, and more preferably to a thickness in the range between about 70 micro-inches and about 80 micro- inches.
  • a thin conductive layer preferably copper
  • the surface preparation followed by electrolytic deposition results in a highly linear distribution of the layer 14 on the sidewalls 16 of the via 10.
  • the second conductive material 18 is a conductive ink, preferably containing silver, copper, or a noble metal suspended in an epoxy resin, such as CB100, manufactured by E . I . du Pont de Nemours and Company of Wilmington, Delaware.
  • an epoxy resin such as CB100, manufactured by E . I . du Pont de Nemours and Company of Wilmington, Delaware.
  • any flowable, curable composition with conductive properties can be used as the second conductive material.
  • the second conductive material 18 is patterned for deposition in the via-through-hole 11 using a stencil or a mask.
  • the second conductive material 18 is deposited in the via-through-hole 11, the second conductive material 18 is partially or tack cured, and any excess material 18 (usually in the form of a small peak or cap extending above layer 14) is removed by, for example, light mechanical abrasion. Preferably, no conductive material 18, such as ink particles, remains on the layer 14 after the removal process .
  • the second conductive material 18 is then hard cured.
  • the second conductive material 18 is preferably sufficiently conductive to allow subsequent plating of a conductive cap layer over the filled and plated via 10.
  • layers 20 and 22 of a third conductive material are formed on both major surfaces, respectively, of the insulator substrate 12 inclusive of both ends of the second conductive material 18, as shown in Fig. IE. That is, the upper conductive layer 20 and the lower conductive layer 22 extend across the via 10 and are in electrical communication with each other through the second conductive material 18 and the first conductive layer 14.
  • the via 10 is sealed by the conductive layers 20 and 22, with the conductive layers 20 and 22 acting as a conductive cap.
  • the conductive layers 20 and 22 can be formed by any conventional process such as attaching a copper film to the substrate or plating a copper layer on the substrate .
  • feature plating or panel plating is used to deposit copper to a thickness in the range between about 0.4 mils and about 0.8 mils, and more preferably to a thickness of approximately 0.5 mils.
  • the conductive layers 20 and 22 are shaped in a desired configuration to obtain desired wiring patterns, through the use of conventional photolithography and print and etch methods, for additive circuitization and solderability.
  • a plurality of vias 10 can be formed concurrently in the insulator substrate 12 at desired positions. During subsequent processing, the vias 10 are filled with the conductive material 18 at the same time, preferably using a stencil. This provides improved registration of the vias and circuit patterns formed on the substrate.
  • the present invention allows for the conservation and recapture of the conductive fill material 18. Because a stencil is used to fill the via(s), material usage of the conductive fill material is decreased because the stencil captures excess conductive material 18 which can be recovered without contamination, unlike prior methods in which the excess conductive fill material resides on a copper layer which contaminates the conductive fill material, thus rendering it unsuitable for recovery and reuse. These factors are important to manufacturing costs because curable conductive materials tend to be very expensive. Moreover, because a stencil is used to fill the via(s) 10, the present invention provides the advantage of being able to use a higher force on the squeegee blade to fill the via(s) 10 with the conductive fill material 18, an advantage believed to be especially useful to ensure complete filling of blind vias. A higher force can cause the copper surface to scratch. A stencil protects against this damage.
  • Fig. 2 depicts an exemplary surface mount land 30 aligned with a filled and plated via 10 as well as a pattern 35 aligned with a filled and plated via 10.
  • the double sided printed wiring board described above allows the surface mount land 30 and a pattern on the opposite side to be electrically conductively interconnected by way of the filled and plated via 10. This eliminates the need of providing a via remotely from the surface mount land 30, and therefore it is not necessary to implement a wiring pattern to interconnect the surface mount land 30 to a remote via. Thus, a high density packing can be realized.
  • the above exemplary embodiments have described vias and methods of making vias between two opposing surfaces of a circuit board or insulator substrate, it is nevertheless intended that the exemplary vias and methods of making vias can also be used to provide electrical communication between wiring patterns formed within the internal surfaces or strata of a circuit board.
  • the present invention is equally applicable to blind hole vias, i.e, vias that do not open on both sides of a circuit board.
  • the present invention can be used to connect a surface of a circuit board with one of the internal strata of the board.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L"invention concerne un substrat isolant ou une carte à circuit imprimé (PCB) dotée d"une traversée pleine et plaquée. Le substrat (12) isolant et les parois latérales de la traversée sont plaqués avec une couche (14) conductrice et la traversée est remplie d"une composition (18) de remplissage conductrice. Des couches d"encapsulation (20, 22) conductrices sont formées aux deux extrémités de la composition de remplissage conductrice dans la traversée et les surfaces principales du substrat isolant et peuvent être collées à un contact de montage de surface tel qu"une pastille ou une plage de connexion.
EP99914213A 1999-03-29 1999-03-29 Connecteur de traversee et son procede de fabrication Withdrawn EP1197131A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1999/006729 WO2000059276A1 (fr) 1999-03-29 1999-03-29 Connecteur de traversee et son procede de fabrication

Publications (2)

Publication Number Publication Date
EP1197131A1 true EP1197131A1 (fr) 2002-04-17
EP1197131A4 EP1197131A4 (fr) 2006-07-19

Family

ID=22272452

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99914213A Withdrawn EP1197131A4 (fr) 1999-03-29 1999-03-29 Connecteur de traversee et son procede de fabrication

Country Status (3)

Country Link
EP (1) EP1197131A4 (fr)
AU (1) AU3210999A (fr)
WO (1) WO2000059276A1 (fr)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131516A (en) * 1977-07-21 1978-12-26 International Business Machines Corporation Method of making metal filled via holes in ceramic circuit boards
US4911796A (en) * 1985-04-16 1990-03-27 Protocad, Inc. Plated through-holes in a printed circuit board
US5071517A (en) * 1989-11-21 1991-12-10 Solution Technology Systems Method for directly electroplating a dielectric substrate and plated substrate so produced
US5243142A (en) * 1990-08-03 1993-09-07 Hitachi Aic Inc. Printed wiring board and process for producing the same
JP2653905B2 (ja) * 1990-08-08 1997-09-17 株式会社日立製作所 プリント基板の製造方法と電子部品の実装方法
JPH05218618A (ja) * 1992-01-30 1993-08-27 Cmk Corp プリント配線板の製造方法
US5473120A (en) * 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
US5319159A (en) * 1992-12-15 1994-06-07 Sony Corporation Double-sided printed wiring board and method of manufacture thereof
US5527998A (en) * 1993-10-22 1996-06-18 Sheldahl, Inc. Flexible multilayer printed circuit boards and methods of manufacture
JP3290041B2 (ja) * 1995-02-17 2002-06-10 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層プリント基板、多層プリント基板の製造方法
US5761803A (en) * 1996-06-26 1998-06-09 St. John; Frank Method of forming plugs in vias of a circuit board by utilizing a porous membrane
EP0865231A1 (fr) * 1997-03-14 1998-09-16 Photo Print Electronic GmbH Procédé de fabrication de circuits imprimés avec des contacts de passage

Also Published As

Publication number Publication date
AU3210999A (en) 2000-10-16
WO2000059276A1 (fr) 2000-10-05
EP1197131A4 (fr) 2006-07-19

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18D Application deemed to be withdrawn

Effective date: 20080625