EP1204095A1 - Einrichtung zur tonumschaltung - Google Patents

Einrichtung zur tonumschaltung Download PDF

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Publication number
EP1204095A1
EP1204095A1 EP00929812A EP00929812A EP1204095A1 EP 1204095 A1 EP1204095 A1 EP 1204095A1 EP 00929812 A EP00929812 A EP 00929812A EP 00929812 A EP00929812 A EP 00929812A EP 1204095 A1 EP1204095 A1 EP 1204095A1
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EP
European Patent Office
Prior art keywords
signal
circuit
signals
switching
speech
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EP00929812A
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English (en)
French (fr)
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EP1204095A4 (de
Inventor
Toshiyuki Nomura
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NEC Corp
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NEC Corp
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Publication of EP1204095A1 publication Critical patent/EP1204095A1/de
Publication of EP1204095A4 publication Critical patent/EP1204095A4/de
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/16—Vocoder architecture
    • G10L19/18—Vocoders using multiple modes
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
    • G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
    • G10L19/08—Determination or coding of the excitation function; Determination or coding of the long-term prediction parameters
    • G10L19/12—Determination or coding of the excitation function; Determination or coding of the long-term prediction parameters the excitation function being a code excitation, e.g. in code excited linear prediction [CELP] vocoders

Definitions

  • the present invention relates to a speech encoding/decoding apparatus and, more particularly, to a speech switching apparatus for switching one of a plurality of speech signals.
  • speech is transmitted on a transmission path on which the bit rate changes by using an encoding method of adjusting the quality of a reconstructed speech signal by adapting an encoding bit rate to the transmission path bit rate by increasing/decreasing the bandwidth of the speech signal in accordance with the transmission path bit rate.
  • the present inventor has already proposed a speech encoding/decoding apparatus in Japanese Patent Laid-Open No.
  • a speech encoding apparatus for generating N + 1 signals by changing the sampling frequency of an input speech signal, in hierarchically encoding the speech signal, and simultaneously multiplexing N-level indexes representing linear predictive coefficients, pitches, multipath signals, and gains which are obtained by sequentially encoding the input speech signal and the signals obtained by changing the sampling frequency in increasing order of sampling frequency
  • a speech decoding apparatus for hierarchically changing the sampling frequency of a reconstructed signal in accordance with the bit rate at which decoding is performed.
  • a first CELP (Code Excited Linear Prediction) encoding circuit for receiving the signal obtained by down-sampling an input signal using a down-sampling circuit outputs an encoded output to a second CELP encoding circuit
  • the second CELP encoding circuit encodes the input signal on the basis of the encoded output from the first CELP encoding circuit
  • a multiplexer outputs the encoded outputs from the first and second CELP encoding circuits in the form of a bit stream
  • a demultiplexer outputs the encoded output obtained by the first CELP encoding circuit from the bit stream to a first CELP decoding circuit when a control signal has a low bit rate
  • the bandwidth of a reconstructed speech signal i.e., the sampling frequency of a decoded speech signal
  • the sampling frequency of a decoded speech signal changes in accordance with the bit rate at the time of reception.
  • a sampling frequency must be set for conversion processing from a digital signal to an analog signal.
  • sampling frequencies must be set/changed. During this sampling frequency setting/changing processing, interruptions tend to occur in reconstructed speech.
  • the operation of a conventional speech switching apparatus will be described with reference to Fig. 7.
  • the speech switching apparatus receives two types of speech signals (first and second digital speech signals) sampled with two different sampling frequencies (e.g., 8 kHz and 16 kHz), together with a control signal, and switching and reconstructing the first and second speech signals in accordance with the control signal.
  • first and second digital speech signals sampled with two different sampling frequencies (e.g., 8 kHz and 16 kHz)
  • control signal is a signal for giving an instruction to reconstruct a specific one of the two types of speech signals.
  • a switching circuit 103 receives first and second speech signals and control signal, and switches and outputs the two types of speech signals to a D/A conversion circuit 112 at the switching timing designated by the control signal.
  • the D/A conversion circuit 112 sets the sampling frequency of the speech signal designated by the control signal, converts the input digital signal into an analog signal, and outputs it.
  • the sampling frequency in the D/A conversion circuit must be set/changed. During the setting/changing processing, interruptions occur in the reconstructed speech.
  • the present invention has therefore been made in consideration of the above problems, and has as its object to provide a speech switching apparatus which can reduce strange sounds produced when a plurality of different speech signals are reconstructed/switched.
  • a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, characterized by comprising at least one sampling frequency conversion circuit for converting a sampling frequency of at least one of the plurality of input signals, a delay adjustment circuit for adjusting a phase of the input signal of the plurality of input signals, whose sampling frequency is converted by the sampling frequency conversion circuit and a phase of the remaining input signal, and outputting the signals, and a switching circuit for selecting one of a plurality of output signals from the delay adjustment circuit in accordance with the control signal.
  • the delay adjustment circuit may make an adjustment to match the phase of the signal whose sampling frequency is converted to the phase of the remaining input signal.
  • the switching circuit may switch outputs at a timing set in consideration of a delay time in the delay adjustment circuit with respect to a switching timing designated by the control signal.
  • a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, characterized by comprising a plurality of sampling frequency conversion circuits for converting sampling frequencies of the plurality of input signals to a predetermined frequency, a delay adjustment circuit for adjusting phases between output signals from the plurality of sampling frequency conversion circuits and outputting the signals, and a switching circuit for selecting one signal from a plurality of output signals from the delay adjustment circuit in accordance with the control signal.
  • the delay adjustment circuit may make an adjustment to match the phase of the signal whose sampling frequency is converted to the phase of the remaining input signal.
  • the switching circuit may switch outputs at a timing set in consideration of a delay time in the delay adjustment circuit with respect to a switching timing designated by the control signal.
  • a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, characterized by comprising at least one sampling frequency conversion circuit for converting a sampling frequency of at least one of the plurality of input signals, a delay adjustment circuit for adjusting a phase of the input signal of the plurality of input signals, whose sampling frequency is converted by the sampling frequency conversion circuit and a phase of the remaining input signal, and outputting the signals, an addition circuit for selecting and weighting two signals from a plurality of output signals from the delay adjustment circuit in accordance with the control signal, and a switching circuit for selecting one signal from a plurality of output signals from the delay adjustment circuit and an output signal from the addition circuit in accordance with the control signal.
  • the switching circuit may switch a signal before switching of output signals from the delay adjustment circuit to an output signal from the addition circuit at a timing set in consideration of a delay time in the delay adjustment circuit from a switching timing designated by the control signal, outputs the output signal from the addition circuit for a predetermined interval, and then output the signal after switching.
  • a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, characterized by comprising a plurality of sampling frequency conversion circuits for converting sampling frequencies of the plurality of input signals to a predetermined frequency, a delay adjustment circuit for adjusting phases between output signals from the plurality of sampling frequency conversion circuits and outputting the signals, an addition circuit for selecting and weighting two signals from a plurality of output signals from the delay adjustment circuit in accordance with the control signal, and a switching circuit for selecting one signal from a plurality of output signals from the delay adjustment circuit and an output signal from the addition circuit in accordance with the control signal.
  • the switching circuit may switch a signal before switching of output signals from the delay adjustment circuit to an output signal from the addition circuit at a timing set in consideration of a delay time in the delay adjustment circuit from a switching timing designated by the control signal, output the output signal from the addition circuit for a predetermined interval, and then output the signal after switching.
  • the above speech switching apparatus may further comprise a speech decoding circuit for decoding a plurality of signals sampled from one bit stream with different sampling frequencies, and outputting the signals as the plurality of input signals to the sampling frequency conversion circuit or the delay adjustment circuit; and one signal is selected from a plurality of output decoded signals from the speech decoding circuit in accordance with a bit rate at the time of reception and the control signal and output.
  • a speech decoding circuit for decoding a plurality of signals sampled from one bit stream with different sampling frequencies, and outputting the signals as the plurality of input signals to the sampling frequency conversion circuit or the delay adjustment circuit; and one signal is selected from a plurality of output decoded signals from the speech decoding circuit in accordance with a bit rate at the time of reception and the control signal and output.
  • the above speech switching apparatus may further comprise a bit stream switching circuit for receiving bit streams obtained by multiplexing a plurality of bit streams in which a plurality of types of signals having different sampling frequencies, and switching/outputting the bit streams to a plurality of output terminals in accordance with types of bit streams, and a plurality of speech decoding circuits for decoding the respective bit streams output from the bit stream switching circuit, and outputting the bit streams as the plurality of input signals to the sampling frequency conversion circuit or the delay adjustment circuit, and one signal may be selected from output decoded signals from the plurality of speech decoding circuits in accordance with the control signal and output.
  • a bit stream switching circuit for receiving bit streams obtained by multiplexing a plurality of bit streams in which a plurality of types of signals having different sampling frequencies, and switching/outputting the bit streams to a plurality of output terminals in accordance with types of bit streams
  • a plurality of speech decoding circuits for decoding the respective bit streams output from the bit stream switching circuit, and outputting the bit streams as the pluralit
  • the present invention includes a sampling frequency conversion circuit (1 in Fig. 1) for converting the sampling frequencies of digital speech signals and a delay adjustment circuit (2 in Fig. 1) for adjusting a phase shift caused by sampling frequency conversion between a plurality of digital speech signals.
  • the digital speech signals before and after switching are weighted/added for a predetermined interval first, and then are switched/reconstructed.
  • the present invention includes a sampling frequency conversion circuit (1 in Fig. 3), a delay adjustment circuit (2 in Fig. 3), an addition circuit (6 in Fig. 3) for weighting/adding output signals from the delay adjustment circuit for a predetermined interval, and a switching circuit (7 in Fig. 3) for switching output signals from the addition circuit in accordance with a control signal after outputting an output signal from the addition circuit for the interval.
  • the sampling frequency conversion circuit and delay adjustment circuit make digital signals before and after switching have the same sampling frequency and phase. This reduces the tendency to cause interruptions in reconstructed speech without requiring sampling frequency setting in a D/A circuit.
  • the addition circuit weights/adds digital signals before and after switching to reduce discontinuity between the final sample of a speech signal before switching and the first sample in the interval as compared with a case where no weighting/adding operation is performed.
  • the switching circuit performs switching after an output signal from the addition circuit is output for a predetermined interval. This reduces discontinuity between samples at the start and end of the interval, and hence reduces the tendency to produce strange sounds in reconstructed speech.
  • Fig. 1 is a block diagram showing the arrangement of the first embodiment of the present invention.
  • two types of speech signals first and second speech signals having different sampling frequencies (e.g., 8 kHz and 16 kHz) and a control signal for instructing to reconstruct one of the two types of speech signals are input, and the speech signals are switched and reconstructed in accordance with the control signal.
  • a sampling frequency conversion circuit 1 performs sampling frequency conversion to match the sampling frequency of the first speech signal to the sampling frequency of the second speech signal (e.g., converts the sampling frequency from 8 kHz to 16 kHz), and outputs the resultant signal to a delay adjustment circuit 2.
  • the sampling frequency conversion circuit 1 performs frequency conversion by using a frequency-multiplying or frequency-dividing circuit or performing interpolation or decimation processing. This frequency conversion is performed by using a known circuit. For its operation, refer to, for example, P.P. Vaidyanathan, "Multirate Systems and Filter Banks", Section 4. 1. 1 ( Figure 4.1-8).
  • the output signal undergoes a phase delay with respect to the input signal.
  • D the delay time in this case.
  • the delay adjustment circuit 2 outputs the signal obtained by delaying the input second speech signal by the delay time D using a delay circuit (not shown) and the output signal from the sampling frequency conversion circuit 1 to a switching circuit 3.
  • a delay circuit an arbitrary circuit such as an inverter array or delay line is used.
  • the switching circuit 3 receives the first speech signal having undergone sampling frequency conversion and the second delay signal having undergone delay adjustment from the delay adjustment circuit 2, switches the two types of speech signals, in consideration of the delay time D, in accordance with the control signal, and outputs the resultant signal to a D/A conversion circuit 4.
  • the D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it.
  • the analog signal is provided for a user through a speaker, headphone, or the like.
  • Fig. 2 is a block diagram showing the arrangement of the second embodiment of the present invention.
  • the second embodiment of the present invention additionally has a sampling frequency circuit 5 for performing sampling frequency conversion of a second speech signal, as compared with the first embodiment.
  • a sampling frequency conversion circuit 1 converts the sampling frequency of a first speech signal into a predetermined sampling frequency, and outputs the resultant signal to a delay adjustment circuit 2.
  • the sampling frequency conversion circuit 5 converts the sampling frequency of the second speech signal into a predetermined sampling frequency, and outputs the resultant signal to the delay adjustment circuit 2.
  • D1 be the delay time produced in the sampling frequency conversion circuit 1
  • D2 be the delay time produced in the sampling frequency conversion circuit 5.
  • the delay adjustment circuit 2 performs delay adjustment to set the first and second speech signals having undergone sampling frequency conversion in phase, and outputs the resultant signals to a switching circuit 3.
  • D be one of the delay times D1 and D2 which is longer than the other
  • the two signals are delayed by the same time, i.e., the delay time D, using a delay circuit (not shown).
  • the switching circuit 3 receives the first and second speech signals having undergone sampling frequency conversion and delay adjustment from the delay adjustment circuit 2, switches the two types of speech signals, in consideration of the delay time D, in accordance with the control signal, and outputs the resultant signal to a D/A conversion circuit 4.
  • the D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it.
  • the analog signal is provided for a user through a speaker, headphone, or the like.
  • the sampling frequencies of the first and second speech signals are 8 kHz and 12 kHz, respectively, the sampling frequencies of the first and second speech signals are converted into 24 kHz. This makes it possible to further reduce the processing amount of sampling frequency conversion as compared with the first embodiment in which only the sampling frequency of the first speech signal is converted into 12 kHz.
  • Fig. 3 is a block diagram showing the arrangement of the third embodiment of the present invention.
  • the third embodiment of the present invention further includes an addition circuit 6 as compared with the first embodiment.
  • the operation of a switching circuit 7 differs from that in the first embodiment.
  • a sampling frequency conversion circuit 1 performs sampling frequency conversion to match the sampling frequency of a first speech signal to the sampling frequency of a second speech signal, and outputs the resultant signal to a delay adjustment circuit 2. Let the delay time produced in the sampling frequency conversion circuit 1 be D. The delay adjustment circuit 2 outputs to the addition circuit 6 the signal obtained by delaying the input second speech signal by the delay time D and the output signal from the sampling frequency conversion circuit 1.
  • the addition circuit 6 weights/adds the first speech signal having undergone sampling frequency conversion and the second speech signal having undergone delay adjustment, and outputs the resultant signal to the switching circuit 7.
  • the switching circuit 7 receives the first speech signal having undergone sampling frequency conversion, the second speech signal having undergone delay adjustment, the output signal from the addition circuit 6, and a control signal, and switches the signal to be output from a signal S1(n) before switching to the output signal S3(n) from the addition circuit 6 at a timing set, in consideration of the delay time D, on the basis of the switching timing designated by the control signal.
  • the switching circuit 7 then outputs the signal S1(n) after switching to a D/A conversion circuit after outputting the signal S3(n) for a predetermined interval.
  • a D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it.
  • the analog signal is provided for a user through a speaker, headphone, or the like.
  • Fig. 4 is a block diagram showing the arrangement of the fourth embodiment of the present invention.
  • the fourth embodiment of the present invention further includes an addition circuit 6 as compared with the second embodiment.
  • the operation of a switching circuit 7 differs from that in the second embodiment.
  • the operations of the addition circuit 6 and switching circuit 7 are the same as those described in the third embodiment.
  • a sampling frequency conversion circuit 1 converts the sampling frequency of a first speech signal into a predetermined sampling frequency (e.g., 24 kHz), and outputs the resultant signal to a delay adjustment circuit 2.
  • a sampling frequency conversion circuit 5 converts the sampling frequency of a second speech signal into a predetermined sampling frequency, and outputs the resultant signal to the delay adjustment circuit 2.
  • D1 be the delay time produced in the sampling frequency conversion circuit 1
  • D2 be the delay time produced in the sampling frequency conversion circuit 5.
  • the delay adjustment circuit 2 performs delay adjustment to set the first and second speech signals having undergone sampling frequency conversion in phase, and outputs the resultant signals to the addition circuit 6 and switching circuit 7. For example, in delay adjustment, letting D be one of the delay times D1 and D2 which is longer than the other, the two signals are delayed by the delay time D.
  • the addition circuit 6 weights/adds the first and second speech signals having undergone sampling frequency conversion and delay adjustment, and outputs the resultant signal to the switching circuit 7.
  • equation (1) is used.
  • signals S1(n) and S2(n) before and after switching one of the first and second speech signals having undergone sampling frequency conversion and delay adjustment is assigned.
  • the switching circuit 7 receives the first and second speech signals having undergone sampling frequency conversion and delay adjustment, the output signal from the addition circuit 6, and a control signal, and switches the signal to be output from the signal S1(n) before switching to an output signal S3(n) from the addition circuit 5 at a timing set, in consideration of the delay time D, on the basis of the switching timing designated by the control signal.
  • the switching circuit 7 then outputs the signal S1(n) after switching to a D/A conversion circuit after the signal S3(n) is output for a predetermined interval.
  • a D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it.
  • the analog signal is provided for a user through a speaker, headphone, or the like.
  • Fig. 5 is a block diagram showing the arrangement of a speech switching apparatus according to the fifth embodiment of the present invention, which is a combination of a speech decoding circuit 8 and the arrangement of the third embodiment.
  • the bandwidth-hierarchized speech decoding circuit 8 outputs as first and second digital speech signals digital speech signals obtained by decoding an input bit stream to a sampling frequency conversion circuit 1 and delay circuit 2.
  • the bandwidth-hierarchized speech decoding circuit 8 outputs, to an addition circuit 6 and switching circuit 7, a control signal for instructing which one of two types of speech signals is to be reconstructed.
  • the bit stream is constituted by a fundamental portion indispensable to decoding of compressed speech signal information and an expansion portion for improving the quality of the speech signal by expanding the bandwidth.
  • the bandwidth-hierarchized speech decoding circuit 8 receives only a fundamental portion, it decodes the portion into a speech signal with a narrow bandwidth (e.g., a digital signal having a sampling frequency of 8 kHz), and outputs it to the sampling frequency conversion circuit 1.
  • a narrow bandwidth e.g., a digital signal having a sampling frequency of 8 kHz
  • this circuit When this circuit also receives an expansion portion, it decodes the signal into a speech signal with a winder bandwidth (e.g., a digital signal having a sampling frequency of 16 kHz), and outputs it to the delay adjustment circuit 2.
  • a winder bandwidth e.g., a digital signal having a sampling frequency of 16 kHz
  • the bandwidth-hierarchized speech decoding circuit 8 When the bandwidth-hierarchized speech decoding circuit 8 receives the expansion portion of a bit stream as well as the fundamental portion, the circuit can simultaneously obtain a plurality of decoded signals, i.e., a decoded signal obtained by using only the fundamental portion and a signal obtained by using both the fundamental portion and the expansion portion.
  • sampling frequency conversion circuit 1 delay adjustment circuit 2
  • addition circuit 6 addition circuit 6
  • D/A conversion circuit 4 D/A conversion circuit 4
  • Fig. 6 is a block diagram showing the arrangement of a speech switching apparatus according to the sixth embodiment of the present invention, which is a combination of a plurality of speech decoding circuits and the first embodiment described above.
  • a bit stream switching circuit 11 receives a bit steam obtained by multiplexing a plurality of bit streams as compressed signals having different sampling frequencies, and outputs the input bit stream to a first speech decoding circuit 9 or second speech decoding circuit 10 depending on the type of the received bit stream.
  • a method of multiplexing bit streams a method of simultaneously multiplexing a plurality of bit streams or a method of switching and multiplexing them may be used.
  • two types of speech signals are simultaneously decoded from two types of bit streams.
  • a speech signal is decoded from only one of the bit streams.
  • a bit stream obtained by switching/multiplexing a plurality of bit streams is input.
  • the bit stream switching circuit 11 outputs, to a switching circuit 3, a control signal for instructing which one of the two types of speech signals is to be reconstructed.
  • the first speech decoding circuit 9 outputs a speech signal (e.g., a digital signal having a sampling frequency of 8 kHz) obtained by decoding a bit stream having a lower bit rate (e.g., 8 kbit/s) than in the second speech decoding circuit 10 as a first digital speech signal to a sampling frequency conversion circuit 1.
  • a speech signal e.g., a digital signal having a sampling frequency of 8 kHz
  • a bit stream having a lower bit rate e.g., 8 kbit/s
  • the second speech decoding circuit 10 outputs a speech signal (e.g., a digital signal having a sampling frequency of 16 kHz) obtained by decoding a bit stream having a higher bit rate (e.g., 16 kbit/s) than in the first speech decoding circuit 9 as a second digital speech signal to a delay adjustment circuit 2.
  • a speech signal e.g., a digital signal having a sampling frequency of 16 kHz
  • a bit stream having a higher bit rate e.g., 16 kbit/s
  • first speech decoding circuit 9 and second speech decoding circuit 10 refer to, for example, Japanese Patent Laid-Open No. 10-207496.
  • sampling frequency conversion circuit 1 delay adjustment circuit 2
  • switching circuit 3 switching circuit 3
  • D/A conversion circuit 4 The operations of the sampling frequency conversion circuit 1, delay adjustment circuit 2, switching circuit 3, and D/A conversion circuit 4 are the same as those in the first embodiment, and a description thereof will be omitted.
  • Fig. 5 shows a combination of the bandwidth-hierarchized speech decoding circuit and the arrangement of the third embodiment.
  • Fig. 6 shows a combination of the plurality of speech decoding circuits and the arrangement of the first embodiment. Obviously, however, the above embodiments may be arbitrarily combined with each other.
  • the addition circuit simultaneously requires a plurality of signals, when the first and second speech signals are switched, the two signals must overlap each other.
  • the apparatus must be combined with a bandwidth-hierarchized speech decoding circuit.
  • an input bit stream must be the one obtained by simultaneously multiplexing a plurality of bit streams.
  • Each embodiment exemplifies the case where two type of input speech signals are processed.
  • An apparatus designed to process three or more types of input speech signals can be realized by adding necessary numbers of sampling frequency conversion circuits and input/output lines to be connected thereto.

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  • Engineering & Computer Science (AREA)
  • Computational Linguistics (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
EP00929812A 1999-06-11 2000-05-19 Einrichtung zur tonumschaltung Withdrawn EP1204095A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16466599 1999-06-11
JP11164665A JP2000352999A (ja) 1999-06-11 1999-06-11 音声切替装置
PCT/JP2000/003230 WO2000077775A1 (en) 1999-06-11 2000-05-19 Sound switching device

Publications (2)

Publication Number Publication Date
EP1204095A1 true EP1204095A1 (de) 2002-05-08
EP1204095A4 EP1204095A4 (de) 2005-08-17

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EP (1) EP1204095A4 (de)
JP (1) JP2000352999A (de)
AU (1) AU773996B2 (de)
CA (1) CA2376816A1 (de)
WO (1) WO2000077775A1 (de)

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AU773996B2 (en) * 1999-06-11 2004-06-10 Nec Corporation Sound switching device
EP1699043A4 (de) * 2004-01-08 2008-04-16 Matsushita Electric Industrial Co Ltd Signaldecodierungsverfahren und signaldecodierungsvorrichtung
WO2012045744A1 (en) * 2010-10-06 2012-04-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Apparatus and method for processing an audio signal and for providing a higher temporal granularity for a combined unified speech and audio codec (usac)

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Cited By (11)

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Publication number Priority date Publication date Assignee Title
AU773996B2 (en) * 1999-06-11 2004-06-10 Nec Corporation Sound switching device
EP1699043A4 (de) * 2004-01-08 2008-04-16 Matsushita Electric Industrial Co Ltd Signaldecodierungsverfahren und signaldecodierungsvorrichtung
US7411522B2 (en) 2004-01-08 2008-08-12 Matsushita Electric Industrial Co., Ltd. Signal decoding apparatus and signal decoding method
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WO2012045744A1 (en) * 2010-10-06 2012-04-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Apparatus and method for processing an audio signal and for providing a higher temporal granularity for a combined unified speech and audio codec (usac)
CN103403799A (zh) * 2010-10-06 2013-11-20 弗兰霍菲尔运输应用研究公司 用于针对合成统一语音和音频编解码器（usac）处理音频信号和提供较高时间粒度的设备和方法
TWI486950B (zh) * 2010-10-06 2015-06-01 Fraunhofer Ges Forschung 用以針對聯合統一語音與音訊編解碼器處理音訊信號與提供較高時間粒度之裝置與方法
AU2011311659B2 (en) * 2010-10-06 2015-07-30 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Apparatus and method for processing an audio signal and for providing a higher temporal granularity for a combined unified speech and audio codec (USAC)
RU2562384C2 (ru) * 2010-10-06 2015-09-10 Фраунхофер-Гезелльшафт Цур Фердерунг Дер Ангевандтен Форшунг Е.Ф. Способ и устройство для обработки аудио сигнала и для обеспечения большей детализации во времени для комбинированного унифицированного кодека речи и аудио (usac)
CN103403799B (zh) * 2010-10-06 2015-09-16 弗兰霍菲尔运输应用研究公司 用于针对合成统一语音和音频编解码器(usac)处理音频信号和提供较高时间粒度的设备和方法
US9552822B2 (en) 2010-10-06 2017-01-24 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Apparatus and method for processing an audio signal and for providing a higher temporal granularity for a combined unified speech and audio codec (USAC)

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AU4778900A (en) 2001-01-02
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EP1204095A4 (de) 2005-08-17
CA2376816A1 (en) 2000-12-21
AU773996B2 (en) 2004-06-10

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