EP1212794A2 - Procede de production d'un circuit integre comportant au moins un plan de metallisation - Google Patents

Procede de production d'un circuit integre comportant au moins un plan de metallisation

Info

Publication number
EP1212794A2
EP1212794A2 EP00965776A EP00965776A EP1212794A2 EP 1212794 A2 EP1212794 A2 EP 1212794A2 EP 00965776 A EP00965776 A EP 00965776A EP 00965776 A EP00965776 A EP 00965776A EP 1212794 A2 EP1212794 A2 EP 1212794A2
Authority
EP
European Patent Office
Prior art keywords
dielectric layer
thickness
etching
layer
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00965776A
Other languages
German (de)
English (en)
Inventor
Siegfried Schwarzl
Manfred Engelhardt
Franz Kreupl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1212794A2 publication Critical patent/EP1212794A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials

Definitions

  • V out for the manufacture of an integrated circuit with at least one metallization.
  • Metallization levels are used in m integrated circuits for connecting active components.
  • a metallization level comprises lines and contacts via which the lines are connected to conductive structures. These contacts are often referred to as vias in the professional world.
  • These conductive structures can be diffusion regions, connection electrodes, metal contacts or lines from metallization levels arranged below the respective metallization level. If a plurality of metallization levels arranged one above the other are provided in an integrated circuit, this is referred to as multilayer metallization.
  • a dielectric is first deposited, which surrounds the lines and contacts to be manufactured later. Holes and trenches are formed in the intermetallic dielectric and then filled with metal. This creates contacts in the holes, which are also called vias, and the cables are created in the trench. Filling with metal is carried out by PVD, CVD or electroplating and subsequent chemical mechanical polishing. This method is used in particular when the metallization level is formed from a metal that is difficult to etch
  • dual da ascene is understood to mean that the contact holes and trench are first structured and these are filled together by deposition of metal and chemical mechanical polishing.
  • the contact hole etching be carried out first and then the trench etching for the lines.
  • the contact hole etching there is a risk of exposing the surface of the conductive structure, which can in particular be a copper conductor track, and of applying impurities to the walls of the contact hole.
  • an etch stop layer made of silicon nitride is usually used, on the surface of which a silicon oxide layer is arranged, with which the contact hole and the trench are etched.
  • the selectivity of the etching is limited in many etching processes, for example by the oxygen released during the Si 2 etching, so that the surface underneath is nevertheless exposed.
  • a layer sequence of a first silicon nitride layer be used as intermetallic dielectric, a SiO 2 layer and a second silicon nitride layer.
  • the upper second silicon nitride layer is first structured with a contact hole mask. After removing the contact hole mask, a second layer of SiO 2 is applied.
  • the trenches are then first etched with a line mask and then the contact holes are selectively selected for silicon nitride, except for the lower first silicon nitride layer. With this etching, the structured upper silicon nitride layer acts as an additional mask.
  • the problem of reduced selectivity due to the oxygen released during the Si2 etching also occurs here.
  • the invention is based on the problem of specifying a method for producing an integrated circuit with at least one metallization level, which is suitable for the production of metallization levels with metals which are difficult to etch and in which contamination is avoided. This problem is solved by a method according to claim 1. Further developments of the invention result from the remaining claims.
  • a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are applied to a surface of a substrate.
  • the Dik ke of the second dielectric layer differs from the thickness of the fourth dielectric layer.
  • the second dielectric layer is etched through the fourth dielectric layer and the third dielectric layer using a first etching mask which defines the arrangement of contact holes.
  • the second dielectric layer is etched so deep m that the remaining thickness of the second dielectric layer is substantially equal to the thickness of the fourth dielectric layer.
  • etching is ended before the surface of the underlying layer is exposed. Then, parts of the fourth dielectric layer and the second dielectric layer that are exposed to the third dielectric layer and to the first dielectric layer are etched until the surface underneath is exposed. In the case of the fourth dielectric layer, the surface of the third dielectric layer is exposed; in the case of the second dielectric layer, the surface of the first dielectric layer is exposed.
  • the second etching mask After formation of the second etching mask, it is preferred to first etch m exposed parts of the fourth dielectric layer and the second dielectric layer using a non-selective etching method, which is optimized with a high etching rate. The etching is ended before the surfaces under the surface are exposed. In this Weis 0, the layer thickness must be etched with a selective etching process, which is usually very low etching rates is having vernn- siege. This shortens the duration of the manufacturing process.
  • the third dielectric layer and the first dielectric layer are then etched until the surface underneath is exposed.
  • the surface of the second dielectric layer is uncovered under the third dielectric layer, and the surface of the substrate is uncovered under the first dielectric layer. After this etching, the contact holes and the cable trench are completed.
  • the first etching mask which defines the arrangement of contact holes, is etched into the fourth dielectric layer.
  • the fourth dielectric layer is etched so deep m that the remaining thickness of the fourth dielectric layer is substantially equal to the thickness of the second dielectric layer.
  • a non-selective etching process is then carried out using the second etching mask, which defines the arrangement of line trenches. Due to the preceding etching with the first etching mask, the fourth dielectric layer has depressions at the locations of the contact holes.
  • the non-selective etching process which etches the fourth dielectric layer, the third dielectric layer and the second dielectric layer with essentially the same etching rate, at the locations of the contact holes through the fourth dielectric layer and the third dielectric layer m the second dielectric Layer etched.
  • the fourth layer is etched at the locations of the line trenches outside the contact holes m. Subsequently, parts of the fourth dielectric layer and the second dielectric layer that are exposed to the third dielectric layer and to the first dielectric layer are etched until the underlying surface of the third dielectric layer or the first dielectric layer is exposed.
  • the third dielectric layer and the first dielectric layer are etched, until the underlying surface of the second dielectric layer and the sub ⁇ strats exposed. After this etching the Maislo ⁇ cher and the line trench are completed.
  • the metallization level is completed by forming contacts and lines in the contact holes and the line trench.
  • the first dielectric layer and the third dielectric layer can be made of silicon nitride and the second dielectric layer and the fourth dielectric layer S1O2 are formed without the impairment of the selectivity of the etching of S1O2 with reference to ⁇ 13N4 known from the literature. Therefore, the widths and heights of the trenches and the contact holes can be checked safely. Since the third dielectric layer is not exposed prematurely, widening and beveling of the contact holes is avoided. The bottom of the trench is smooth.
  • Another advantage is that a non-selective etching process can be used for the etching with the first etching mask, which can be optimized with regard to the speed of the etching removal. This means that a fast, inexpensive etching process with a high etching rate can be used for the etching with the first etching mask, since no selectivity of the etching is required here.
  • line trenches and contact holes are first produced, which are subsequently used to form contacts and lines at the metallization level. It is therefore for Preparation of metallization of difficult atzbaren Me ⁇ metals suitable for a damascene technique or dual damascene technology.
  • first dielectric layer and the third dielectric layer are formed from a material containing S13N4 and the second dielectric layer and the fourth dielectric layer are formed from a material containing S1O2.
  • first dielectric layer and the third dielectric layer which act as an etch stop: SiON, amorphous silicon, polysilicon, SiC, Al2O3.
  • the following materials are also suitable for the second dielectric layer and the fourth dielectric layer, in which the majority of the contact holes and the line trench are arranged: S1O2, BPSG, SOG, Flare, BCB, Silk, HSQ, FSG, nanoglass, parylme , PTFE, xerogels, aerogels.
  • the first dielectric layer and the third dielectric layer are preferably of substantially the same thickness. In this case, the first dielectric is etched
  • Layer and the third dielectric layer prevents premature exposure of the surface of the substrate. This avoids contamination of the side walls of the contact holes and / or line trench by material which is present in the surface of the substrate and which is removed by premature exposure in the sense of overstressing.
  • the method is therefore particularly suitable for producing a metallization level which extends to contacts or lines containing copper.
  • any substrate that is suitable as a carrier for a metallization eye is suitable as a substrate.
  • a substrate a semiconductor wafer containing an inte grated circuit ⁇ .
  • the contacts can be manufactured both to one above the integrated circuit that are already metallization and on the Surface Terminal of active components of the integrated circuit rich.
  • the contacts can be on lines, contacts, diffusion areas such as source / dram areas, base areas, emitter areas, collector areas as well as on doped areas of a solar cell or a diode, or connections such as gate electrodes, source / drain areas.
  • An integrated circuit realized in thin-film technology or an insulating carrier is also suitable as a substrate.
  • the integrated circuit can be generated both before and after the production of the metallization level.
  • FIG. 1 shows a section through a substrate on which a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer are arranged.
  • FIG. 2 shows the section through the substrate after formation of a first etching mask and etching up to m d e second dielectric layer.
  • FIG. 3 shows a section through the substrate after the formation of a second etching mask after a partial etching.
  • FIG. 4 shows a section through the substrate after selective etching of the fourth dielectric layer and second dielectric layer.
  • FIG. 5 shows a section through the substrate after etching the third dielectric layer and the first dielectric layer and formation of contacts and lines.
  • a first dielectric layer 3, a second dielectric layer 4, a third dielectric layer 5 and a fourth dielectric layer 6 are applied to a substrate 1, which has a conductive structure 2 (see FIG. 1).
  • the substrate 1 is a monocrystalline silicon wafer in which an integrated circuit (not shown in detail) is implemented.
  • the surface of the substrate 1 is formed by a dielectric passivation layer, on which the conductive structure 2 is arranged.
  • the conductive structure 2 is a copper line.
  • the first dielectric layer 3 is formed by deposition in a Plas a CVD process from S13N4 in a layer thickness of 50 nm.
  • the second dielectric layer 4 is formed by deposition in a Plas a CVD process of S1O2 m with a layer thickness of 850 nm.
  • the third dielectric layer 5 is formed by deposition in a plasma CVD method of S13N4 in a layer thickness of 50 nm.
  • the fourth dielectric layer 6 is formed by deposition in a plasma CVD process from S1O2 in a layer thickness of 600 nm.
  • a first etching mask of photoresist 7 is formed (s ⁇ ere Figure 2).
  • the first etching mask 7 defines the arrangement of contact holes.
  • the second dielectric layer 4 is etched through the fourth dielectric layer 6 and the third dielectric layer 5 m.
  • the etching process used has essentially the same etching rates for S ⁇ 0 2 and S13N4.
  • the etching is controlled over time. The etching stops as soon as the remaining plane thickness of the third dielectric layer is substantially equal to the thickness of the fourth dielectric layer 6, that is to say 600 nm.
  • the first etching mask 7 is then removed by ashing and / or wet-chemically with EKC 525 (this is wet-chemical polymer removal).
  • a second etching mask 8 is subsequently produced, which defines the arrangement of line trenches (see FIG. 3).
  • a RIE process with a high etching rate, the exposed parts of the fourth dielectric layer 6 and the second dielectric layer 4 are subsequently etched.
  • the etching is controlled via the etching time. It is ended before the surface of the third dielectric layer 5 or the first dielectric layer 3 is exposed.
  • the etching is also carried out with CHF 3 and CF4.
  • the remaining thickness of the second dielectric layer 4 and the fourth dielectric layer is 50 to 100 nm.
  • the etching takes place in a RIE process with CF4 and Ar with a low RF power of 250 W and a diameter of the substrate disk of 6.
  • the contact holes and the cable trench are completed.
  • a conformal diffusion barrier layer is subsequently applied by sputtering, which is composed of a 10 nm thick TaN layer and a 40 nm thick Ta layer.
  • a copper seed layer is then sputtered on.
  • the contact holes and cable trenches are filled by electroplating with copper.
  • CMP chemical mechanical polishing

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Selon l'invention, pour réaliser un plan de métallisation comportant des lignes et des contacts, on applique des couches diélectriques sur un substrat (4). On procède d'abord à la réalisation de trous de contact par attaque à travers les deux couches diélectriques supérieures, jusqu'à pénétration dans la couche diélectrique située sous ces deux couches, l'épaisseur restante de cette couche étant sensiblement égale à l'épaisseur de la couche supérieure. Ensuite on procède à la réalisation de tranchées de ligne par attaque sélective par rapport à la première couche diélectrique et à la troisième couche diélectrique dont les surfaces sont enlevées sensiblement simultanément. Après structuration de la première couche diélectrique et de la troisième couche diélectrique, on réalise les contacts et les lignes dans les trous de contact et dans les tranchées de ligne.
EP00965776A 1999-08-25 2000-08-18 Procede de production d'un circuit integre comportant au moins un plan de metallisation Withdrawn EP1212794A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19940358 1999-08-25
DE19940358 1999-08-25
PCT/DE2000/002811 WO2001015219A2 (fr) 1999-08-25 2000-08-18 Procede de production d'un circuit integre comportant au moins un plan de metallisation

Publications (1)

Publication Number Publication Date
EP1212794A2 true EP1212794A2 (fr) 2002-06-12

Family

ID=7919589

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00965776A Withdrawn EP1212794A2 (fr) 1999-08-25 2000-08-18 Procede de production d'un circuit integre comportant au moins un plan de metallisation

Country Status (7)

Country Link
US (2) US20020098679A1 (fr)
EP (1) EP1212794A2 (fr)
JP (1) JP2003508896A (fr)
KR (1) KR20020025237A (fr)
CN (1) CN1192427C (fr)
TW (1) TW461037B (fr)
WO (1) WO2001015219A2 (fr)

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US6605540B2 (en) 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
US20060261036A1 (en) * 2005-04-11 2006-11-23 Stmicroelectronics S.R.L. Method for patterning on a wafer having at least one substrate for the realization of an integrated circuit
US7358182B2 (en) * 2005-12-22 2008-04-15 International Business Machines Corporation Method of forming an interconnect structure
US7592253B2 (en) * 2005-12-29 2009-09-22 Dongbu Electronics Co., Ltd. Method for forming a damascene pattern of a copper metallization layer
WO2007100125A1 (fr) * 2006-02-28 2007-09-07 Advanced Interconnect Materials, Llc Dispositif semiconducteur, son procede de fabrication et materiau cible de pulverisation a utiliser dans ledit procede
US20080303154A1 (en) * 2007-06-11 2008-12-11 Hon-Lin Huang Through-silicon via interconnection formed with a cap layer
DE102007054384A1 (de) 2007-11-14 2009-05-20 Institut Für Solarenergieforschung Gmbh Verfahren zum Herstellen einer Solarzelle mit einer oberflächenpassivierenden Dielektrikumdoppelschicht und entsprechende Solarzelle
TWI490939B (zh) * 2008-10-01 2015-07-01 Vanguard Int Semiconduct Corp 孔洞的形成方法
CN102543837A (zh) * 2010-12-22 2012-07-04 中芯国际集成电路制造(上海)有限公司 顶层金属互连层结构和制作方法
RU2617284C2 (ru) * 2012-03-01 2017-04-24 Конинклейке Филипс Н.В. Устройство электронной схемы и способ его изготовления
KR102477608B1 (ko) * 2017-12-12 2022-12-14 삼성디스플레이 주식회사 표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 표시 장치
CN112018077A (zh) * 2020-07-29 2020-12-01 复旦大学 一种铜互连结构及其制造方法

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US5143820A (en) * 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
KR0184158B1 (ko) * 1996-07-13 1999-04-15 문정환 반도체장치의 자기 정합정 금속 배선 형성 방법
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
US6291334B1 (en) * 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6197696B1 (en) 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
JP3657788B2 (ja) * 1998-10-14 2005-06-08 富士通株式会社 半導体装置及びその製造方法
FR2791472B1 (fr) * 1999-03-26 2002-07-05 Commissariat Energie Atomique Procede de creation de lignes de connexion et de points de contact sous-jacents dans un substrat dielectrique
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Also Published As

Publication number Publication date
WO2001015219A3 (fr) 2001-07-19
CN1377511A (zh) 2002-10-30
US20020098679A1 (en) 2002-07-25
WO2001015219A2 (fr) 2001-03-01
US6930052B2 (en) 2005-08-16
CN1192427C (zh) 2005-03-09
TW461037B (en) 2001-10-21
US20040092093A1 (en) 2004-05-13
KR20020025237A (ko) 2002-04-03
JP2003508896A (ja) 2003-03-04

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