EP1236090A4 - System und verfahren zum implementieren eines cross-barschalters eines breitbandprozessors - Google Patents

System und verfahren zum implementieren eines cross-barschalters eines breitbandprozessors

Info

Publication number: EP1236090A4
Authority: EP; European Patent Office
Prior art keywords: switching system; crossbar switching; broadband processor; processor crossbar; broadband
Prior art date: 1999-02-12
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Withdrawn

Application number

EP00910150A

Other languages

English (en)

French (fr)

Other versions

EP1236090A1 (de

Inventor

Craig Hansen

Bruce Bateman

John Moussouris

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Microunity Systems Engineering Inc

Original Assignee

Microunity Systems Engineering Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1999-02-12

Filing date

2000-02-11

Publication date

2002-09-04

1999-08-24 Priority claimed from US09/382,402 external-priority patent/US6295599B1/en

2000-02-11 Application filed by Microunity Systems Engineering Inc filed Critical Microunity Systems Engineering Inc

2002-09-04 Publication of EP1236090A1 publication Critical patent/EP1236090A1/de

2002-09-04 Publication of EP1236090A4 publication Critical patent/EP1236090A4/de

Status Withdrawn legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Software Systems (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Mathematical Physics (AREA)
Logic Circuits (AREA)

EP00910150A 1999-02-12 2000-02-11 System und verfahren zum implementieren eines cross-barschalters eines breitbandprozessors Withdrawn EP1236090A4 (de)

Applications Claiming Priority (5)

Application Number	Priority Date	Filing Date	Title
US11984199P	1999-02-12	1999-02-12
US119841P		1999-02-12
US09/382,402 US6295599B1 (en)	1995-08-16	1999-08-24	System and method for providing a wide operand architecture
US382402		1999-08-24
PCT/US2000/003566 WO2000048070A1 (en)	1999-02-12	2000-02-11	System and method to implement a cross-bar switch of a broadband processor

Publications (2)

Publication Number	Publication Date
EP1236090A1 EP1236090A1 (de)	2002-09-04
EP1236090A4 true EP1236090A4 (de)	2002-09-04

Family

ID=26817762

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP00910150A Withdrawn EP1236090A4 (de)	1999-02-12	2000-02-11	System und verfahren zum implementieren eines cross-barschalters eines breitbandprozessors

Country Status (2)

Country	Link
EP (1)	EP1236090A4 (de)
WO (1)	WO2000048070A1 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5367694A (en) *	1990-08-31	1994-11-22	Kabushiki Kaisha Toshiba	RISC processor having a cross-bar switch
US5794061A (en) *	1995-08-16	1998-08-11	Microunity Systems Engineering, Inc.	General purpose, multiple precision parallel operation, programmable media processor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE69430018T2 (de) *	1993-11-05	2002-11-21	Intergraph Corp., Huntsville	Befehlscachespeicher mit assoziativem Kreuzschienenschalter
US5931944A (en) *	1997-12-23	1999-08-03	Intel Corporation	Branch instruction handling in a self-timed marking system

2000
- 2000-02-11 EP EP00910150A patent/EP1236090A4/de not_active Withdrawn
- 2000-02-11 WO PCT/US2000/003566 patent/WO2000048070A1/en not_active Ceased

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5367694A (en) *	1990-08-31	1994-11-22	Kabushiki Kaisha Toshiba	RISC processor having a cross-bar switch
US5794061A (en) *	1995-08-16	1998-08-11	Microunity Systems Engineering, Inc.	General purpose, multiple precision parallel operation, programmable media processor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IYER R ET AL: "Switch cache: a framework for improving the remote memory access latency of CC-NUMA multiprocessors", HIGH-PERFORMANCE COMPUTER ARCHITECTURE, 1999. PROCEEDINGS. FIFTH INTERNATIONAL SYMPOSIUM ON ORLANDO, FL, USA 9-13 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 9 January 1999 (1999-01-09), pages 152 - 160, XP010321131, ISBN: 0-7695-0004-8 *
See also references of WO0048070A1 *

Also Published As

Publication number	Publication date
EP1236090A1 (de)	2002-09-04
WO2000048070A1 (en)	2000-08-17

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Legal Events

Date	Code	Title	Description
2002-07-19	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
2002-09-04	17P	Request for examination filed	Effective date: 20010809
2002-09-04	A4	Supplementary search report drawn up and despatched	Effective date: 20020718
2002-09-04	AK	Designated contracting states	Kind code of ref document: A4 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
2003-03-12	17Q	First examination report despatched	Effective date: 20030124
2003-10-24	STAA	Information on the status of an ep patent application or granted ep patent	Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN
2003-12-10	18D	Application deemed to be withdrawn	Effective date: 20030604