EP1313256A3 - Vorrichtung zur Rückgewinnung des Datentaktes - Google Patents

Vorrichtung zur Rückgewinnung des Datentaktes Download PDF

Info

Publication number: EP1313256A3
Authority: EP; European Patent Office
Prior art keywords: phase; locked loop; jitter; upper limit; limit value
Prior art date: 2001-11-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Withdrawn

Application number

EP02005904A

Other languages

English (en)

French (fr)

Other versions

EP1313256A2 (de

Inventor

Hitoyuki c/o Mitsubishi Denki K.K. Tagami

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Mitsubishi Electric Corp

Original Assignee

Mitsubishi Electric Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2001-11-14

Filing date

2002-03-14

Publication date

2006-05-17

2002-03-14 Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp

2003-05-21 Publication of EP1313256A2 publication Critical patent/EP1313256A2/de

2006-05-17 Publication of EP1313256A3 publication Critical patent/EP1313256A3/de

Status Withdrawn legal-status Critical Current

Links

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Landscapes

Engineering & Computer Science (AREA)
Computer Networks & Wireless Communication (AREA)
Signal Processing (AREA)
Synchronisation In Digital Transmission Systems (AREA)
Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

EP02005904A 2001-11-14 2002-03-14 Vorrichtung zur Rückgewinnung des Datentaktes Withdrawn EP1313256A3 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP2001349319A JP2003152694A (ja)	2001-11-14	2001-11-14	データ・クロック再生装置
JP2001349319		2001-11-14

Publications (2)

Publication Number	Publication Date
EP1313256A2 EP1313256A2 (de)	2003-05-21
EP1313256A3 true EP1313256A3 (de)	2006-05-17

Family

ID=19162004

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP02005904A Withdrawn EP1313256A3 (de)	2001-11-14	2002-03-14	Vorrichtung zur Rückgewinnung des Datentaktes

Country Status (3)

Country	Link
US (1)	US7039149B2 (de)
EP (1)	EP1313256A3 (de)
JP (1)	JP2003152694A (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CN100521597C (zh) *	2003-05-01	2009-07-29	三菱电机株式会社	时钟数据恢复电路
US7412019B2 (en) *	2004-07-30	2008-08-12	Faraday Technology Corp.	Spread spectrum clock generator
CN101176259B (zh) *	2005-05-12	2011-12-21	三菱电机株式会社	Pll电路及其设计方法
JP2011254122A (ja) *	2009-03-23	2011-12-15	Nec Corp	回路、制御システム、制御方法及びプログラム
US8681917B2 (en)	2010-03-31	2014-03-25	Andrew Llc	Synchronous transfer of streaming data in a distributed antenna system
US8666010B1 (en) *	2012-09-24	2014-03-04	Xilinx, Inc.	Phase detector for bursty data streams
US9660797B2 (en) *	2013-03-21	2017-05-23	Telefonaktiebolaget Lm Ericsson (Publ)	Method and apparatus for implementing clock holdover
US9143316B1 (en) *	2014-07-03	2015-09-22	Xilinx, Inc.	Non-disruptive eye scan for data recovery units based on oversampling
CN106301358B (zh) *	2015-05-28	2019-01-01	瑞昱半导体股份有限公司	快速锁定的时脉数据回复装置与其方法
US10560109B2 (en) *	2017-12-29	2020-02-11	Texas Instruments Incorporated	Phased locked loop integrated circuit
US11212072B1 (en)	2020-12-22	2021-12-28	Xilinx, Inc.	Circuit for and method of processing a data stream

Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0585050A2 (de) *	1992-08-24	1994-03-02	Oki Electric Industry Co., Ltd.	Mehrmoden-Frequenzsynthetisierer mit reduziertem Zittern
US6061352A (en) *	1995-12-14	2000-05-09	Matsushita Electric Industrial Co., Ltd.	ATM cell receiver system with source clock recovery
WO2001024373A1 (en) *	1999-09-29	2001-04-05	Tait Electronics Limited	Improvements relating to pll frequency synthesisers

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS58108832A (ja) *	1981-12-23	1983-06-29	Toshiba Corp	信号再生回路
JPS63136718A (ja)	1986-11-28	1988-06-08	Hitachi Ltd	Ｐｌｌ回路
JPH03258022A (ja)	1990-03-08	1991-11-18	Nec Corp	二重ループ形ｐｌｌ回路
US5038115A (en) *	1990-05-29	1991-08-06	Myers Glen A	Method and apparatus for frequency independent phase tracking of input signals in receiving systems and the like
US6067335A (en) *	1996-08-02	2000-05-23	Silicon Systems, Inc.	Read channel IC for dual PLL solution
JP2944607B2 (ja) *	1998-02-12	1999-09-06	日本電気アイシーマイコンシステム株式会社	ディジタルｐｌｌ回路とクロックの生成方法
JP2000003563A (ja)	1998-06-15	2000-01-07	Matsushita Electric Ind Co Ltd	情報伝送方法と情報伝送装置およびこれを用いた光ディスク装置
DE19842711C2 (de) *	1998-09-17	2002-01-31	Infineon Technologies Ag	Schaltung zur Datensignalrückgewinnung und Taktsignalregenerierung
DE19913110C1 (de) *	1999-03-23	2000-11-16	Siemens Ag	Frequenzsynthesizer
US6636575B1 (en) *	1999-08-05	2003-10-21	Koninklijke Philips Electronics N.V.	Cascading PLL units for achieving rapid synchronization between digital communications systems
US6876651B1 (en) *	2000-09-21	2005-04-05	Ericsson Inc.	Cascaded parallel phase locked loops

2001
- 2001-11-14 JP JP2001349319A patent/JP2003152694A/ja not_active Abandoned
2002
- 2002-03-13 US US10/095,518 patent/US7039149B2/en not_active Expired - Fee Related
- 2002-03-14 EP EP02005904A patent/EP1313256A3/de not_active Withdrawn

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0585050A2 (de) *	1992-08-24	1994-03-02	Oki Electric Industry Co., Ltd.	Mehrmoden-Frequenzsynthetisierer mit reduziertem Zittern
US6061352A (en) *	1995-12-14	2000-05-09	Matsushita Electric Industrial Co., Ltd.	ATM cell receiver system with source clock recovery
WO2001024373A1 (en) *	1999-09-29	2001-04-05	Tait Electronics Limited	Improvements relating to pll frequency synthesisers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CO R S ET AL: "OPTIMIZATION OF PHASE-LOCKED LOOP PERFORMANCE IN DATA RECOVERY SYSTEMS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 29, no. 9, 1 September 1994 (1994-09-01), pages 1022 - 1034, XP000475946, ISSN: 0018-9200 *

Also Published As

Publication number	Publication date
US7039149B2 (en)	2006-05-02
US20030091138A1 (en)	2003-05-15
JP2003152694A (ja)	2003-05-23
EP1313256A2 (de)	2003-05-21

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Legal Events

Date	Code	Title	Description
2003-04-04	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
2003-05-21	AK	Designated contracting states	Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
2003-05-21	AX	Request for extension of the european patent	Extension state: AL LT LV MK RO SI
2006-03-31	PUAL	Search report despatched	Free format text: ORIGINAL CODE: 0009013
2006-05-03	RAP1	Party data changed (applicant data changed or rights of an application transferred)	Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA
2006-05-17	AK	Designated contracting states	Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
2006-05-17	AX	Request for extension of the european patent	Extension state: AL LT LV MK RO SI
2006-07-19	17P	Request for examination filed	Effective date: 20060602
2006-09-06	17Q	First examination report despatched	Effective date: 20060807
2007-01-24	AKX	Designation fees paid	Designated state(s): DE FR GB IT
2007-05-04	STAA	Information on the status of an ep patent application or granted ep patent	Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN
2007-06-06	18D	Application deemed to be withdrawn	Effective date: 20061219