EP1405413A2 - Circuit multiplicateur - Google Patents

Circuit multiplicateur

Info

Publication number
EP1405413A2
EP1405413A2 EP20020752994 EP02752994A EP1405413A2 EP 1405413 A2 EP1405413 A2 EP 1405413A2 EP 20020752994 EP20020752994 EP 20020752994 EP 02752994 A EP02752994 A EP 02752994A EP 1405413 A2 EP1405413 A2 EP 1405413A2
Authority
EP
European Patent Office
Prior art keywords
input
current
output
multiplier circuit
current mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP20020752994
Other languages
German (de)
English (en)
Other versions
EP1405413B1 (fr
Inventor
Martin Simon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1405413A2 publication Critical patent/EP1405413A2/fr
Application granted granted Critical
Publication of EP1405413B1 publication Critical patent/EP1405413B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function

Definitions

  • the present invention relates to a multiplier circuit.
  • Analog multiplier circuits for multiplying two input signals i.e. determining their sum and difference frequencies, are usually used in transmitters and receivers in high-frequency applications.
  • a Gilbert multiplier cell constructed in bipolar circuit technology is given in FIG. 10.9.
  • a first input for example a local oscillator signal, which has a carrier frequency
  • a first input which is coupled to control inputs of two transistor pairs.
  • the load connections of the transistors of these pairs of transistors are connected on the one hand to a current output of the mixer and on the other hand each connected in pairs in a common emitter node.
  • a load connection of a differential amplifier is connected to each emitter node, the control inputs of which can be supplied with a second signal to be multiplied, which is usually the useful input signal to be converted to a different frequency level or the carrier frequency modulating signal. While the differential amplifier works in its linear range, the transistors of the transistor pairs, to which the local oscillator signal can be fed on the control input side, are operated in a switched manner and form quadrature modulators of the mixer.
  • the control inputs of the differential amplifier are accordingly controlled by low-pass filtered baseband signals, these control inputs being fed by digital / analog converters which are connected on the output side to a digital baseband module.
  • a relatively large operating current must be set in the differential amplifiers.
  • the comparatively high operating current and the normally provided feedback resistances of the differential amplifiers also lead to a comparatively high noise level at the modulator output.
  • An analog multiplier circuit is specified in document EP 1 160 717 AI. Both inputs are designed for supplying voltage signals.
  • the emitter nodes of the differential amplifiers are connected to one of the inputs via current mirrors.
  • a total of four resistors are connected between the current mirror and ground to convert the voltage signal into a current signal.
  • a circuit for setting the amplitude of a signal is specified in EP 0 365 085 A2.
  • the object of the present invention is to provide a multiplier circuit which is suitable for use in vector modulators and which, with a simple structure, has improved noise properties.
  • At least one current mirror is provided in the present invention for feeding the useful signal to be transmitted. This allows the Gilbert multiplier cell described at the beginning
  • a further reduction in the noise of the present multiplier circuit can be achieved by reducing the channel width to channel length ratio of the current mirror transistors.
  • a filter circuit for filtering the second input signal that can be fed to the second input of the multiplier circuit is provided with a current output that is connected to the input of the at least one current mirror.
  • low-pass filters are usually provided on the input side of frequency mixers or multiplier circuits, which usually have a current output anyway on the output side.
  • this current output of the low-pass filter can advantageously be coupled to the inputs of the current mirror of the multiplier, so that a conversion of the output current of the filter into a voltage, which can then be supplied to the conventional Gilbert multiplier cell, can be avoided. This can further improve the noise properties, the power requirement and the linearity properties.
  • the filter circuit comprises a low-pass filter.
  • the current source for supplying the second signal input of the mixer namely the linear input, is preferably the current source already provided in the output stage of the baseband low-pass filter.
  • a voltage-controlled current source is provided, the current output of which is coupled to the input of the at least one current mirror.
  • the control voltage that can be supplied to the voltage-controlled current source represents, for example, a baseband signal that can be supplied to the mixer in a mobile radio transmitter. If this signal is present as a voltage signal, the voltage-controlled current source described, which represents a voltage-current converter with a downstream current mirror for forming the second input of the analog multiplier, can be used while maintaining the improved linearity and noise characteristics as well as the lower current requirement of the present multiplier circuit a voltage input with high input resistance can be provided at the second input.
  • the at least one current mirror has an input transistor connected as a diode, which is followed by a current mirror output transistor.
  • a low-pass filter is provided between the input and output transistor of the current mirror, which couples the input transistor to the output transistor.
  • the multiplier circuit is designed for processing differential signals.
  • FIG. 1 shows a first exemplary embodiment of the present invention with a low-pass filter as the current source
  • FIG. 2 shows a second exemplary embodiment of the invention using a simplified circuit diagram with a voltage-controlled current source
  • FIG. 3 shows a further development of the embodiment according to Figure 2 and
  • FIG. 4 shows an application example of the multiplier circuits according to FIGS. 1 to 3 in a modulator of a mobile radio transmitter using a simplified block diagram.
  • FIG. 1 shows a multiplier circuit with a first input 1, 2 designed for supplying a differential signal, to which a local oscillator signal provided by an oscillator with a carrier frequency to be modulated can preferably be supplied.
  • the first input 1, 2 is connected to one control input each of a transistor 3, 4, 5, 6, two transistors 3, 4; 5, 6 are interconnected in pairs.
  • one load connection each of the transistors 3, 4, which form a first transistor pair, and one load connection each of the transistors 5, 6, which form a second transistor pair are connected to one another to form a current input 7, 8.
  • the high-frequency output 9, 10 is designed to provide differential output signals.
  • the current input 7, 8 of the transistor pairs 3, 4; 5, 6 is via a current mirror 11, 12; 13, 14 connected to a second input 15, 16 for supplying a second input signal to be multiplied.
  • the current mirror 11, 12; 13, 14 each include an input current mirror transistor 11, 13 connected as a diode and an output transistor 12, 14, which is connected with its control input to the control input of the input current mirror transistor 11, 13.
  • the current mirror transistors 11 to 14 are coupled to a reference potential connection 17 via one load connection each.
  • the low-pass filter 18 is preceded by a digital / analog converter 19, which converts the useful signals to be transmitted, which are usually present as digital signals, or components of these useful signals to be transmitted, which can be supplied, for example, from a baseband processing chain, into analog signals.
  • a digital / analog converter 19 which converts the useful signals to be transmitted, which are usually present as digital signals, or components of these useful signals to be transmitted, which can be supplied, for example, from a baseband processing chain, into analog signals.
  • undesired spectral components can arise, which can be filtered out before a frequency mixing of the useful signal with a local oscillator signal with a carrier frequency with a low-pass filter 18.
  • the current mirror transistors 11 to 14 can be used to achieve a desired current gain by adjusting the ratio of the current mirrors by suitably setting the channel width to channel length ratio of the transistors.
  • the transistor pairs 3 to 6, which operate as quadrature modulators in the present exemplary embodiment, are operated in a switched manner.
  • the differential amplifier usually provided in Gilbert mixers for supplying the second input signal is omitted in the present circuit and can be replaced by current sources with a significantly higher linearity, the present multiplier circuit operates with a significantly lower one
  • Figure 2 shows a further embodiment of the present multiplier circuit.
  • a voltage / current converter formed with an operational amplifier is provided at the second input 15, 16 to provide a current source for the current mirror transistors 11 to 14 instead of the low-pass filter 18 provided in FIG.
  • the structure of the multiplier circuit between first input 1, 2, second input 15, 16 and output 9, 10 corresponds in terms of circuitry and function to that already explained for FIG. 1 and should therefore not be repeated again here.
  • a transistor 22, 23, controlled by an associated operational amplifier 20, 21, each with a load connection is connected to the second input 15, 16.
  • Each additional load connection of the transistors 22, 23 controlled by the operational amplifier 20, 21 is connected via a resistor 24 to a reference potential connection 25.
  • the resistors 24 work as a current source and each serve to adjust the current to be amplified by the current mirrors 11 to 13.
  • the inverting inputs of the operational amplifiers 20, 21 are each connected to that load connection of the transistor 22, 23 which is connected to the resistor 24, 25 to form a feedback.
  • FIG. 3 shows a development of the multiplier circuit with voltage / current conversion according to FIG. 2 in an implementation of the operational amplifiers for voltage / current conversion and the rest of the circuit with MOS field-effect transistors. Structure and function of the multiplier circuit between the first input 1, 2, output 9, 10, transistor pairs 3 to 6, and current input 15, 16 correspond to the exemplary embodiments according to FIGS.
  • FIG. 3 shows an embodiment of the operational amplifiers 20, 21 shown schematically in FIG. 2 with MOS field-effect transistors. These each have an input transistor 28, 29 which forms the ⁇ input, the control input of which is connected in each case to the non-inverting input 26, 27 of the operational amplifier 20, 21 and which in each case has one of its load connections to the load terminal of a input which forms the input of the operational amplifier Transistors 30, 31 is connected, which according to FIG.
  • a reference potential side, common load connection node of transistors 28, 30; 27, 29 is via a current mirror 32, 33; 34, 35 each connected to a connection for supplying a reference current 36, 37.
  • the further load connections of the operational amplifier input transistors 28, 30; 29, 31 are each connected to one another and to supply voltage connection 25 via a further current mirror 38, 39 or 40, 41.
  • FIG. 4 finally shows the use of a multiplier circuit 42, 43 according to the invention in each case in an in-phase and a quadrature branch I, Q of a transmission arrangement with complex signal processing.
  • the transmission arrangement comprises a baseband module 44, with a block for digital signal processing 45, which provides digital baseband signals to be transmitted with complex values, that is to say broken down into an in-phase and a quadrature component I, Q.
  • a low-pass filter 47 is connected to a respective digital / analog converter 48 provided in the in-phase and quadrature branches I, Q.
  • the outputs of the low-pass filters 47 are in turn connected to the useful signal inputs of the mixers 42, 43.
  • the frequency mixers 42, 43 are each used to form a vector modulator
  • the local oscillator input connected via a common frequency divider 49 to a voltage-controlled oscillator 50, which provides the local oscillator signal.
  • the multipliers 42, 43 are linked to a common summing node 51 for summing up the high-frequency output signals of the multiplier circuits 42, 43, the summing node 51, for example, via provides a high-frequency signal to be sent, not shown, antenna.
  • the multiplier circuit according to the invention which dispenses with the differential amplifier of a conventional Gilbert cell, significantly improves the noise properties of the multipliers, the high-frequency signal provided on the summing node 51 on the output side has a particularly high signal-to-noise ratio.
  • the multipliers 42, 43 due to the reduced power requirement of the specified multipliers 42, 43, a longer battery or accumulator operating time between two charging cycles can be achieved when the multipliers are used in mobile radio transmitters in mobile stations.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Amplitude Modulation (AREA)
  • Transmitters (AREA)
  • Amplifiers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

L'invention concerne un circuit multiplicateur destiné à multiplier deux signaux d'entrée. Selon l'invention, deux paires de transistors (2, 3 ; 4, 5) couplent une première entrée (1, 2) à une sortie (9, 10) du multiplicateur, des connexions de charge des paires de transistors (2, 3 ; 4, 5) étant raccordées à une deuxième entrée (15, 16) du multiplicateur par l'intermédiaire d'un miroir de courant (11, 12). Ainsi, il est possible de s'affranchir de l'amplificateur différentiel habituellement employé dans des multiplicateurs Gilbert de manière à obtenir de meilleures caractéristiques de bruit d'un dispositif émetteur comportant un modulateur vectoriel dans lequel les multiplicateurs sont de préférence employés.
EP02752994A 2001-07-06 2002-07-03 Circuit multiplicateur Expired - Lifetime EP1405413B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10132802A DE10132802A1 (de) 2001-07-06 2001-07-06 Multipliziererschaltung
DE10132802 2001-07-06
PCT/DE2002/002427 WO2003005582A2 (fr) 2001-07-06 2002-07-03 Circuit multiplicateur

Publications (2)

Publication Number Publication Date
EP1405413A2 true EP1405413A2 (fr) 2004-04-07
EP1405413B1 EP1405413B1 (fr) 2005-02-02

Family

ID=7690837

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02752994A Expired - Lifetime EP1405413B1 (fr) 2001-07-06 2002-07-03 Circuit multiplicateur

Country Status (4)

Country Link
US (1) US20040174199A1 (fr)
EP (1) EP1405413B1 (fr)
DE (2) DE10132802A1 (fr)
WO (1) WO2003005582A2 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003016379A (ja) * 2001-06-29 2003-01-17 A&Cmos Communication Device Inc アナログ乗算回路
DE10334805B4 (de) * 2003-07-30 2005-07-07 Fachhochschule Karlsruhe-Hochschule für Technik, Anstalt des öffentlichen Rechts Analoge Multiplizierschaltung
DE10351606B3 (de) 2003-11-05 2005-05-25 Infineon Technologies Ag Hochfrequenz-Mischeranordnung
US7049882B2 (en) * 2004-02-03 2006-05-23 Broadcom Corporation Transmitter IF section and method enabling IF output signal amplitude that is less sensitive to process, voltage, and temperature
US7221300B2 (en) * 2004-05-21 2007-05-22 Texas Instruments Incorporated Digital-to-analog converter data rate reduction by interleaving and recombination through mixer switching
DE102005005332A1 (de) * 2005-01-28 2006-08-10 Atmel Germany Gmbh Mischstufe und Verfahren zur Mischung von Signalen verschiedener Frequenzen
TWI326965B (en) * 2007-01-30 2010-07-01 Mstar Semiconductor Inc Mixer
US8344803B2 (en) * 2007-11-09 2013-01-01 Hittite Microwave Norway As Variable gain amplifier
US8279006B2 (en) * 2007-11-12 2012-10-02 Hittite Microwave Norway As Low noise amplifier
US8456236B2 (en) * 2008-05-19 2013-06-04 Hittite Microwave Norway As Multiple input variable gain amplifier
CN101989835B (zh) * 2009-07-30 2013-04-03 晨星软件研发(深圳)有限公司 信号处理电路
CN101873102A (zh) * 2010-04-30 2010-10-27 北京利云技术开发公司 一种高线性度且适合低电压工作的上变频混频器
GB2539457A (en) 2015-06-16 2016-12-21 Nordic Semiconductor Asa Voltage regulators
US10700640B2 (en) * 2018-06-11 2020-06-30 The Regents Of The University Of California Harmonic-based nonlinearity factorization scheme to facilitate up-conversion mixer linearity
US10852182B2 (en) * 2018-06-29 2020-12-01 Osram Opto Semiconductors Gmbh Ambient light detector, detector array and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3835499A1 (de) * 1988-10-19 1990-04-26 Philips Patentverwaltung Schaltungsanordnung zum einstellen der amplitude eines signals
JP3300534B2 (ja) * 1993-09-13 2002-07-08 株式会社東芝 電子回路
JP2891297B2 (ja) * 1996-09-30 1999-05-17 日本電気株式会社 電圧電流変換回路
FR2769388B1 (fr) * 1997-10-07 2001-08-03 Korea Telecomm Authority Multiplieur et synapse de reseau neuronal utilisant un miroir de courant comportant des transistors a effet de champ mos de faible puissance
FI107656B (fi) * 1998-10-30 2001-09-14 Nokia Mobile Phones Ltd Alipäästösuodin lähettimessä ja matkaviestin
JP2001344559A (ja) * 2000-05-30 2001-12-14 Matsushita Electric Ind Co Ltd アナログ乗算回路および可変利得増幅回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03005582A2 *

Also Published As

Publication number Publication date
US20040174199A1 (en) 2004-09-09
EP1405413B1 (fr) 2005-02-02
WO2003005582A2 (fr) 2003-01-16
DE50202182D1 (de) 2005-03-10
WO2003005582A3 (fr) 2003-03-13
DE10132802A1 (de) 2002-11-14

Similar Documents

Publication Publication Date Title
DE4420447C2 (de) Phasenschieberschaltung und Quadraturnetzwerk
EP1405413B1 (fr) Circuit multiplicateur
DE69934020T2 (de) Pll-schaltung und funkbetriebenes kommunikationssendegerät mit einer phasenregelschleife
DE10351606B3 (de) Hochfrequenz-Mischeranordnung
DE4126080A1 (de) Mischersystem fuer einen direktumsetzungsempfaenger
EP0341531A2 (fr) Amplificateur à large bande réglable
DE10231181A1 (de) Verstärkerschaltung mit einstellbarer Verstärkung und Sendeanordnung mit der Verstärkerschaltung
DE102004060177B3 (de) Polarmodulator und Verfahren zur Modulation eines Signals
DE10245609B4 (de) Mischvorrichtung
DE69802158T2 (de) Doppelgegentaktmodulator und vier Phasen Modulationseinrichtung
EP1481487B1 (fr) Dispositif d'emission
DE102005028747A1 (de) Mischeranordnung, Verwendung der Mischeranordnung und Verfahren zur Frequenzumsetzung
WO2003005575A2 (fr) Dispositif d'emission a regulation de puissance
DE102005008372B4 (de) Steuerbarer Verstärker und dessen Verwendung
DE10344876B3 (de) Signalverarbeitungseinrichtung, insbesondere für den Mobilfunk
DE19950714A1 (de) Vorrichtung mit einer Schaltung zum Kombinieren einer Vorspannung mit Signalen mit wahlweise variabler Signalverstärkung
DE19844970A1 (de) Schaltungsanordnung zum Mischen eines Eingangssignals und eines Oszillatorsignals miteinander
DE102004030039B3 (de) Mischerschaltung
DE69531088T2 (de) Auswahlvorrichtung zur Wahl elektrischer Zellen und Gerät zur Anwendung einer solchen Vorrichtung
DE3412191A1 (de) Integrierbare empfaengerschaltung
DE1277944B (de) Frequenzumsetzer
EP1527524B1 (fr) Systeme de transmission, en particulier pour la radiotelephonie mobile
DE10210708B4 (de) Mobilfunkgerät mit einer Schaltungsanordnung zur Frequenzumsetzung
DE2646035A1 (de) Verstaerkerschaltung fuer wechselspannung
EP1407416B1 (fr) Circuit multiplicateur

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20040123

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR

RIC1 Information provided on ipc code assigned before grant

Ipc: 7H 03J 1/00 B

Ipc: 7G 06F 7/52 A

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: GERMAN

REF Corresponds to:

Ref document number: 50202182

Country of ref document: DE

Date of ref document: 20050310

Kind code of ref document: P

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20050412

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20050712

Year of fee payment: 4

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20050913

Year of fee payment: 4

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

ET Fr: translation filed
26N No opposition filed

Effective date: 20051103

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070201

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20060703

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20070330

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060731