EP1420409A3 - Datenausgabeschaltung und Verfahren für synchrone ddr-Halbleiterbausteine - Google Patents

Datenausgabeschaltung und Verfahren für synchrone ddr-Halbleiterbausteine Download PDF

Info

Publication number: EP1420409A3
Authority: EP; European Patent Office
Prior art keywords: data; data output; output circuit; semiconductor device; synchronous semiconductor
Prior art date: 2002-11-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

EP03257121A

Other languages

English (en)

French (fr)

Other versions

EP1420409A2 (de

EP1420409B1 (de

Inventor

Nak-Won Heo

Chang-Sik Yoo

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Samsung Electronics Co Ltd

Original Assignee

Samsung Electronics Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-11-18

Filing date

2003-11-12

Publication date

2006-11-22

2003-01-03 Priority claimed from KR10-2003-0000338A external-priority patent/KR100510512B1/ko

2003-11-12 Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd

2004-05-19 Publication of EP1420409A2 publication Critical patent/EP1420409A2/de

2006-11-22 Publication of EP1420409A3 publication Critical patent/EP1420409A3/de

2013-03-20 Application granted granted Critical

2013-03-20 Publication of EP1420409B1 publication Critical patent/EP1420409B1/de

2023-11-12 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch

Landscapes

Dram (AREA)

EP20030257121 2002-11-18 2003-11-12 Datenausgabeschaltung und Verfahren für synchrone ddr-Halbleiterbausteine Expired - Lifetime EP1420409B1 (de)

Applications Claiming Priority (6)

Application Number	Priority Date	Filing Date	Title
US411724		1982-08-26
KR2002071747		2002-11-18
KR20020071747		2002-11-18
KR10-2003-0000338A KR100510512B1 (ko)	2002-11-18	2003-01-03	이중 데이터율 동기식 반도체 장치의 데이터 출력 회로 및그 방법
KR2003000338		2003-01-03
US10/411,724 US7376021B2 (en)	2002-11-18	2003-04-11	Data output circuit and method in DDR synchronous semiconductor device

Publications (3)

Publication Number	Publication Date
EP1420409A2 EP1420409A2 (de)	2004-05-19
EP1420409A3 true EP1420409A3 (de)	2006-11-22
EP1420409B1 EP1420409B1 (de)	2013-03-20

Family

ID=32180322

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP20030257121 Expired - Lifetime EP1420409B1 (de)	2002-11-18	2003-11-12	Datenausgabeschaltung und Verfahren für synchrone ddr-Halbleiterbausteine

Country Status (2)

Country	Link
EP (1)	EP1420409B1 (de)
JP (1)	JP4607444B2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7324564B2 (en) *	2003-02-20	2008-01-29	Sun Microsystems, Inc.	Transmitting odd-sized packets over a double data rate link
JP4600825B2 (ja) *	2005-09-16	2010-12-22	エルピーダメモリ株式会社	半導体記憶装置
KR100705335B1 (ko) *	2005-10-31	2007-04-09	삼성전자주식회사	메모리 장치, 메모리 시스템 및 메모리 장치의 데이터입출력 방법
KR100668499B1 (ko) *	2006-02-09	2007-01-12	주식회사 하이닉스반도체	반도체 메모리 장치의 데이터 출력 회로 및 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP1028427A1 (de) *	1999-02-11	2000-08-16	Infineon Technologies North America Corp.	Hierarchische Vorausladung in Halbleiterspeicheranordnungen
EP1028429A2 (de) *	1999-02-12	2000-08-16	Infineon Technologies North America Corp.	Vorausladearchitektur für Daten- und Taktsignale in einer integrierten Schaltung und Verfahren hierfür

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP3192077B2 (ja) *	1996-01-30	2001-07-23	日本電気株式会社	半導体記憶装置
JP3788867B2 (ja) *	1997-10-28	2006-06-21	株式会社東芝	半導体記憶装置
JP3706772B2 (ja) *	1999-07-12	2005-10-19	富士通株式会社	半導体集積回路
KR100362193B1 (ko) *	1999-11-26	2002-11-23	주식회사 하이닉스반도체	디디알 동기식 메모리 장치의 데이터 출력 장치

2003
- 2003-11-04 JP JP2003373913A patent/JP4607444B2/ja not_active Expired - Fee Related
- 2003-11-12 EP EP20030257121 patent/EP1420409B1/de not_active Expired - Lifetime

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP1028427A1 (de) *	1999-02-11	2000-08-16	Infineon Technologies North America Corp.	Hierarchische Vorausladung in Halbleiterspeicheranordnungen
EP1028429A2 (de) *	1999-02-12	2000-08-16	Infineon Technologies North America Corp.	Vorausladearchitektur für Daten- und Taktsignale in einer integrierten Schaltung und Verfahren hierfür

Also Published As

Publication number	Publication date
EP1420409A2 (de)	2004-05-19
JP2004171743A (ja)	2004-06-17
EP1420409B1 (de)	2013-03-20
JP4607444B2 (ja)	2011-01-05

Legal Events

Date	Code	Title	Description
2004-04-02	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
2004-05-19	17P	Request for examination filed	Effective date: 20031125
2004-05-19	AK	Designated contracting states	Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
2004-05-19	AX	Request for extension of the european patent	Extension state: AL LT LV MK
2004-09-29	RIN1	Information on inventor provided before grant (corrected)	Inventor name: YOO, CHANG-SIK Inventor name: HEO, NAK-WON
2006-10-20	PUAL	Search report despatched	Free format text: ORIGINAL CODE: 0009013
2006-11-22	AK	Designated contracting states	Kind code of ref document: A3 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
2006-11-22	AX	Request for extension of the european patent	Extension state: AL LT LV MK
2007-07-25	AKX	Designation fees paid	Designated state(s): DE GB IT
2008-01-02	17Q	First examination report despatched	Effective date: 20071129
2012-09-26	GRAP	Despatch of communication of intention to grant a patent	Free format text: ORIGINAL CODE: EPIDOSNIGR1
2012-09-26	RAP1	Party data changed (applicant data changed or rights of an application transferred)	Owner name: SAMSUNG ELECTRONICS CO., LTD.
2012-10-24	RIN1	Information on inventor provided before grant (corrected)	Inventor name: HEO, NAK-WON Inventor name: YOO, CHANG-SIK
2013-02-13	GRAS	Grant fee paid	Free format text: ORIGINAL CODE: EPIDOSNIGR3
2013-02-15	GRAA	(expected) grant	Free format text: ORIGINAL CODE: 0009210
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2023-06-28	P01	Opt-out of the competence of the unified patent court (upc) registered	Effective date: 20230520

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