EP1428218A2 - Procede de reconnaissance d'erreurs de memoire dans des systemes de freinage electroniques, ensemble ordinateur et son utilisation - Google Patents

Procede de reconnaissance d'erreurs de memoire dans des systemes de freinage electroniques, ensemble ordinateur et son utilisation

Info

Publication number
EP1428218A2
EP1428218A2 EP02762470A EP02762470A EP1428218A2 EP 1428218 A2 EP1428218 A2 EP 1428218A2 EP 02762470 A EP02762470 A EP 02762470A EP 02762470 A EP02762470 A EP 02762470A EP 1428218 A2 EP1428218 A2 EP 1428218A2
Authority
EP
European Patent Office
Prior art keywords
data
test data
memory
test
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02762470A
Other languages
German (de)
English (en)
Inventor
Wolfgang Fey
Adrian Traskov
Andreas Kirschbaum
Michael Zydek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Continental Teves AG and Co OHG
Original Assignee
Continental Teves AG and Co OHG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Continental Teves AG and Co OHG filed Critical Continental Teves AG and Co OHG
Publication of EP1428218A2 publication Critical patent/EP1428218A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Definitions

  • the invention relates to a computer system according to the preamble of claim 1, a method according to the preamble of claim 8 and the use of a computer system according to claim 17.
  • the reliability of a motor vehicle computer system can also be improved in that when reading flash memories by the microprocessor, parity bits are stored in the same memory module or in a separate memory module for each data line. Parity bits are also generated during the memory access and compared with the stored test data for the purpose of error checking.
  • a line-by-line backup of data in a data store by storing parity bits allows the detection of individual errors for small block sizes (half words / words), but is extremely memory-intensive.
  • the storage space requirement for the parity memory can disadvantageously reach an order of magnitude due to the processing speed in modern processors, which almost corresponds to that of the area to be protected.
  • the invention therefore proposes a computer system according to claim 1 and a method according to claim 8.
  • test data is generated in columns (for example, protection by means of checksums, such as CRC, ECC methods), consumes significantly less chip area.
  • checksums such as CRC, ECC methods
  • the methods mentioned in brackets are particularly suitable for securing larger data blocks and are therefore preferred according to the invention.
  • the proportion of the test data can then be in the range of up to about 10 ⁇ 8 .
  • test data are preferably generated using a CRC or ECC method.
  • test data generating device has the advantage that the data of the program memory can be read at high speed.
  • test data comparison device When accessing the memory, errors are preferably detected by means of a test data comparison device which compares test data generated during reading with stored test data. When an error is detected, suitable safety functions (fail-safe) are triggered, e.g. switching the brake system into an emergency operating state.
  • test data are preferably generated column by column and / or row by row by a parity generator using a test data generating device, these generators being connected in particular to the data bus of the computer system.
  • the program memory is protected by an error detection device.
  • This accesses the data bus and / or the address bus independently or controlled by software. It is equally possible that the independent access is supported by software. It can also be provided that the error detection device tracks the bus traffic initiated by a central processing unit and uses the data collected during the tracking for error detection.
  • the described method for error detection is preferably a combination of a software method with hardware means. This offers the advantage that ' both during the term (“on-line”) and otherwise ("off-line”) a check of the memory can be made.
  • the data in microcomputer systems known per se must disadvantageously be transferred via the data bus to the central processing unit (CPU), as a result of which the data bus is loaded. It is therefore preferably provided to use a central processing unit with an integrated cache.
  • CPU central processing unit
  • an access unit for direct memory access is particularly preferably provided, which further reduces the load on the data bus and the central processing unit.
  • This access unit is in particular connected to its own test data generation device.
  • a central processing unit without an integrated cache it is also possible for a central processing unit without an integrated cache to be used in the embodiment with an access unit.
  • the term computer system generally refers to individual or networked computer systems such as Microcontrollers understood, which in addition to a central processing unit (CPU) additionally include memory and input / output functions. These systems can be “single-core” or, in particular, “multi-core”, wherein in the case of a multi-core system the computer systems comprise two or more central processing units.
  • CPU central processing unit
  • program memory is understood to mean a memory which is primarily intended for read access, such as in particular mask ROMs, flash ROMs, E2PR0MS or OTP ROMs.
  • Test data signature or CRC checksum
  • the block test data can be calculated after compilation and written to the memory together with the program file.
  • the test data are generated, for example, by software using the same method as is later the case when the memory is read by the test data generating device.
  • memory errors are recognized by the fact that when a data word is read from a program memory, line check data are generated from this word at a first point in time. These can be generated and stored in particular during the mass production of the memory, particularly preferably during the production of a mask ROM. When reading, the currently determined line check data are compared with line check data for this word that has already been stored at an earlier point in time. In addition, collected or stored column test data on data words from read operations prior to the first point in time are compared with stored test data for the previously read block.
  • the address decoder is additionally protected. This is done in particular by generating address check data generated in columns, according to one of the methods described above.
  • the address test data are preferably stored in the test data area.
  • test data are stored both in an additional data area of the data memory for the data to be protected and in a further physically separated program memory filed, which is addressed according to the first data memory.
  • the memory is checked by means of a software test. This is started periodically.
  • the central processing unit preferably completely reads out at least one memory block at maximum speed.
  • the test data generating device monitors the data bus and collects all the data of the memory block that is present on the data bus. After reading out the memory block, the calculated block test data are compared with the block data previously stored for this block. In this way, the block test data information associated with the data stream can be calculated without delay.
  • the incorrect data is corrected using the information contained in the test data.
  • the program memory is preferably arranged on-chip, on a multichip module or as a separate chip.
  • the computer system according to the invention is preferably part of an electronic motor vehicle control unit, in particular an electronic controller (ECU), which can be plugged together with a hydraulic brake control unit (HCU) to form a block-shaped assembly.
  • ECU electronic controller
  • HCU hydraulic brake control unit
  • the invention therefore also relates to the use of the computer system described above in electronic control units for motor vehicles, in particular in electronic motor vehicle brake systems. Further preferred embodiments result from the subclaims and the following description of exemplary embodiments with reference to figures.
  • FIG. 1 is a schematic and simplified representation of a computer system according to the invention with an access unit for direct memory access,
  • FIG. 2 shows a further exemplary embodiment for a computer system according to the invention with two test data generation devices
  • Fig. 3 is a schematic representation of a data memory, which is divided into parity memory and signature memory.
  • the central processing unit 1 comprises an integrated cache 2.
  • Central processing unit 1 is connected to mask ROM 4 via data bus 30.
  • a data connection 5 leads from data bus 30 to access unit 6.
  • a data connection 7 leads from access unit 6 to test computer 8.
  • the access unit 6 is preferably a DMA (Direct Memory Access) controller for independent access to the memory without loading the central processing unit.
  • the data are forwarded to test computer 8 via line 7. If an error is detected by test computer 8, an error signal can be output via line 9.
  • the test data are stored together with the data in program memory 4.
  • Program memory 4 can be understood as a table made up of address columns 13 and data columns 14, each address forming a table line together with the data stored at this address. Address column 13 is shown for illustration only and is not physically present. Data memory 14 is divided into data area 15 and redundancy data area 16. Furthermore, data area 14 is in blocks 12 with a block size of typically about 10E2 to 10E5 words.
  • column check data 11 are stored to secure the stored data, which are generated by means of a checksum method (e.g. CRC method). If a Hamming distance method is used as the checksum method, the detection of single and multiple errors or a correction of these errors is possible, which leads to improved availability of the overall system.
  • a checksum method e.g. CRC method
  • the chip area requirement of the computer system according to the invention is particularly low if, according to a preferred embodiment, the test data are accommodated in the program memory itself (i.e. no separate chip, chip area or core). In this case, it is expedient to secure the address decoder using address check data. For this purpose, before the memory is written to for the first time, totals are formed across all program memory addresses of the blocks 12 and are stored in the test data area 10.
  • each read access by parity generator 100 from the current data word on data bus 30 calculates a parity word or bit.
  • Central processing unit 1 simultaneously addresses the required memory location in data memory 20 and parity memory 70 via address bus 21.
  • the parity data are preferably arranged in a separate parity memory 70, but can also be located in a further memory area 60.
  • the parity word or bit is then generated and compared by comparator 90 with the stored parity data 130, 140 (FIG. 3). In the event of an error, a signal is output at output 11 of comparator 90 to a suitable evaluation circuit.
  • central processing unit 1 reads out data block 12 to be read (FIG. 3), the read data being read into signature checking circuit 3 and being ignored by processing unit 1.
  • Circuit 3 independently calculates a CRC sum from the data stream present. After the block has been read out, the calculated CRC sum is compared with the sum permanently stored for the block.
  • FIG. 3 shows an example of the division of program memory 150. This is divided into individual blocks 12 from two data words 80 each 16 bits wide. Block check data 160 are assigned to each block 12. In addition, line check data 130, 140 are provided in a further memory area 70 for each data word assigned to a memory address. Exactly one parity bit is formed for each 16-bit word.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Regulating Braking Force (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Valves And Accessory Devices For Braking Systems (AREA)

Abstract

L'invention concerne un ensemble ordinateur (50) qui comprend au moins une unité centrale (1),et au moins un bus de données (30) relié à l'unité centrale et à des éléments de mémorisation (4, 20, 60, 70) qui comprennent au moins une mémoire de programmes (15, 20) et au moins une mémoire de données de contrôle (16, 60, 70). La mémoire de données de contrôle est une partie (16, 60) de la mémoire de programmes (4, 20) et/ou une partie (70) d'un élément de mémorisation disposé séparément. Au moins un dispositif de génération de données de contrôle (3, 6, 8, 90, 100) sert à l'évaluation et/ou à la mémorisation de données (80) appliquées au bus de données et/ou à la génération de données de contrôle (130, 140, 160). L'invention concerne également un procédé de reconnaissance d'erreurs lors de l'accès à une mémoire de programmes (4, 20). Selon ledit procédé, des données de contrôle qui ont été générées au moyen des données à sécuriser sont déposées, de façon complémentaire, en colonnes, et un dispositif de reconnaissance d'erreurs (3, 6, 8, 90, 100) accède indépendamment au bus de données (30) et/ou au bus d'adresses (21) et/ou suit le trafic de bus déclenché par l'unité centrale (1) et collecte des données.
EP02762470A 2001-09-13 2002-09-04 Procede de reconnaissance d'erreurs de memoire dans des systemes de freinage electroniques, ensemble ordinateur et son utilisation Withdrawn EP1428218A2 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10145227 2001-09-13
DE10145227 2001-09-13
DE10162345 2001-12-18
DE10162345 2001-12-18
PCT/EP2002/009891 WO2003025936A2 (fr) 2001-09-13 2002-09-04 Procede de reconnaissance d'erreurs de memoire dans des systemes de freinage electroniques, ensemble ordinateur et son utilisation

Publications (1)

Publication Number Publication Date
EP1428218A2 true EP1428218A2 (fr) 2004-06-16

Family

ID=26010128

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02762470A Withdrawn EP1428218A2 (fr) 2001-09-13 2002-09-04 Procede de reconnaissance d'erreurs de memoire dans des systemes de freinage electroniques, ensemble ordinateur et son utilisation

Country Status (4)

Country Link
EP (1) EP1428218A2 (fr)
JP (1) JP2005503624A (fr)
DE (1) DE10294299D2 (fr)
WO (1) WO2003025936A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006038428A1 (de) * 2006-08-17 2008-02-21 Bayerische Motoren Werke Ag Verfahren zur Programmierung eines Steuergerätes eines Kraftfahrzeugs
DE102016211124A1 (de) * 2016-06-22 2017-12-28 Robert Bosch Gmbh Verfahren und Vorrichtung zum Bearbeiten von Binärcodedaten

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433388A (en) * 1980-10-06 1984-02-21 Ncr Corporation Longitudinal parity
US5146459A (en) * 1986-11-28 1992-09-08 Canon Kabushiki Kaisha Electronic equipment with check-sum function
DE10018722A1 (de) * 1999-09-22 2001-03-29 Continental Teves Ag & Co Ohg Verfahren und Schaltungsanordnung zum Speichern von Datenworten in einem RAM Modul
DE10029141A1 (de) * 2000-06-14 2001-07-12 Daimler Chrysler Ag Verfahren zur Fehlerüberwachung eines Speicherinhalts mittels Prüfsummen sowie Mikrocontroller mit einem prüfsummengesicherten Speicherbereich

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03025936A3 *

Also Published As

Publication number Publication date
DE10294299D2 (de) 2004-07-22
JP2005503624A (ja) 2005-02-03
WO2003025936A3 (fr) 2004-03-11
WO2003025936A2 (fr) 2003-03-27

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