EP1428367A2 - Modulation hierarchique - Google Patents

Modulation hierarchique

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Publication number
EP1428367A2
EP1428367A2 EP02762167A EP02762167A EP1428367A2 EP 1428367 A2 EP1428367 A2 EP 1428367A2 EP 02762167 A EP02762167 A EP 02762167A EP 02762167 A EP02762167 A EP 02762167A EP 1428367 A2 EP1428367 A2 EP 1428367A2
Authority
EP
European Patent Office
Prior art keywords
data
bit
bits
digital word
mapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02762167A
Other languages
German (de)
English (en)
Inventor
Octavian V. Sarca
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Redline Communications Inc
Original Assignee
Redline Communications Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Redline Communications Inc filed Critical Redline Communications Inc
Publication of EP1428367A2 publication Critical patent/EP1428367A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/3488—Multiresolution systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/183—Multiresolution systems

Definitions

  • the present invention relates to wireless communications and is particularly concerned with modulation schemes for digital data.
  • Fig. 1 shows the typical block diagram of a transmitter for wireless communications.
  • the process that transforms the input data 10 into an RF signal involves scrambling and forward-error-correction (FEC) encoding 12, interleaving 14,
  • FEC forward-error-correction
  • Gray encoding 16 symbol mapping 18, wave mapping, up-conversion and amplification 20.
  • Fig. 2 shows the typical block diagram of corresponding receiver for wireless communications with the transmitter of Fig. 1.
  • the process that transforms the received RF signal into received data in made of the inverses of the operations in the transmit chain, placed in reversed order: amplification, down-conversion, wave de- mapping 22, symbol de-mapping 24, gray decoding 26, de-interleaving 28, FEC decoding and de-scrambling 30.
  • Fig. 2 does not include channel estimation or equalization functions.
  • the scrambler 12 randomizes the input data to remove repetitive and constant sequences, and to ensure a uniform, white-noise like spectrum at the output.
  • the de- scrambler provides the inverse operation, thereby returning the scrambled signal to its original form.
  • Forward-error-correction (FEC) encoding 12 adds redundancy to the input data stream that is used by FEC decoding in the receiver to detect and correct transmission errors.
  • Interleaving 14 spreads the data quasi-randomly in time and, for multi-carrier modulations, in frequency. It also spreads data bits among different modulation levels: c n- ⁇ , ..., ci, c ⁇ Interleaving 14 and de-interleaving 28 ensure that error bursts (errors located close in time or frequency) in the received data are spread in such a way that FEC decoding 30 can correct them with similar performance as uniform errors.
  • Gray encoding 16 maps n binary inputs c n- ⁇ , ..., ci, c 0 into n binary outputs b n- i, ..., bi, bo using formulas:
  • Gray decoding 26 performs the inverse operation using formulas:
  • Gray encoding 16 and decoding 26 ensure that the noise in the received signal causes the minimum number of bit errors. More details are given herein below.
  • Symbol mapping 18 transforms n binary inputs b n- ⁇ , ..., bi, b 0 in one analog output y.
  • Symbol de-mapping 24 performs the inverse operation - it extracts n binary outputs b n _ ⁇ , ..., bj, b 0 from one analog input y. More details are given herein below.
  • Wave mapping 20 takes the stream of symbols y(k) and constructs a baseband signal. Some modulations, usually called quadrature modulations, transform each pair of two real symbols y(2k) and y(2k+l) into a complex symbol
  • Wave de-mapping 22 performs the inverse operation extracting the stream of symbols y(k) from the received baseband signal.
  • the up-conversion shifts 20 the spectrum of the modulated signal from baseband to RF.
  • the down-conversion 22 provides the inverse operation.
  • amplification is needed to obtain the desired power at the antenna.
  • amplification is needed to compensate the losses in the channel and to rise the signal level to the point where the following blocks can process it.
  • Symbol mapping 18 transforms n binary inputs b n- ⁇ , ..., b ⁇ , bo in one analog output y using formula:
  • y (2° xo + 2 1 x, + ... + 2 ⁇ -' x n-1 )/sqrt(2° + 2 2 + ... + 2 2 n'1 )
  • Fig. 3 shows a typical implementation of symbol mapping 18.
  • Fig. 4 shows a typical implementation of symbol de-mapping.
  • Symbol de- mapping 24 performs the inverse operation where n binary outputs b route.
  • the analog input y at input 44 is first multiplied 46 by the weighting factor sqrt(2° + 2 2 + ... + 2 2(n"1) ) at 49 and then passed through an n- bit slicer 50 to produce the bipolar number [x n- ⁇ ...xiXo] at 52.
  • the slicer operation 50 is similar to rounding: it chooses [x n-1 ...x ⁇ x 0 ] to be the closest to y-sqrt(2° + 2 2 + ... + 2 2(n-1) ).
  • the symbol value is shown in first column, the bipolar number in the second, the binary number in third, the Gray- coded bit vector in fourth and the bit vector before Gray coding in fifth.
  • the distance between two consecutive symbols is constant for a given n.
  • the distance between two consecutive symbols depends on n. For each additional bit the distance approximately halves which means that noise sensitivity is worsened by approximately 6dB for each additional bit.
  • Transitions between two consecutive symbols may cause one bit bi to change but may also cause all n bits bj to change (e.g. when [x n- ⁇ ...x ⁇ Xo] changes from -1 to 1). Due to Gray encoding, all one-symbol transitions cause only one bit c,- to change, all two-symbol transitions cause two bits to change and so.
  • the interleaving/de-interleaving scheme is used in an attempt ti mitigate the difference in error probability between levels.
  • the invention describes the method and apparatus to provide hierarchical modulation of data at transmission and hierarchical demodulation of data in the receiver.
  • Hierarchical modulation a number n of distinct data streams are encoded in a single symbol stream and subsequently into a single RF signal.
  • hierarchical demodulation extracts n data streams from the same RF signal.
  • Each data stream will provide a different level of protection against noise and interference.
  • the difference between data streams can be controlled using a single parameter a.
  • Fig. 1 illustrates a block diagram of a known transmitter for wireless data communications
  • Fig. 2 illustrates a block diagram of a known receiver for wireless data communications
  • Fig. 3 illustrates a typical implementation of symbol mapping
  • Fig. 4 illustrates a typical implementation of symbol de-mapping
  • Fig. 5 illustrates a block diagram of a hierarchical transmitter in accordance with an embodiment of the present invention
  • Fig. 6 illustrates a block diagram of a hierarchical receiver in accordance with an embodiment of the present invention
  • Fig. 7 illustrates an implementation of hierarchical symbol mapping of Fig. 5; and Fig. 8 illustrates an implementation of hierarchical symbol de-mapping of Fig. 6.
  • the hierarchical transmitter 60 includes a plurality of data inputs 62a-62n, a plurality of scrambling and FEC encoding blocks 64a-64n, and a plurality of interleaving blocks
  • a wave mapping up-conversion and amplification block 78 converts the analog symbols y to RF for output at 80 to antenna 82.
  • Each of the n input data streams (62a-n) is processed separately through independent scrambling, FEC encoding and interleaving.
  • Scrambling, FEC encoding and interleaving applied to each data stream are functionally similar to the blocks with the same name from known transmitters (Fig.l), except that they each operate on only 1/n-th part of the data.
  • Gray encoding, wave mapping, up-conversion and amplification are functionally similar to the blocks with the same name from known transmitters (Fig.l). Symbol mapping from known transmitters may also be used in a hierarchical transmitter, but an improved hierarchical symbol mapping described herein below is recommended.
  • the hierarchical receiver 90 includes an antenna 92 for receiving an RF signal at 94, an amplification, down-conversion, wave demapping block 96 for deriving a symbol y at 98, a symbol demapping block 100 having a plurality of outputs 102a-102n, a gray decoding block 104 having a plurality of outputs 106a-106n and a plurality of series connected de- interleaving (108a-n), de-scrambler and FEC decoding and data outputs HOa-n.
  • the receiver 90 performs the inverses of the operations in the transmit chain of Fig.
  • the received RF signal 94 is first passed through amplification, down-conversion, wave de-mapping 96, symbol de-mapping 100 and Gray decoding 104.
  • Amplification, down-conversion, wave de-mapping and Gray decoding are functionally similar to the blocks with the same name from known receivers (Fig.2). Symbol de-mapping can be either known or hierarchical depending what is used in the transmitter.
  • the n-bit data stream at the output of Gray-decoding 104 is split into n separate bit streams 106(a-n).
  • Each bit stream is then processed separately through de-interleaving 108(a-n), FEC decoding and de-scrambling 110(a- n) to produce n separate output data streams 112a-n.
  • De-interleaving, FEC decoding and de-scrambling applied to each bit stream are functionally similar to the blocks with the same name from known receivers, except that they each operate on only 1/n- th part of the data.
  • Hierarchical symbol mapping transforms n binary inputs b n- ⁇ , ..., bi, bo in one analog output y using formula:
  • FIG. 7 illustrates a implementation of hierarchical symbol mapping of Fig. 5.
  • the binary vector [b n- ⁇ ...b ⁇ bo] at 72a-72n is first serialized by a block 120 in order b n- ⁇ , ..., b ⁇ ,bo (b n- ⁇ first) at output 122.
  • the register 132 contains zero.
  • the register 132 is clocked n-times (one clock for each bit) before its contents will passed to the second multiplier 142.
  • One can easily verify that the content of the register 142 is x n- ⁇ after the first clock, x n-2 +ax n - ⁇ after the second, x n-3 +ax n-2 +a x n- ⁇ after third and so on up to a 0 xo+a 1 x ⁇ +...+a n"1 x n- ⁇ after n clocks.
  • This result is finally passed through the second multiplier 142 that applies the weighting factor at 144 of l/sqrt(a° + a 2 + ... + a 2(n - 1) ).
  • the hierarchical mapping requires only few low-cost components: one parallel to series converter 120, one adder 128, one register
  • the constant a can be approximated without any impact on the system performance since the same approximation can be used in de-mapping (see below).
  • Fig. 8 illustrates an implementation of hierarchical symbol de-mapping of Fig.
  • Hierarchical symbol de-mapping performs the inverse of the mapping of the transmitter, if operated with the same constant a.
  • the de-mapping extracts n binary outputs b n -i, ..., bi, bo from a single analog input y.
  • the analog input y at 98 is first multiplied 150 by the weighting factor sqrt(a° + a 2 + ... + a 2 1"0 )/a n" ' at input 152.
  • the register 160 and the serial-to-parallel converter 170 must be clocked n times for each input value y.
  • the switch 156 is positioned as depicted allowing the weighted input to be clocked into the register.
  • the switch 156 connects the register 160 input to the second multiplier 166.
  • the 1-bit slicer 162 outputs +1 if its input is greater than zero and -1 otherwise.
  • the slicer will output x n- ⁇ , which is converted to b n- ⁇ by the bipolar-to-binary converter 168 and loaded into the serial-to-parallel converter 170.
  • x n- ⁇ is subtracted at 164 from the register output and the result is multiplied by a at 166.
  • the symbol value is shown in first column, the Gray-coded bit vector in second and the bit vector before Gray coding in third.
  • n and a can be trimmed to obtain the desired number of levels and the desired range, respectively.
  • PAPR peak to average power ratio
  • the number bits is usually chosen adaptively according to the channel characteristics, i.e. to the achievable signal to noise ratio (SNR).
  • SNR signal to noise ratio
  • the receiver replies with an automatic retransmission request (ARQ) for each packet lost.
  • ARQ automatic retransmission request
  • the transmitter estimates the average packet-error-rate (PER) based on the number of ARQ received per quantity of packets sent and adjusts the number of bits per symbol n accordingly.
  • the receiver periodically reports the average SNR to the transmitter. For slowly varying channels both methods gives good and reliable results.
  • n-i provides reliable communication under worst channel conditions
  • these parameters can be used for all transmissions.
  • packets will be transmitted successfully via one or more data streams.
  • the ARQ will still be used to retransmit the unsuccessful packets.
  • retransmissions may only be performed on higher levels in the hierarchy to reduce the number of retransmissions per each particular packet (i.e. to reduce the delay).
  • n and a are chosen ensures that at least one data stream is reliable under all situations and that the bandwidth is effectively and efficiently used.
  • Hierarchical modulation ensures better utilization of the channel because it makes effective use of temporary SNR improvements.
  • Hierarchical modulation provides a smooth degradation of the overall data rate with the degradation of the SNR. This is because, as the SNR degrades, the number of successful data streams decreases. With known non-hierarchical modulation, degradation is sharp. In other words, either all data stream are successful or none.
  • the hierarchical modulation is more reliable than the known modulation because higher levels are better protected to noise.
  • Hierarchical modulation provides more robust error detection. It is known that error detection codes can misdiagnose packets with many errors. With hierarchical modulation, once one level is detected to have errors, all the Tower levels in the hierarchy can be declared unreliable because they are much more sensitive to noise. With known modulation, all levels are mixed together so there is no hierarchy to help the error detection.
  • Hierarchical modulation allows vital (e.g. management and control) information to be sent with higher reliability than data while preserving the nominal data rate (number of bits/symbol).
  • the higher reliability can only be achieved by decreasing the data rate, i.e. the number of bits/symbol.
  • BS base-station
  • SS subscriber-stations
  • the BS must adjust its number of bits per symbol according to the channel to a particular SS, e.g. it will transmit with more bits for near SS's and less bits for far SS's.
  • the vital management and control information is sent in such situations with minimum number of bits/symbol in order to ensure reliable reception by all SS's.
  • the BS will waste precious bandwidth in order to reach the far SS's.
  • the BS can send packets for near stations on lower levels and packets for far stations on higher levels.
  • This we define this as hierarchy- division-multiplexing (HDM).
  • HDM hierarchy- division-multiplexing
  • the BS does not need to decrease the data rate to reach the far SS's since their designated information is encoded in most robust levels of the hierarchy. As the far stations ignore lower levels, it is of no consequence that the lower levels will be received with errors. However, near SS's will be able to decode correctly the lower levels where their designated information is placed.
  • HDM has the following advantages: a) HDM ensures better utilization of the channel because it effectively uses the SNR differences. b) HDM allows vital (e.g. management and control) information to be transmitted with higher reliability without wasting bandwidth. This is because vital information can be encoded in the most reliable level while other levels are used for data. HDM also provides more robustness to burst noise and narrow band interference because the control data is spread both in time and frequency instead of being concentrated. c) HDM is very flexible and permits different combinations of a and n to be chosen according to each particular set of SS's to which the packets are designated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Noise Elimination (AREA)

Abstract

L'invention concerne un procédé et un appareil de modulation hiérarchique de données lors de la transmission et de la démodulation hiérarchique de données dans le récepteur. La modulation hiérarchique permet de coder un nombre n de flots de données distincts en un seul flot de symboles et, par conséquent, en un seul signal RF. Lors de la réception, la démodulation hiérarchique extrait n flots de données du même signal RF. Chaque flot de données fournit un niveau différent de protection contre le bruit et les interférences. La différence entre les flots de données peut être contrôlée au moyen d'un seul paramètre a. La mise en correspondance des symboles hiérarchiques transforme n entrées binaires bn-1, , b1, b0 en une seule sortie analogue y au moyen de la formule : y = (a0xo + a1x1 + + a n-1 xn-1)/sqrt(a?0+a2+ +a 2(n-1)¿) dans laquelle sqrt(.) représente la fonction de racine carrée et chaque x¿i?, i = 0,1, , n-1 est le résultat de la conversion binaire-polaire de bits de données bi définies par xi = 2bi 1 (xi = 1 2bi est également possible) avec bi ⊂ {0,1} et xI ⊂ {-1,1}. L'invention concerne aussi l'application de modulations hiérarchiques aux communications sans fil dans les canaux à changement rapide et aux communications point à multipoint, lesquelles marquent des améliorations significatives par rapport aux autres procédés connus.
EP02762167A 2001-09-13 2002-09-12 Modulation hierarchique Withdrawn EP1428367A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US31867901P 2001-09-13 2001-09-13
US318679P 2001-09-13
PCT/CA2002/001389 WO2003024048A2 (fr) 2001-09-13 2002-09-12 Modulation hierarchique

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050113040A1 (en) 2003-11-26 2005-05-26 Walker Glenn A. Method to minimize compatibility error in hierarchical modulation using variable phase
US7725799B2 (en) * 2005-03-31 2010-05-25 Qualcomm Incorporated Power savings in hierarchically coded modulation
EP2139179A1 (fr) * 2008-06-26 2009-12-30 THOMSON Licensing Procédé et appareil pour le rapport d'informations d'état
US8379769B2 (en) 2010-03-10 2013-02-19 Delphi Technologies, Inc. Communication system utilizing a hierarchically modulated signal and method thereof
FR2969449B1 (fr) * 2010-12-17 2013-03-22 Thales Sa Procede et systeme de transmission utilisant une modulation hierarchique adaptative et programmable
CN104333436A (zh) * 2014-11-04 2015-02-04 杭州电子科技大学 用于分层编码调制的m-qam信号迭代解码方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO03024048A3 *

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Publication number Publication date
WO2003024048A3 (fr) 2003-05-30
AU2002328209A1 (en) 2003-03-24
WO2003024048A2 (fr) 2003-03-20

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