EP1429253A2 - Méthode pour le fonctionnement d'un ordinateur à plusieurs bus mémoire - Google Patents

Méthode pour le fonctionnement d'un ordinateur à plusieurs bus mémoire Download PDF

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Publication number
EP1429253A2
EP1429253A2 EP03257379A EP03257379A EP1429253A2 EP 1429253 A2 EP1429253 A2 EP 1429253A2 EP 03257379 A EP03257379 A EP 03257379A EP 03257379 A EP03257379 A EP 03257379A EP 1429253 A2 EP1429253 A2 EP 1429253A2
Authority
EP
European Patent Office
Prior art keywords
memory
information
channel mode
buses
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03257379A
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German (de)
English (en)
Other versions
EP1429253A3 (fr
EP1429253B1 (fr
Inventor
Cheol-Ho Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of EP1429253A2 publication Critical patent/EP1429253A2/fr
Publication of EP1429253A3 publication Critical patent/EP1429253A3/fr
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Publication of EP1429253B1 publication Critical patent/EP1429253B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Definitions

  • the present invention relates to a method of operating a computer having a plurality of memory buses to determine whether the memory buses can operate in a multi-channel mode.
  • RAM random access memory
  • ROM read only memory
  • RAM is a typical volatile memory, that is data stored therein is lost if power is cut off.
  • ROM is generally used for storing non-changeable data, such as a basic input/output system (BIOS).
  • BIOS basic input/output system
  • ROM is typically non-volatile memory, that is data stored therein is not lost even if power is cut off.
  • Dynamic RAM needs frequent recharging or refreshing to preserve/maintain its contents.
  • a plurality of RAM integrated circuits arranged on a small circuit card are referred to as a "memory module".
  • a currently widespread module type DRAM has an edge connector plug that is inserted into a memory socket connected to a main board or a memory carrier card in a computing device.
  • Some examples of current memory modules are: fast page mode (FPM) modules, extended data out (EDO) modules, synchronous DRAM (SDRAM) modules, Rambus DRAM (RDRAM) modules and double data rate SDRAM (DDR SDRAM) modules.
  • a dual channel mode memory module configuration that theoretically shows a twofold efficiency for same memory capacity as a single channel mode memory module configuration, has been adopted to improve efficiency when using two or more memory modules.
  • the memory modules are separated into two channels and used in parallel, advantageously accomplishing a twofold memory bandwidth using the currently available memory modules.
  • Operation in the dual channel mode is based on the assumption that memory modules connected to the two channels are mutually compatible. Therefore, when critical features of the memory modules connected to the two channel are different, the dual channel mode cannot be performed.
  • memory modules of different manufacturers have features, such as various device structures and logical banks or kinds of memories, which differ from each other and cannot work in the dual channel mode if they are connected to each channel.
  • the memory capacities of respective channels are different, for example a memory capacity of a first channel of 128MB and a memory capacity of a second channel of 64MB, the dual channel mode cannot be performed.
  • a computer operating in the conventional dual channel mode does not have a way of confirming whether the memory system is operating in the dual channel mode.
  • a computer is operating in the dual channel mode, there is a problem that operation efficiency is decreased, in the case that the memory modules are not correctly arranged.
  • a method of operating a computer having a plurality of memory buses to determine whether the memory buses can operate in a multi-channel mode comprising:
  • the method includes, in the event of a negative result to said determination, determining whether the memory modules can be rearranged to support multi-channel operation and, in the event of a multi-channel operation supporting arrangement being determined, displaying an indication of the multi-channel operation supporting arrangement.
  • a computer including display means, a plurality of memory buses and a boot ROM, wherein the boot ROM contains a program for causing the computer to perform a method according to the present invention.
  • boot ROM containing a program for causing a computer to perform a method according to the present invention.
  • an electrical or electromagnetic signal carrying program codes for causing a computer to perform a method according to the present invention.
  • a data carrier carrying a recording of a signal according to the present invention.
  • a computer comprises a CPU, a memory part, an output part and an input part.
  • the output part comprises a video controller controlling a display output to a display apparatus /monitor, and a sound controller controlling audio output to a speaker.
  • the input part comprises an input/output controller, an IDE controller, and a FDD controller, controlling a keyboard, a mouse, a hard disk drive, a CDROM drive and a floppy disk drive, respectively.
  • these structural parts (computer system apparatuses/devices) are mutually connected to one another through a bus, such as a system bus, a PCI bus and a memory bus.
  • the memory part comprises a main memory, a BIOS ROM (also known as a "boot ROM”) and a CMOS RAM.
  • BIOS ROM is a non-volatile memory storing BIOS data concerning the computer.
  • the BIOS which is a built-in software controlling and testing computer system apparatuses, performs a POST (Power On Self Test) to confirm whether the computer system apparatuses operate normally when power is supplied to the computer.
  • the CMOS RAM stores computer system structure data. The BIOS initializes and tests each system apparatus during the POST by comparing system structure data obtained from the POST with the system structure data stored in the CMOS RAM.
  • the main memory comprises a random access memory (RAM).
  • RAM random access memory
  • the main memory comprises a random access memory (RAM).
  • RAM random access memory
  • the memory module circuit card has a plug that inserts into a memory socket connected to a main board or a memory carrier card of the computer system.
  • the memory socket is connected to the memory bus, to thereby allow the memory module to be connected to the memory bus.
  • the RAM arranged on the memory module can be SDRAM (Synchronous DRAM), Rambus DRAM, DDR SDRAM (Double Date Rate SDRAM) or the like.
  • a computer comprises first and second memory buses 11, 12 operated in a multi-channel mode.
  • a controlling part (controller) 20 determines whether the memory buses 11, 12 can be operated in multi-channel mode by comparing memory information relating to at least one of a plurality of memory modules 14a, 14b, 15a, 15b connected to each of the memory buses 11, 12.
  • a displaying part 5, comprising a monitor 5a and a graphics controller 5b, displays whether the memory buses 11, 12 can operate in the multi-channel mode.
  • the multi-channel mode which is a concept in contrast to a single channel mode, has been developed for the following reason.
  • the memory modules 14a, 14b, 15a, 15b are separated into a plurality of channels and used in parallel, thereby providing, for example, a dual channel mode memory bus operation, so that an increased memory bandwidth can be accomplished using the RAM ICs in the memory modules.
  • the two memory buses 11, 12 adapted to be operated in a dual channel mode are illustrated by way of an example, and a larger number of channel memory buses and corresponding memory modules may be configured as a multi-channel RAM.
  • the memory modules 14a, 14b, 15a, 15b are each connected to one or other of the memory buses 11, 12.
  • the first memory bus 11 and the second memory bus 12 extend from a memory controller 10 in parallel.
  • the memory controller 10 controls the first memory bus 11 and the second memory bus 12 according to known multi-channel memory mode techniques. Accordingly, in this case, the memory controller 10 controls the first channel memory bus 11 and the second channel memory bus 12 to operate in a dual-channel mode.
  • the memory modules 14a, 14b connected to the first memory bus 11 will be referred to as "the first channel memory module” and the memory modules 15a, 15b connected to the second channel memory bus 12 will be referred to as "the second channel memory module.”
  • the memory information regarding the first channel memory modules 14a, 14b and the second channel memory modules 15a, 15b comprise SPD (Serial Presence Detect) data stored in each memory module 14a, 14b, 15a, 15b.
  • the SPD data comprises information, such as the device structure of the memory modules 14a, 14b, 15a, 15b, a logic bank, an access speed and a refresh time, stored in a non-volatile memory, such as an EEPROM, provided in each memory module 14a, 14b, 15a, 15b.
  • the memory controller 10 controls access to each memory module 14a, 14b, 15a, 15b using the SPD data.
  • the controlling part 20 determines that the first channel memory bus 11 and the second channel memory bus 12 do not/cannot operate in the dual channel mode, the controlling part 20 transmits this information to the displaying part 5.
  • the displaying part 5 displays the information that the first channel memory bus 11 and the second channel memory bus 12 are not operating/operable in the dual channel mode. If the controlling part 20 determines that the first channel memory bus 11 and the second channel memory bus 12 do/can operate in the dual channel mode, the controlling part 20 transmits this information to the displaying part 5. Accordingly, the displaying part 5 can display that the first channel memory bus 11 and the second channel memory bus 12 do/can operate in the dual channel mode.
  • the controlling part 20 determines that the first channel memory bus 11 and the second channel memory bus 12 are not operable in the dual channel mode, the controlling part 20 looks for the existence of an arrangement of memory modules in which the first channel memory bus 11 and the second channel memory bus 12 can operate in the dual channel mode. If there exists an arrangement of the memory modules enabling operation in the dual channel mode by the first channel memory modules 14a, 14b and the second channel memory modules 15a, 15b, the controlling part 20 transmits such memory module arrangement information regarding the dual channel mode operation to the displaying part 5. Accordingly the displaying part 5 displays memory module arrangement information enabling operation in dual channel mode.
  • the displaying part 5 can display that the first channel memory bus 11 and the second channel memory bus 12 do not/cannot operate in the dual channel mode and that a memory module arrangement enabling the dual channel mode does not exist.
  • a user can obtain memory module arrangement information enabling a dual channel mode by the first channel memory modules 14a, 14b and the second channel memory modules 15a, 15b connected to the first channel memory bus 11 and the second channel memory bus 12.
  • the computer comprises a CPU 1, the main memory 13, a BIOS ROM 4 storing a BIOS, a North Bridge 2 and a South Bridge 3.
  • the North Bridge 2 which is a chipset controlling data transmission between the CPU 1, the main memory 13 and the graphics controller 5b, includes the memory controller 10.
  • the South Bridge 3 is a chipset controlling other devices not controlled by the North Bridge 2.
  • the South Bridge 3 controls a keyboard/mouse controller (not shown), a USB port (not shown) and a PCI bus (not shown) and transmits a booting order received through the North Bridge 2 from the CPU 1 to the BIOS ROM 4.
  • the main memory 13 comprises RAM (Random Access Memory), which is a volatile memory.
  • the RAM is provided as a module-type memory and is connected to the first channel memory bus 11 and the second channel memory bus 12 through corresponding memory sockets.
  • Each RAM IC arranged on the memory modules 14a, 14b, 15a, 15b can be SDRAM (synchronous DRAM), Rambus DRAM or DDR SDRAM (double data rate SDRAM).
  • the first channel memory bus 11 and the second channel memory bus 12 are connected to the memory controller 10 in parallel.
  • the memory controller 10 controls the first channel memory modules 14a, 14b connected to the first channel memory bus 11 and the second channel memory modules 15a, 15b connected to the second channel memory bus 12 so that both the first and second channel memory modules (i.e., both channel memory buses) operate in a dual channel mode.
  • two 64MB memory modules 14a, 14b are connected to the first channel memory bus 11 and two 128MB memory modules 15a, 15b are connected to the second channel memory bus 12.
  • the features of each memory module 14a, 14b, 15a, 15b are the same except for the memory capacity.
  • the BIOS ROM 4 stores the BIOS and includes a setup program used for changing the configuration of the computer system.
  • the BIOS comprises a determining program for determining whether the first channel memory bus 11 and the second channel memory bus 12 can operate and/or are operating in the dual channel mode (i.e. a multi-channel memory mode determiner).
  • the determining program operates during the POST to determine whether the first channel memory bus 11 and the second channel memory bus 12 operate in the dual channel mode.
  • a monitor 5a of the displaying part 5 displays whether the first channel memory bus 11 and the second channel memory bus 12 are operated in the dual channel mode based upon the dual channel mode status (i.e. multi-channel memory mode information) from the determining program.
  • the dual channel mode status i.e. multi-channel memory mode information
  • information about whether the first and second memory modules can operate in dual channel mode as determined by the determining program is transmitted to the graphics controller 5b through the North Bridge 2.
  • the graphics controller 5b controls the monitor 5a to display the received multi-channel memory mode information.
  • BIOS is executed by the booting order of the CPU 1 to perform the POST (operation 41).
  • the CPU 1 reads BIOS data, stores the read BIOS data in the main memory 13 and performs the BIOS initialisation program for fast processing.
  • the CPU 1 executes a determining program (i.e. a channel memory mode determiner) stored in the BIOS ROM 4 (operation 42).
  • a determining program i.e. a channel memory mode determiner
  • the CPU 1 typically executes the determining program by transmitting a predetermined order signal to the BIOS ROM 4 through the North Bridge 2 and the South Bridge 3.
  • the CPU 1 reads the determining program, stores the read determining program in the main memory 13 and executes the determining program from the main memory 13 to thereby increase processing speed.
  • the South Bridge 3 reads SPD data of the first channel memory modules 14a, 14b and the second channel memory modules 15a, 15b and transmits the SPD data to the CPU 1 (operation 43). Subsequently, the determining program determines whether the first channel memory bus 11 and the second channel memory bus 12 can operate in a dual channel mode by comparing the SPD data of the first channel memory modules 14a, 14b with the SPD data of the second channel memory modules 15a, 15b transmitted to the CPU 1 (operation 44). For example, the determining program recognizes the difference between memory capacities of the first channel memory modules 14a, 14b (i.e. 64MB) and the second channel memory modules 15a, 15b (i.e. 128MB) and, thus, determines that the first channel memory bus 11 and the second channel memory bus 12 do not/cannot operate in the dual channel mode.
  • the determining program recognizes the difference between memory capacities of the first channel memory modules 14a, 14b (i.e. 64MB) and the second channel memory modules 15a, 15b (i.e. 128
  • the monitor 5a of the displaying part 5 displays that the first channel memory bus 11 and the second channel memory bus 12 can/do operate in the dual channel mode (operation 45). If the determining program determines that the first channel memory bus 11 and the second channel memory bus 12 cannot operate in the dual channel mode at operation 44, the determining program looks for the existence of an arrangement of the first and second memory modules allowing the first channel memory bus 11 and the second channel memory bus 12 to operate in the dual channel mode (operation 46). For example, the determining program may determine that an arrangement in which on 64MB and one 128MB memory module is connected to each memory bus 1, 2 in corresponding locations is possible and enables dual channel mode.
  • the graphics controller 5b controls the monitor 5a to display the memory module arrangement information enabling the dual channel mode, which is transmitted through the North Bridge 2 to the displaying part 5 (operation 47). If an arrangement of the memory modules enabling the dual channel mode does not exist at operation 46, the graphic controller 5b is controlled to control the monitor 5a to display that the first channel memory bus 11 and the second channel memory bus 12 do not/cannot operate in the dual channel mode, or that an arrangement of the memory modules enabling the dual channel mode does not exist (operation 48).
  • the memory module arrangement information enabling the dual channel mode can be displayed in various forms, such as pictures as well as characters, to see the arrangement of the memory modules enabling the dual channel mode.
  • the controlling part 20 is operated by (i.e., embodied in/implemented as) the determining program (software) stored in the BIOS ROM 4 and a multi-channel mode, such as a dual channel mode, a memory status is determined during the POST, the present invention is not limited to such configuration, and the controlling part 20, which typically is based on an operating system (OS), can be, for example, provided as an application stored in a hard disk drive, so that the controlling part 20 can be executed by a user after booting of the computer.
  • OS operating system
  • the displaying part 5 comprises the monitor 5a
  • the present invention is not limited to such configuration, and any information output apparatus (i.e., a multi-channel memory mode output unit), such as a dedicated LED (Light-Emitting Diode), to inform a user as to whether memory buses are operated in the dual channel mode can be provided. Further, an emitting color of an existing LED can be varied according to whether memory buses are operated in the dual channel mode.
  • a multi-channel memory mode output unit such as a dedicated LED (Light-Emitting Diode)
  • an emitting color of an existing LED can be varied according to whether memory buses are operated in the dual channel mode.
  • the first channel memory bus 11 and the second channel memory bus 12 adapted to be operated in the dual channel mode is described by way of an example, but if 3 or more memory buses controlled by a memory controller are provided, so that the memory buses operate in a multi-channel mode, the controlling part 20 determines whether the 3 or more memory buses can be operated in the multi-channel mode and display multi-channel memory mode information according to the determination via the displaying part 5.
  • memory information of a plurality of channeled memory modules is compared with one another to determine whether a plurality of memory buses connected to the respective channeled memory modules operate according to a multi-channel mode, and to inform a user as to whether the main memory 13 can be operated in the multi-channel mode.
  • the compared memory information may be, for example, manufacturer information, device structure and logical bank information, type information, capacity information, or etc.
  • a memory module arrangement is searched for in which the plurality of the memory buses operate in the multi-channel mode (i.e., a channeled memory module arrangement that allows a multi-channel mode memory bus operation).
  • a user is informed of multi-channel memory mode information, for example, as to whether the memory buses can operate in the multi-channel mode and/or whether there exists a memory module arrangement that allows a multi-channel mode memory bus operation, thereby allowing the user, for example, to rearrange the memory modules.
  • the present invention provides a computer dynamically confirming whether a plurality of memory buses operate in a multi-channel mode, and a control method thereof. Also, if the plurality of the memory buses do not operate in the multi-channel mode, the present invention provides a computer confirming an existence of an arrangement of memory modules enabling the multi-channel mode, and a control method thereof.
  • the processes of the invention embodied in the controlling part 20 of the computer shown in Figure 1 can be implemented in software, for example, as the multi-channel memory mode determiner (the determining program) provided in the BIOS, and/or in computing hardware.
  • a computing device according to the invention comprises data storage, such as magnetic and optical discs, RAM, ROM, etc., on which the processes of the invention can be stored as software and executed to control the computing device according to the invention.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
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EP03257379A 2002-12-13 2003-11-21 Méthode pour le fonctionnement d'un ordinateur à plusieurs bus mémoire Expired - Lifetime EP1429253B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2002079661 2002-12-13
KR1020020079661A KR100929143B1 (ko) 2002-12-13 2002-12-13 컴퓨터 및 그 제어방법

Publications (3)

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EP1429253A2 true EP1429253A2 (fr) 2004-06-16
EP1429253A3 EP1429253A3 (fr) 2006-05-03
EP1429253B1 EP1429253B1 (fr) 2008-02-13

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EP03257379A Expired - Lifetime EP1429253B1 (fr) 2002-12-13 2003-11-21 Méthode pour le fonctionnement d'un ordinateur à plusieurs bus mémoire

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US (1) US7185166B2 (fr)
EP (1) EP1429253B1 (fr)
KR (1) KR100929143B1 (fr)
DE (1) DE60319052T2 (fr)
TW (1) TW200410072A (fr)

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CN111095228A (zh) * 2017-09-29 2020-05-01 英特尔公司 具有一个存储器通道的第一启动

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TW200410072A (en) 2004-06-16
KR20040051956A (ko) 2004-06-19
KR100929143B1 (ko) 2009-12-01
US7185166B2 (en) 2007-02-27
EP1429253A3 (fr) 2006-05-03
US20040117581A1 (en) 2004-06-17
EP1429253B1 (fr) 2008-02-13
DE60319052D1 (de) 2008-03-27
DE60319052T2 (de) 2009-02-12

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