EP1471580A2 - Transistor bipolaire et procédé pour sa fabrication - Google Patents

Transistor bipolaire et procédé pour sa fabrication Download PDF

Info

Publication number
EP1471580A2
EP1471580A2 EP04291043A EP04291043A EP1471580A2 EP 1471580 A2 EP1471580 A2 EP 1471580A2 EP 04291043 A EP04291043 A EP 04291043A EP 04291043 A EP04291043 A EP 04291043A EP 1471580 A2 EP1471580 A2 EP 1471580A2
Authority
EP
European Patent Office
Prior art keywords
layer
base
mesa portion
contact pad
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04291043A
Other languages
German (de)
English (en)
Other versions
EP1471580A3 (fr
Inventor
Junichiro Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of EP1471580A2 publication Critical patent/EP1471580A2/fr
Publication of EP1471580A3 publication Critical patent/EP1471580A3/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/281—Base electrodes for bipolar transistors

Definitions

  • the present invention relates to a semiconductor device having bipolar transistors and a method of producing the same, more particularly relates to a semiconductor device having heterojunction bipolar transistors and a method of producing the same.
  • the transistors used for semiconductor devices may be roughly divided into bipolar transistors and metal oxide semiconductor (MOS) field effect transistors and other field effect transistors.
  • MOS metal oxide semiconductor
  • bipolar transistor is a heterojunction bipolar transistor (HBT).
  • HBT heterojunction bipolar transistor
  • IEICE Technical Reports, ED99-262 discloses a base electrode takeout portion able to lower the capacity between a base and a collector of an InP/InGaAs-based HBT.
  • FIG. 1A is a plane view showing such an HBT
  • FIG. 1B is a cross-sectional view along the line X-X' of FIG. 1A.
  • a substrate 100 of InP has a sub-collector layer 101 of an n + -type InGaAs and forming a collector takeout layer, a collector layer 102 of an n - -type InGaAs, a base layer 103 of a p + -type InGaAs, an emitter layer 104 of an n-type InP, an emitter cap layer (not shown) of an n + -type InP and InGaAs, etc. successively stacked on each other.
  • An emitter electrode 105 is formed connected to the emitter cap layer.
  • the emitter cap layer and the emitter layer 104 are removed in part to form an emitter mesa portion EM.
  • a base electrode 106a is formed connected to the base layer 103.
  • the base layer 103 and the collector layer 102 are formed with a base mesa portion BM.
  • the sub-collector layer 101 is formed with a sub-collector mesa portion SM, while a collector electrode 110 is formed connected to the sub-collector layer 101.
  • a base contact pad base mesa portion PBM comprised of a layer 101a of the same layer as the sub-collector layer 101, a layer 102a of the same layer as the collector layer 102, and a layer 103a of the same layer as the base layer 103 is formed.
  • the base contact pad base mesa portion PBM is formed with a base contact pad electrode 106b.
  • the base layer 103 formed under the base electrode 106a and the layer 103a formed under the base contact pad electrode 106b were originally the same layer, the heights of the surfaces of the two layers are the same, and the base electrode 106a and the base contact pad electrode 106b are connected by an interconnect 106c.
  • the area below the conductive layer 106 between the base mesa portion BM and the base contact pad base mesa portion PBM forms a space SP.
  • the interconnect 106c is formed floating above this.
  • a heterojunction bipolar transistor HBT is formed as described above.
  • An insulating film 108 is formed covering the entire HBT.
  • the insulating film 108 is formed with an emitter contact hole CHe reaching the emitter electrode 105, a base contact hole CHb reaching the base contact pad electrode 106b, and a collector contact hole CHc reaching the collector electrode 110.
  • the emitter contact hole CHe is formed with an emitter contact plug interconnect 109e connected with the emitter electrode 105.
  • the base contact hole CHb is formed with a base contact plug interconnect 109b connected with the base contact pad electrode 106b.
  • the collector contact hole CHc is formed with a collector contact plug interconnect 109c connected with the collector electrode 110.
  • the drawn direction DR of the interconnect 106c is for example made the [001] direction or the [010] direction of an InP crystalline orientation of the substrate due to the following production reasons.
  • a substrate 100 of InP is successively formed with, by a molecular beam epitaxy (MBE) or a metal organic chemical vapor deposition (MOCVD), the n + -type InGaAs as the sub-collector layer 101, the n - -type InGaAs as the collector layer 102, the p + -type InGaAs as the base layer 103, an n-type InP as the emitter layer 104, and an n + -type InP and InGaAs as the emitter cap layer (not shown).
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • a resist film (not shown) is formed in the pattern of the emitter mesa portion EM. This is used as a mask for etching to process the emitter cap layer (not shown) and the emitter layer 105 to the emitter mesa portion EM and to expose the surface of the base layer 103.
  • an emitter electrode 105 is formed by vapor deposition of a conductive layer for example by using the lift-off method and to form a conductive layer 106 comprised of a base electrode 106a, a base contact pad electrode 106b, and an interconnect 106c.
  • the conductive layer 106 is arranged so that the interconnect 106c extends in the [001] direction or the [010] direction of the InP crystalline orientation of the substrate 100 as shown in FIG. 1A.
  • a resist film 107 is formed in the pattern of the base mesa portion BM.
  • the base layer 103 and the collector layer 102 are etched using the resist film 107 as a mask to form the base mesa portion BM.
  • Another resist film (not shown) is formed in the pattern of the sub-collector mesa portion SM. This is used as a mask for etching to process the sub-collector layer 101 to the sub-collector mesa portion SM to isolate the element.
  • a collector electrode 110 is formed on the sub-collector 101 by vapor deposition using the lift-off method for example, an insulating film 108 is formed by CVD etc., a resist film is formed in a pattern of the contact holes, and the insulating film 108 is etched using the resist as a mask by reactive ion etching (RIE) to open an emitter contact hole CHe, a base contact hole CHb, and a collector contact hole CHc.
  • RIE reactive ion etching
  • An object of the present invention is to provide a semiconductor device free of the restrictions on the pattern layout or type of etchant used and able to be produced while suppressing mesa portion-shaped abnormalities and a method of producing the same.
  • a semiconductor device having a semiconductor mesa portion formed on a substrate, including a stack of at least a collector layer, a base layer, and an emitter layer formed in a narrower region compared with the base layer, and functioning as an active region of a bipolar transistor; a base contact pad mesa portion formed on the substrate apart from the semiconductor mesa portion and formed with a height the same as the height of the top surface of the base layer; and a conductive layer formed integrally with a base electrode formed connected to the base layer at part of a region of formation of the base layer other than the region of formation of the emitter layer, a base contact pad electrode formed above the base contact pad mesa portion in a region other than near the edges of the top surface of the base contact pad mesa portion, and an interconnect for connecting the base electrode and the base contact pad electrode.
  • the semiconductor device of the present invention has the base contact pad electrode taken out from the base electrode through the interconnect and has a conductive layer formed integrally with the base electrode formed connected to the base layer at part of the region of formation of the base layer other than the region of formation of the emitter layer, the base contact pad electrode formed above the base contact pad mesa portion, and the interconnect for connecting the base electrode and the base contact pad electrode.
  • the base contact pad electrode is formed at a region other than near the edges of the top surface of the base contact pad mesa portion.
  • a method of producing a semiconductor device having a bipolar transistor including an emitter layer, a base layer and a collector layer on a substrate having the steps of forming a stack of at least a collector layer, a base layer, and an emitter layer on a substrate; patterning the stack to form, separated by a predetermined distance, a semiconductor mesa portion including a stack of at least a collector layer, a base layer, and an emitter layer formed in a narrower region than the base layer and functioning as an active region of a bipolar transistor and a base contact pad mesa portion having the same height as the height of the top surface of the base layer and having a surface layer formed by the same layer as the base layer; forming, between the semiconductor mesa portion and the base contact pad mesa portion, a covering layer having a top surface higher than the height of the top surface of the base layer on the substrate and covering at least up to near the edges of the top surface of the base contact pad mesa portion;
  • the method of producing a semiconductor device of the present invention first forms a stack of at least a collector layer, a base layer, and an emitter layer on the substrate. Next, it patterns the stack to form, a predetermined distance apart, a semiconductor mesa portion including the stack of at least the collector layer, the base layer, and the emitter layer formed in a narrower region than the base layer and functioning as an active region of a bipolar transistor and a base contact pad mesa portion having the same height as the height of the top surface of the base layer and having a surface layer comprised of the same layer as the base layer.
  • a covering layer having a top surface higher than the height of the top surface of the base layer on the substrate and covering at least up to near the edges of the top surface of the base contact pad mesa portion.
  • a conductive layer above the covering layer using the covering layer as a mask and integrally forms a base electrode connected to the base layer at part of the region of formation of the base layer other than the region of formation of the emitter layer, a base contact pad electrode above the base contact pad mesa portion at a region other than near the edges of the top surface of the base contact pad mesa portion, and an interconnect connecting the base electrode and the base contact pad electrode.
  • FIG. 3A is a plane view of a semiconductor device including a heterojunction bipolar transistor according to a first embodiment of the present invention
  • FIG. 3B is a cross-sectional view along the line X-X' of FIG. 3A
  • a semi-insulating substrate 10 comprised of an Fe-doped single crystal InP has successively formed on it a sub-collector layer 11 of a thickness of about 500 nm of an n + -type InP, a collector layer 12 of a thickness of about 500 nm of an n - -type InP, a base layer 13 of a p + -type InGaAs, an emitter layer 14 of a thickness of about 75 nm of an n-type InP, and an emitter cap layer (not shown) of a thickness of about 75 nm of an n + -type InGaAs and functions as an active region of a heterojunction bipolar transistor.
  • the sub-collector layer 11 includes a higher concentration of conductive
  • An emitter electrode 15 is formed connected to the emitter cap layer.
  • the emitter cap layer and the emitter layer 14 are removed in part to form an emitter mesa portion EM.
  • a base electrode 17a is formed connected to the base layer 13, while the base layer 13 and the collector layer 12 are formed with a base mesa portion BM.
  • the sub-collector layer 11 is formed with a sub-collector mesa portion SM, and a collector electrode 18 is formed connected with the sub-collector layer 11. Note that the sub-collector mesa portion SM is a mesa portion for isolating elements.
  • the base contact pad electrode 17b is formed on the base contact pad base mesa portion PBM.
  • the base layer 13 under the base electrode 17a and the layer 13a under the base contact pad electrode 17b are originally formed by the same layer and are the same in heights of the top surfaces.
  • the base electrode 17a and the base contact pad electrode 17b are connected by an interconnect 17c.
  • a base electrode takeout portion is formed for reducing the base-collector capacity.
  • the area between the base mesa portion BM and the base contact pad base mesa portion PBM below the conductive layer 17 forms a space 16a.
  • the interconnect 17c floats above this.
  • the base contact pad base mesa portion PBM and the sub-collector mesa portion PSM are electrically insulated from the transistor part and other elements by the semiinsulating substrate 10, so the capacities of these parts do not become the parasitic capacitance of the transistor.
  • the emitter electrode 15, the conductive layer 17 including the base electrode 17a, and the collector electrode 18 are formed by a stack of Ti/Pt/Au for example.
  • the base contact pad electrode 17b is formed in a region other than near the edges PBMa of the top surface of the base contact pad mesa portion constituted by the base mesa portion PBM. For example, it is formed in a region inside from the edges PBMa of the top surface of the base contact pad base mesa portion PBM in a range of 0.5 to 2 ⁇ m.
  • the base electrode 17a is formed in a region other than the region of formation of the emitter layer 14 and other than near the edges 13b of the base layer 13. For example, it is formed in a region inside from the edges 13b of the base layer 13 in a range of 0.5 to 2 ⁇ m.
  • a heterojunction bipolar transistor HBT is formed as explained above.
  • An insulating film 19 is formed covering the entire HBT.
  • the insulating film 19 is formed with an emitter contact hole CHe reaching the emitter electrode 15, a base contact hole CHb reaching the base contact pad electrode 17b, and a collector contact hole CHc reaching the collector electrode 18.
  • the emitter contact hole CHe is formed with an emitter contact plug interconnect 20e connected with the emitter electrode 15.
  • the base contact hole CHb is formed with a base contact plug interconnect 10b connected with the base contact pad electrode 17b.
  • the collector contact hole CHc is formed with a collector contact plug interconnect 20c connected with the collector electrode 18.
  • the semiconductor device having an HBT according to the present embodiment is configured provided with an external takeout contact pad from the base electrode without increasing the base-collector capacity and can prevent degradation of the high frequency properties of the devices.
  • the height of the top surface of the base contact pad base mesa portion PBM is the same as the height of the top surface of the base mesa portion BM, so it is possible to form an air bridge at the interconnect for taking out the base with a good shape.
  • the base contact pad electrode 17b is formed in the region other than near the edges PBMa of the top surface of the base contact pad mesa portion constituted by the base mesa portion PBM.
  • the base electrode 17a is formed in a region other than the region of formation of the emitter layer 14 and other than near the edges 13b of the base layer 13.
  • the thickness of the interconnect 17c is a thin one of about 0.2 to 0.5 ⁇ m and the strength is insufficient, so if increasing the distance, the interconnect 17c is liable to be damaged. To prevent this, it is preferable to set the distance between the base mesa portion BM and the base contact pad base mesa portion PBM to the above range.
  • a semi-insulating substrate 10 comprised of Fe-doped single crystal InP is successively formed with, by the MBE or the MOCVD, an n + -type InGaAs as the sub-collector layer 11, an n - -type InP as the collector layer 12, a p + -type InGaAs as the base layer 13, an n-type InP as the emitter layer 14, and an n + -type InGaAs as the emitter cap layer (not shown).
  • an emitter electrode 15 is formed on the emitter layer 14 by for example the lift-off method etc.
  • a not shown resist film used for patterning the emitter electrode 15, the emitter electrode 15, etc. is used as a mask to successively process the emitter cap layer and the emitter layer 14 to emitter mesa portion EM. Due to this, the surface of the base layer 13 is exposed.
  • the InGaAs of the emitter cap layer is etched by using a mixture of phosphoric acid, hydrogen peroxide, and water, while the InP of the emitter layer is etched by using a mixture of hydrochloric acid and phosphoric acid.
  • a resist film (not shown) is formed in the pattern of the base mesa portion BM and the base contact pad base mesa portion PBM. This is used as a mask for etching to process the base layer 13 and the collector layer 12 to the base mesa portion BM. Simultaneously, a layer 12a formed by the same layer as the collector layer 12 and a layer 13a formed by the same layer as the base layer 13 are patterned as the base contact pad base mesa portion BM.
  • the InGaAs of the base layer 13 is etched using a mixture of phosphoric acid, hydrogen peroxide, and water, while the InP of the collector layer 12 is etched using a mixture of hydrochloric acid and phosphoric acid.
  • a resist film (not shown) is formed in a pattern of the sub-collector mesa portion SM and the base contact pad sub-collector mesa portion PSM. This is used as a mask for etching to process the sub-collector layer 11 to the sub-collector mesa portion SM and isolate the elements. Simultaneously, the layer 11a formed by the same layer as the sub-collector layer 11 is patterned to form the base contact pad sub-collector mesa portion PSM. In the same way as the above, for example, the InGaAs of the sub-collector layer 11 is etched using a mixture of phosphoric acid, hydrogen peroxide, and water.
  • a resist film 16 is patterned on the substrate 10 as a covering layer having a top surface higher than the height of the top surface of the base layer 13 so as to cover at least up to near the edges PBMa of the top surface of the base contact pad base mesa portion PBM (region of 0.5 to 2 ⁇ m from the edges PBMa) and cover up to near the edges 13b of the base layer 13 (region of 0.5 to 2 ⁇ m from the edges).
  • a base contact pad electrode 17b above the base contact pad base mesa portion in the region other than near the edges PBMa of the top surface of the base contact pad base mesa portion PBM, and an interconnect 17c connecting the base electrode 17a and the base contact pad electrode 17b are integrally formed.
  • the resist film 16 is removed. Due to this, the area below the conductive layer 17 between the semiconductor mesa portion of the emitter mesa portion EM, the base mesa portion BM, and the sub-collector mesa portion SM and the base contact pad mesa portion constituted by the base mesa portion PBM and the sub-collector mesa portion PSM forms a space 16a and becomes an air bridge structure.
  • a collector electrode 18 is formed on the sub-collector layer 11 by vapor deposition using for example the lift-off method.
  • a heterojunction bipolar transistor HBT is formed by the above.
  • CVD is used to deposit silicon oxide over the entire surface covering the entire HBT to form an insulating film 19.
  • part of the insulating film is formed sneaking into the space 16a under the interconnect 17c, but it is possible to prevent the film from sneaking into and leave the space as it is depending on the film-forming conditions.
  • CVD etc. is used to form an insulating film 19
  • a resist film is formed in the pattern of the contact holes, and the insulating film is etched by reactive ion etching (RIE) to form the emitter contact hole CHe, the base contact hole CHb, and the collector contact hole CHc.
  • RIE reactive ion etching
  • the contact holes are formed with a contact plug interconnect 20e, a contact plug interconnect 20b, and a contact plug interconnect 20c.
  • the height of the top surface of the base contact pad base mesa portion PBM is the same as the height of the top surface of the base mesa portion BM, it is possible to form an air bridge of the interconnect for taking out the base in a good shape. Further, since the mesa shape is formed without etching utilizing the side etching property based on the crystalline orientation of the substrate, then a conductive layer 17 integrally formed of a base electrode 17a, a base contact pad electrode 17b, and an interconnect 17c is formed, there is no restriction on the pattern layout, the type of the etchant used, etc.
  • FIG. 5 is a cross-sectional view of a semiconductor device having a heterojunction bipolar transistor according to a second embodiment of the present invention.
  • the semiconductor device of the second embodiment is similar to the semiconductor device of the first embodiment, but differs in the point that a silicon oxide or other insulating film 16b is formed in the space formed below the conductive layer 17 between the semiconductor mesa portion of the emitter mesa portion EM, the base mesa portion BM, and the sub-collector mesa portion SM and the base contact pad mesa portion constituted by the base mesa portion PBM and the sub-collector mesa portion PSM.
  • the semiconductor device according to this embodiment can be produced in substantially the same way as the first embodiment.
  • a silicon oxide or other insulating film 16b is formed as a covering layer.
  • the conductive layer 17 using the covering layer as a mask above the covering layer is formed above the insulating film 16b using the insulating film 16b as a mask.
  • etching since there is no etching utilizing the side-etching property based on the crystalline orientation of the substrate, there is no restriction on the pattern layout, type of etchant used, etc.
  • etching for forming a base mesa portion etching is possible in a state with no step difference possibly causing mesa portion-shaped abnormalities and the occurrence of mesa portion-shaped abnormalities can be suppressed.
  • the present invention is not limited to the above embodiments.
  • a base mesa portion PBM and sub-collector mesa portion PSM are used as the base contact pad mesa portion, but the invention is not limited to this. It is also possible to form a new mesa portion for the base contact pad.
  • the height of the top surface of the base contact pad mesa portion has to be designed to become the same as the height of the top surface of the base layer.
  • the base electrode 17a does not necessarily have to be formed in the region other than the region of formation of the emitter layer 14 and other than near the edges 13b of the base layer 13.
  • the base contact pad electrode 17b is formed in a region other than near the edges PBMa of the top surface of the base contact pad mesa portion constituted by the base mesa portion PBM.
  • the structure becomes easier to produce by also forming the base electrode 17a in a region other than near the edges 13b of the base layer 13.
  • the explanation was given with reference to an npn-type bipolar transistor, but the invention can also be applied to a pnp-type bipolar transistor.
  • the shapes of the mesa portion of the stack of the collector layer, the base layer, and the emitter layer, the arrangement of the electrodes connected to the different layers, etc. are not limited to the above embodiments. Other shapes and arrangements may also be employed.
  • the present invention is not limited to heterojunction bipolar transistors and may be applied to semiconductor devices having other bipolar transistors as well.
  • the semiconductor device of the present invention can be produced without restriction as to the pattern layout, type of etchant used, etc. and while suppressing mesa portion-shaped abnormalities.
  • the method of producing a semiconductor device of the present invention it is possible to produce a semiconductor device without restriction as to the pattern layout, type of etchant used, etc. and while suppressing mesa shape abnormalities.

Landscapes

  • Bipolar Transistors (AREA)
EP04291043A 2003-04-24 2004-04-22 Transistor bipolaire et procédé pour sa fabrication Withdrawn EP1471580A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003120393 2003-04-24
JP2003120393A JP2004327717A (ja) 2003-04-24 2003-04-24 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
EP1471580A2 true EP1471580A2 (fr) 2004-10-27
EP1471580A3 EP1471580A3 (fr) 2005-06-01

Family

ID=32959672

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04291043A Withdrawn EP1471580A3 (fr) 2003-04-24 2004-04-22 Transistor bipolaire et procédé pour sa fabrication

Country Status (6)

Country Link
US (2) US20040211978A1 (fr)
EP (1) EP1471580A3 (fr)
JP (1) JP2004327717A (fr)
KR (1) KR20040092404A (fr)
CN (1) CN1309089C (fr)
TW (1) TWI237392B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007058265A1 (ja) * 2005-11-18 2009-05-07 独立行政法人科学技術振興機構 バイポーラトランジスタ及びその製造方法
CN105668602A (zh) * 2016-04-07 2016-06-15 安徽江东科技粉业有限公司 超细碳酸钙的制备方法
JP2019033199A (ja) * 2017-08-09 2019-02-28 株式会社村田製作所 半導体装置
JP2020098865A (ja) * 2018-12-18 2020-06-25 株式会社村田製作所 半導体装置
JP2020184580A (ja) * 2019-05-08 2020-11-12 株式会社村田製作所 半導体装置
WO2022049752A1 (fr) * 2020-09-07 2022-03-10 日本電信電話株式会社 Transistor bipolaire à hétérojonction et son procédé de fabrication

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US15474A (en) * 1856-08-05 William s
US3809889A (en) * 1972-12-29 1974-05-07 Gen Electric Image intensifier compensated for earth{40 s magnetic field
US4000432A (en) * 1975-07-25 1976-12-28 Varian Associates Magnetic shield for image intensifier tube
US4328418A (en) * 1980-04-10 1982-05-04 Picker Corporation Magnetic field correction method and apparatus
US5268315A (en) * 1992-09-04 1993-12-07 Tektronix, Inc. Implant-free heterojunction bioplar transistor integrated circuit process
US5471078A (en) * 1992-09-09 1995-11-28 Texas Instruments Incorporated Self-aligned heterojunction bipolar transistor
US5734193A (en) * 1994-01-24 1998-03-31 The United States Of America As Represented By The Secretary Of The Air Force Termal shunt stabilization of multiple part heterojunction bipolar transistors
FR2726125A1 (fr) * 1994-10-25 1996-04-26 Thomson Csf Composant semiconducteur a transistors bipolaires, stabilises thermiquement
JP4018165B2 (ja) * 1995-05-19 2007-12-05 株式会社東芝 Ｘ線イメージ管装置
DE19615456A1 (de) * 1996-04-19 1997-10-23 Philips Patentverwaltung Verfahren zur Detektion und Korrektur von Bildverzerrungen bei der Computertomographie
KR100257192B1 (ko) * 1998-01-26 2000-05-15 구자홍 이종접합 바이폴라 트랜지스터
US6379043B1 (en) * 1998-12-08 2002-04-30 U.S. Philips Corporation X-ray examination apparatus and method for generating distortion-free X-ray images
DE19856537A1 (de) * 1998-12-08 2000-06-15 Philips Corp Intellectual Pty Verfahren zur intraoperativen Kalibration von C-Bogen Röntgenanordnungen
FR2805081B1 (fr) * 2000-02-14 2002-10-11 Cit Alcatel Procede de fabrication de transistor bipolaire a double heterojonction sur materiau iii-v
US6680791B2 (en) * 2001-10-01 2004-01-20 The Board Of Trustees Of The Leland Stanford Junior University Semiconductor device for rapid optical switch by modulated absorption
US6605825B1 (en) * 2002-02-14 2003-08-12 Innovative Technology Licensing, Llc Bipolar transistor characterization apparatus with lateral test probe pads
US6924203B2 (en) * 2003-05-27 2005-08-02 Northrop Grumman Corporation Double HBT base metal micro-bridge
US6870184B2 (en) * 2003-07-30 2005-03-22 Innovative Technology Licensing, Llc Mechanically-stable BJT with reduced base-collector capacitance

Also Published As

Publication number Publication date
EP1471580A3 (fr) 2005-06-01
CN1540765A (zh) 2004-10-27
TWI237392B (en) 2005-08-01
JP2004327717A (ja) 2004-11-18
US20070243689A1 (en) 2007-10-18
CN1309089C (zh) 2007-04-04
TW200425506A (en) 2004-11-16
US20040211978A1 (en) 2004-10-28
KR20040092404A (ko) 2004-11-03

Similar Documents

Publication Publication Date Title
EP0747964B1 (fr) Transistor bipolaire à hétérojonction submicrométrique entièrement auto-aligné et sa méthode de fabrication
US20010023947A1 (en) Ultra high speed heterojunction bipolar transistor having a cantilevered base
US20070243689A1 (en) Semiconductor device having semiconductor and base contact pad mesa portions
US5296733A (en) Hetero junction bipolar transistor with improved electrode wiring contact region
US6870184B2 (en) Mechanically-stable BJT with reduced base-collector capacitance
JP4288852B2 (ja) バイポーラトランジスタの製造方法
US7679105B2 (en) Hetero junction bipolar transistor and method of manufacturing the same
US6924203B2 (en) Double HBT base metal micro-bridge
EP0362104A1 (fr) Technologie pour circuit intégré de transistors bipolaires
WO2007058265A1 (fr) Transistor bipolaire et son procede de fabrication
US5387808A (en) Heterojunction bipolar transistors with sloped regions
JP4026347B2 (ja) 化合物半導体バイポーラトランジスタの製造方法
KR100497840B1 (ko) 이종접합 바이폴라 트랜지스터의 제조방법, 그에 의해제조된 이종접합 바이폴라 트랜지스터
JPH0588541B2 (fr)
US7282418B1 (en) Method for fabricating a self-aligned bipolar transistor without spacers
JP2007273538A (ja) ヘテロ接合バイポーラトランジスタ及びその製造方法
JP3244795B2 (ja) 半導体装置の製造方法
US20040159911A1 (en) Method for fabricating base-emitter self-aligned heterojunction bipolar transistors
JP2006344884A (ja) ヘテロ接合型半導体装置及びその製造方法
JP3536840B2 (ja) 半導体装置の製造方法
KR100198425B1 (ko) 폴리이미드를 이용한 이종접합 바이폴라 트랜지스터의 제조방법
EP1134809A2 (fr) Transistor bipolaire à hétérojonction à ultra haute vitesse ayant une base en porte à faux
JPH0645345A (ja) エミッタ電極引出し配線およびその作製方法
JP4930269B2 (ja) 化合物半導体バイポーラトランジスタ
KR20080052195A (ko) 측벽을 이용한 이종접합 바이폴라 트랜지스터 제조방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL HR LT LV MK

17P Request for examination filed

Effective date: 20051123

AKX Designation fees paid

Designated state(s): DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20081104