Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01332—Making the insulator
  • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
  • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/86—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of Schottky-barrier gate FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0277—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming conductor-insulator-semiconductor or Schottky barrier source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
  • H10D64/647—Schottky drain or source electrodes for IGFETs

Definitions

• the present invention generally relates to the field of semiconductor systems and manufacturing processes. More particularly, the present invention relates to semiconductor integrated circuits (ICs) having Schottky barrier Metal- Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs) including Schottky barrier P-type MOSFETs (PMOS), N-type MOSFETs (NMOS) and/or Schottky barrier complimentary MOSFETs (CMOS), and the manufacturing processes thereof.
• MOSFETs Metal- Oxide-Semiconductor-Field-Effect-Transistors
• PMOS Schottky barrier P-type MOSFETs
• NMOS N-type MOSFETs
• CMOS Schottky barrier complimentary MOSFETs
• CMOS Complementary Metal-Oxide-Semiconductors
• Current CMOS technology allows for the cost- effective fabrication of integrated circuits with over 100 million components - all on a piece of silicon roughly 10mm on a side.
• the one billion transistor IC will be commercially available within a few years.
• the desire for greater functionality and performance at less cost per IC drives several trends.
• the channel length is a distance that charge carriers travel to pass through the device, and a reduction in this length simultaneously implies higher current drives, reduced parasitic resistances and capacitances and improved high-frequency performance.
• MOS transistors behave like switches. When 'on', they drive relatively large amounts of current and when turned 'off they are characterized by a certain amount of leakage current.
• a common CMOS inverter circuit comprising an NMOS and PMOS device connected in series, dissipates appreciable power only during switching transients. Otherwise, the quiescent power dissipation, or the power dissipated by the CMOS circuit when idle, is a strong function of MOSFET leakage current, and significantly affects the overall circuit power dissipation for most applications. As channel lengths are reduced, drive current increases, which is beneficial for circuit performance as stated above. However, leakage current increases as well. Leaky transistors contribute to quiescent power dissipation and in extreme cases can affect the transfer of binary information during active operation. Device designers therefore have good reason to keep MOSFET leakage currents low as channel lengths are reduced.
• Yield is the ratio of functioning devices to the total number of devices on a fabricated substrate.
• Process yield is a strong function of the total number of processing steps. For example, if the average yield per process step is 99.5% and a complete
• CMOS process has 50 processing steps, then the process yield is approximately 90%.
• the manufacturing cost of a CMOS process is a strong function of the process yield, increasing as process yield decreases.
• a simple metric that characterizes the manufacturing complexity and therefore cost of a CMOS technology is the total number of mask steps, each of which contains a series of photoresist procedures, mask alignments, lithography exposures, etching steps, cleaning and metrology. Reducing the number of mask steps in a CMOS process directly reduces manufacturing cost by reducing the total number of process steps and additionally by increasing yield.
• MOS transistor design and architecture, and CMOS manufacturing processes there are only limited solutions to the trade-off between drive current, leakage current, parasitic capacitance and resistance, and manufacturing complexity and cost.
• the present invention offers a new relationship between these competing requirements, and makes possible MOS devices and CMOS-based integrated circuits with characteristics that are not achievable with traditional (impurity doped) MOS architectures.
• the use of metal for the source and drain provides for improvements to device characteristics in terms of reduced parasitic capacitance, reduced statistical variations in these characteristics (especially as the channel length is decreased) and reduced manufacturing cost and complexity.
• FIG. 1 illustrates an exemplary long-channel conventional MOS device (100) that comprises an impurity doped source (101), an impurity doped drain (102), a conventional MOS type gate stack (103), and a laterally uniform channel doping profile (104) in the substrate to assist in the control of source-to-drain leakage currents.
• Devices are electrically isolated from each other via a field oxide (105).
• Such channel dopant profiles are common in devices with channel lengths down to approximately 200 nanometers (nm).
• the exemplary short-channel MOS device (200) has some elements similar to the long-channel MOS device (100).
• the structure comprises a conventional impurity doped source (201) and drain (202) as well as a conventional MOS gate stack (203) (width ⁇ -100 nm, corresponding to the channel length L).
• the structure further comprises shallow, impurity doped extensions for the source (208) and drain (209) electrodes which are used in conjunction with drain (206) and source (207) pocket doping as well as conventional channel doping (204) to control source to drain leakage currents.
• Source and drain electrodes (201) and (202) and their respective extensions (208) and (209) are all of the same doping polarity (either N-type or P-type) and are of the opposite polarity from the channel (204) and pocket doping elements (206) and (207). Again, a field oxide
• a typical CMOS inverter circuit 300 is a P-type MOSFET device 301 and an N-type MOSFET device 302 connected in series fabricated on a lightly doped P-type epitaxial semiconductor layer 331 on a heavily doped semiconductor substrate 330.
• 303,305 contacts comprise impurity doped source 304, 306 and drain 303, 305 electrodes, shallow impurity doped source 316, 318 and drain 315, 317 extensions, pocket doping 345, 346 and channel and substrate doping 347, 348.
• the drain contacts 303,305 of the two devices 301, 302 are connected, the source 304 of the P-type device 301 is connected to a supply voltage V dd 307, the source
• N-type device 306 of the N-type device 302 is connected to a lower voltage N ss 308, usually ground, and the gates 309, 310 of the two devices 301, 302 have a common connection N g 311.
• the PMOS 301 and ⁇ MOS 302 devices are isolated by a field oxide 320 and an ⁇ -type well implant 321 for the PMOS device, and the ⁇ - type well implant 321 is electrically connected via a heavily doped ⁇ -type ohmic contact 340 to V dd 307.
• the output voltage V 0 312 at the common drain connection depends on the input voltage at the gate N g 311.
• V g 311 is high (usually V dd 307), then the ⁇ -type device 302 is "on” and the P-type device 301 is “off. That is, a channel region 313 of the ⁇ -type device 302 conducts while a channel region 314 of the
• P-type device 301 does not conduct. The result being that the output voltage V 0 312 changes to that of the ⁇ -type source 306, or V ss 308. The opposite occurs when V g 311 is low (usually V ss 308). The ⁇ -type device 302 is now “off and the P-type device 301 "on", and the output voltage V 0 312 changes to that of the P-type source 304, or V dd 307.
• a high (low) input voltage V g 311 produces a low (high) output voltage V 0 312, effectively providing an inverting function.
• One exemplary characteristic of this typical CMOS inverting circuit is that appreciable current only flows during switching of the input voltage V g 311 from high to low or low to high.
• Schottky Barrier CMOS In U.S. Pat. No. 5,760,449, Welch discloses a Schottky barrier transistor device system having N-channel and P-channel MOSFETS connected in series, in which source junctions, not drain junctions, of the N- and P-type devices are electrically interconnected, and which uses a mid-gap chromium silicide to form the Schottky barrier source and drain regions of both N- and P-type devices.
• a mid-gap silicide such as chromium silicide is characterized by a Fermi level that attaches close to the mid band gap for silicon at approximately 0.56 eV.
• Welch refers to the resulting circuit as a "single device equivalent to CMOS" because the CMOS device is fabricated on a single doping type semiconductor substrate and uses identical metal silicide to form the source and drain regions of both transistors. Both transistors of the device are identical, as compared to conventional CMOS devices in which complimentary opposite-type N- and P- type transistors are used together. Further, Welch teaches that the device demonstrates regenerative inverting switching characteristics. As the device switches, the source voltage changes (not the drain as in a conventional CMOS inverter), thereby increasing the potential difference from gate to source, thereby "regeneratively” or additionally turning the device “on,” until the switching is complete.
• the prior art does not disclose or teach a Schottky barrier, metal source/drain CMOS device or a fabrication process for the Schottky barrier, metal source/drain CMOS device.
• Device isolation To fabricate integrated circuits, individual transistor devices must be isolated from one another in order to allow each device to operate independently of other devices in the circuit. Optimal device isolation technologies have high density, reasonable process complexity, high yield, and acceptable parasitic effects. Device isolation divides the semiconductor substrate into regions of two types. A first region has an exposed semiconductor surface and is denoted as an active region - a region in which the transistors are fabricated. A second region comprises a "field oxide" that masks the semiconductor substrate and is denoted as a field region - a region in which no devices are fabricated.
• LOCOS local oxidation of silicon
• STI shallow trench isolation
• LOCOS and STI have been optimized for advanced CMOS technologies, they suffer from several integration challenges. Examples of a few LOCOS challenges include stress of the silicon substrate induced during the oxidation process, the white ribbon nitride effect, and the existence of the so-called bird's beak phenomena. Although solutions exist for most of these challenges, they add complexity to the manufacturing process or limit the process flexibility.
• Silicide Exclusion Mask Process Silicides conventionally are provided for across an entire semiconductor substrate.
• silicides may detrimentally affect circuit performance for some applications such as active CMOS pixel arrays (increased photodiode dark current and opaqueness) or analog circuits (degrade signal integrity, aggravate circuit stress, affect threshold voltage offset and junction leakage).
• a silicide exclusion mask process has been developed in the prior art to selectively mask portions of the semiconductor substrate to prevent silicides from forming in the masked regions. See for example U.S. Patent 6,160,282, in which Merrill discloses a silicide exclusion mask process to improve performance of an active CMOS pixel array and U.S. Patent 5,883,010 in which Merrill discloses a spacer oxide mask process to provide silicide exclusion.
• a silicide exclusion mask process typically comprises deposition of a silicide exclusion oxide mask layer, deposition of photoresist, patterning of the photoresist, etching the silicide exclusion oxide mask layer so that regions covered by photoresist and oxide are protected from silicide formation and that regions to be silicided are exposed, stripping the photoresist layer, selectively forming silicide metal layers on silicon surfaces exposed by the silicide exclusion oxide mask pattern, and removing the silicide exclusion oxide mask layer.
• the silicide exclusion mask technique has not been used to fabricate Schottky barrier
• a CMOS device comprising a Schottky barrier NMOS device optionally having P-type channel dopants and a Schottky barrier PMOS device optionally having N-type channel dopants.
• the channel dopants and/or well implants may or may not be electrically contacted by ohmic contacts.
• the devices may be separated by a field oxide, optionally an oxide window not substantially recessed into the semiconductor substrate.
• a simple non-recessed oxide window is provided as the field oxide.
• Channel and/or well implants are further introduced to isolate N-type and P-type active regions.
• a gate electrode for an NMOS device is formed in the N- type active region and a gate electrode for a PMOS device is formed in the P-type active region, the gate electrodes having a thin electrically insulating sidewall spacer.
• a silicide exclusion mask is used to prevent formation of silicide in the P- type active region while exposing the N-type active region. When the exclusion mask layer is patterned using a wet chemical etch, the exclusion mask layer etch rate is greater than the NMOS device sidewall spacer etch rate.
• Schottky-like contact is formed by reacting a thin metal layer with the exposed semiconductor substrate at least in areas adjacent to the NMOS gate electrode.
• a silicide exclusion mask is used to prevent formation of silicide in the N-type active region while exposing the P-type active region.
• the exclusion mask layer etch rate is greater than the PMOS device sidewall spacer etch rate.
• a Schottky or Schottky-like contact is formed by reacting a thin metal layer with the exposed semiconductor substrate at least in areas adjacent to the PMOS gate electrode.
• FIG. 1 illustrates a prior art long channel, impurity doped source/drain device
• FIG. 2 illustrates a prior art short channel, impurity doped source/drain device with pocket implants and source/drain extensions
• FIG. 3 illustrates a prior art short channel, impurity doped source/drain CMOS inverter circuit
• FIG. 4 illustrates the definitions of channel length and channel region
• FIG. 5 illustrates a CMOS device according to one embodiment of the present invention .
• FIG. 6 illustrates an exemplary embodiment of the present invention process using implantation of the P-type device active region
• FIG. 7 illustrates an exemplary embodiment of the present invention process using implantation of the N-type device active region
• FIG. 8 illustrates an exemplary embodiment of the present invention process using a formation of a LOCOS field oxide for device isolation
• FIG. 9 illustrates an exemplary embodiment of the present invention process using a patterned silicon film on thin gate oxide
• FIG. 10 illustrates an exemplary embodiment of the present invention process using a formation of thin oxide sidewalls, and exposure of silicon in the gate, source and drain areas;
• FIG. 11 illustrates an exemplary embodiment of the present invention process using a silicide exclusion mask and a metal deposition and silicidation anneal of the N-type device and using a removal of unreacted metal
• FIG. 12 illustrates an exemplary embodiment of the present invention process using a silicide exclusion mask and a metal deposition and silicidation anneal of the P-type device and using a removal of unreacted metal
• FIG. 13 illustrates an exemplary embodiment of the resulting structure of the present invention process
• FIG. 14 illustrates an exemplary embodiment of a Schottky barrier CMOS inverter circuit having PMOS and NMOS devices connected in series with a simple thin field oxide and well implants not electrically contacted via ohmic contacts, in accordance with the principles of the present invention
• FIG. 15 illustrates an exemplary embodiment of a layout of the Schottky barrier CMOS inverter circuit having PMOS and NMOS devices connected in series, in accordance with the principles of the present invention.
• FIG. 5 shows an exemplary embodiment of the present invention, as exemplified by two final complementary MOSFET structures 500.
• This embodiment comprises a Schottky barrier N-channel device fabricated with Erbium Silicide 504 for the source/drain regions, and a Schottky barrier P-channel device fabricated with Platinum Silicide 505.
• Indium 502 and Arsenic 503 layers may be used as the channel dopants for the N-channel and P-channel devices respectively.
• the gate electrodes are fabricated from in-situ Phosphorous and
• An ohmic contact is a low resistivity electrical contact to a semiconductor substrate.
• impurity-doped ohmic contacts comprise an N-type heavily doped region in contact with an N-type doped semiconductor substrate or a P-type heavily doped region in contact with a P-type doped semiconductor substrate.
• metal ohmic contacts to semiconductor substrate comprise Erbium silicide in contact with an N-type doped semiconductor substrate or Platinum silicide in contact with a P-type doped semiconductor substrate. The contacts that these metal silicides make with their respective semiconductor substrate types are ohmic because of their low Schottky barrier heights to charge carriers and thus low contact resistance.
• CMOS layout typically includes N- and P-type well implants for the P- and N-type MOSFET devices respectively.
• the N- and P-type well implants are electrically contacted via ohmic contacts to V dd and ground power supplies respectively.
• an N-well 321 is doped with the opposite polarity of that of the semiconductor substrate 330, typically with a doping concentration approximately one order of magnitude greater than the epitaxial substrate layer 331.
• a heavily doped N-type ohmic contact 340 is provided in direct contact with the N-well 321, and is electrically connected to the supply voltage V d , while the substrate 330 is connected to V ss , typically ground.
• Channel Length is provided in direct contact with the N-well 321, and is electrically connected to the supply voltage V d , while the substrate 330 is connected to V ss , typically ground.
• the channel length (L) 401 is a distance that charge carriers travel in the semiconductor substrate 415 to pass from the source electrode 402 to the drain electrode 403.
• this length is defined by the distance from the interface 404 of the source electrode 402 facing the drain electrode 403, to the interface 405 of the drain electrode 403 facing the source electrode 402, just below the gate insulator 406.
• Channel Region, Channel Dopant and Substrate Dopant Referencing FIG. 4, the current-carrying region of the active region is often referred to as the channel region in a semiconductor device.
• the channel region in the semiconductor substrate 415 is located very near the gate insulator 406, and does not extend substantially vertically down into the semiconductor substrate 415.
• significant current may flow in regions substantially below the gate insulator 406.
• the channel region in the semiconductor substrate 415 extends vertically below the source 402 and drain 403 electrodes to a boundary 416 approximately aligned with the bottom edge 420 of the source 402 and bottom edge 421 of the drain 403 electrodes at a depth d* 407.
• Channel dopant is an impurity dopant provided for in the semiconductor substrate 415 in the channel region, usually for the purpose of improving leakage performance from the source 402 and drain 403 electrodes of the MOSFET device.
• Substrate dopant is an impurity dopant provided for in the semiconductor substrate below the bottom 416 of the channel region and below the bottom interface 420,421 of the source 402 and drain 403 electrodes. It is important to understand the difference of a channel dopant and substrate dopant. Referencing FIG. 4, two dopant implants are shown. A first dopant implant is provided for to a depth d 430 in exposed regions of a first masking layer and has laterally uniform and vertically non-uniform concentration profiles.
• a second dopant implant is provided for to a depth d 3 431 in exposed regions of a second masking layer and has laterally uniform and vertically non- uniform concentration profiles.
• the first dopant implant and second dopant implant have different concentrations and vertical non-uniform profiles.
• the resulting MOS device depicted by FIG. 4 has a doping concentration profile in the channel region that is laterally uniform and vertically non-uniform while the substrate doping profile below the channel region has a laterally and vertically non-uniform doping concentration profile.
• An SOI substrate comprises a semiconductor material such as silicon having a thickness of approximately 20 nanometers (nm) to 100 nm, on a buried insulating material such as silicon dioxide (SiO 2 ) having a thickness of approximately 100 nm to 400 nm, which is formed on a semiconductor substrate.
• a semiconductor material such as silicon having a thickness of approximately 20 nanometers (nm) to 100 nm, on a buried insulating material such as silicon dioxide (SiO 2 ) having a thickness of approximately 100 nm to 400 nm, which is formed on a semiconductor substrate.
• CMOS integrated circuits are particularly suitable for use and fabrication of CMOS integrated circuits, but the use of the present teachings is not limited to this particular application.
• Other circuits comprising complimentary or non- complimentary NMOS and or PMOS transistors may be applied to the present invention teachings.
• this specification speaks in terms of 'CMOS' circuits, this term should be interpreted broadly to include any circuit that comprises connected N- and/or P-MOS transistors.
• the present invention is particularly suitable for use in situations where short channel length MOSFETs are to be fabricated, especially in the range of channel lengths ⁇ 100 nm.
• nothing in the teachings of the present invention limits application of the teachings of the present invention to these short channel length devices.
• Advantageous use of the teachings of the present invention may be had with channel lengths of any dimension.
• impurity atoms are selected from the group consisting of Arsenic, Phosphorous, Antimony, Boron, Indium, and/or Gallium as being within the scope of the teachings of the present invention. Circuit Type Not Limitive
• CMOS complementary metal-oxide-semiconductor
• circuit type such as digital logic circuits including inverters, NAND gates, NOR gates, compound gates, multiplexers, and volatile and non-volatile memory.
• present invention is not limited to digital or analog CMOS applications. These and all other circuit types that use combinations of NMOS and/or PMOS transistors are within the scope of the teaching of the present invention.
• the terms 'source' and 'drain' should be interpreted to include the variants 'drain' and 'source' as well as 'source or drain' and 'source and drain'.
• the present invention specifically anticipates the use of source/drain electrodes formed from the group comprising any of Platinum Silicide, Palladium Silicide, Iridium Silicide, and/or the rare-earth silicides as being within the scope of the teachings of the present invention.
• the suicided source/drain can be made of multiple layers of metal silicide, in which case other exemplary silicides, such as titanium silicide or tungsten silicide for example, may be used.
• the present invention specifically anticipates that in some circumstances an interfacial layer may be utilized between the silicon substrate and the actual Schottky barrier metal.
• the present invention specifically anticipates 'Schottky-like' junctions and their equivalents to be useful in implementing the present invention.
• the interfacial layer may comprise materials that have conductive, semi-conductive, and/or insulator-like properties.
• isolation technologies utilized to electrically isolate individual NMOS and PMOS transistors.
• the present invention does not restrict the type of isolation technology used to achieve the results illustrated in the typical process flows. Isolation technologies such as LOCOS, STI and non- recessed oxide windows are well known in the art.
• any well implant described in the discussion will be characterized as either “electrically contacted to an ohmic contact” or “not electrically contacted to an ohmic contact.”
• the phrase "electrically contacted to an ohmic contact” implies ohmic contacting to a power supply such as V dd or ground for example.
• Exclusion Mask Process Not Limitive Throughout the discussion herein, there will be examples provided that make reference to a silicide exclusion mask process for selectively forming silicides in regions of a semiconductor substrate.
• the present invention does not restrict the exclusion mask process from being used for metal-semiconductor compounds other than metal silicides.
• metal-semiconductor compounds forming Schottky or Schottky-like contacts may be used and are within the scope of the teachings of the present invention.
• FIGS. 6-13 One exemplary process for the fabrication of a metal source/drain CMOS device is illustrated in FIGS. 6-13. While this process is exemplary of the broad teachings of the present invention, it will be instructive to one skilled in the art to teach the fundamental concepts of the present invention.
• This exemplary process flow may be described as follows: Referencing FIG. 6, starting with a heavily doped silicon substrate 602 and a lightly doped epitaxial layer 601 that has means for electrically isolating transistors from one another, a thin screen oxide 604 is grown (approximately 200 A) to act as an implant mask. In another embodiment, the silicon substrate 601 is strained.
• a strained silicon substrate 601 in combination with a Schottky barrier MOSFET device results in additional improvements in power and speed performance, as explained in co-pending U.S. patent application number 10/342,590, filed on January 15, 2003.
• the substrate is SOI.
• the dopant Arsenic 607 is ion-implanted through the screen oxide to a predetermined depth dl 608 in the silicon (approximately 1000 A or so).
• the resist pattern layer 605 is stripped, and the wafer is patterned again so that an active region of the N-type device 701 is exposed.
• the dopant Indium 702 for the N-type device active region 701 is ion-implanted through the screen oxide 604 to a pre-determined depth d2 703 in the silicon (e.g. approximately 1000 A).
• P-type and N-type device active regions 606, 701 are isolated by an isolation process, such as local oxidation of silicon (LOCOS).
• LOCOS local oxidation of silicon
• the screen oxide 604 is removed in hydro-fluoric acid, and a thin pad oxide 801 (e.g. approximately 150 A) is grown.
• a layer of Si3N4 802 is then deposited on the wafer (approximately 3000 A). Lithographic techniques define the field oxide regions and the wafer is oxidized.
• the field oxide regions 803 have a thickness of 2500 A and are partially recessed into the epitaxial semiconductor substrate 601.
• the pad oxide 801 and nitride film 802 are then stripped.
• the device active regions 606, 701 are isolated by a simple oxide process, as explained in U.S. provisional patent application number 60/381,162, filed on May 16, 2002.
• the screen oxide 604 is removed in hydrofluoric acid, and then an isolation oxide is grown having a thickness of approximately 100 A.
• the active regions 606, 701 and field oxide regions 803 are then patterned by standard lithographic techniques. It is important to understand that this simple oxide process produces a field oxide 803 that is not recessed into the semiconductor substrate 601 to a depth substantially lower than the source-drain junction 1102, 1103, 1202, 1203 depth.
• a thin gate oxide 901 (e.g. approximately 10-40 A) is grown.
• high K is used as the insulating layer 901.
• high K materials are those materials having dielectric constants greater than that of silicon dioxide, including for example metal oxides such as TiO 2 .
• the use of a high K gate insulating layer in combination with a Schottky barrier device results in additional improvements in drive current, as explained in U.S. Patent Application, Serial
• a polysilicon layer having thickness of approximately 2000 A is deposited.
• the PMOS active regions are masked, and the exposed polysilicon in the NMOS active regions is heavily doped with an N-type dopant, such as phosphorous by ion implantation.
• the NMOS active regions are masked, and the exposed polysilicon in the PMOS active regions is heavily doped with an P-type dopant, such as boron by ion implantation.
• the substrate is annealed so that the implanted dopants in the channel region and gate electrodes are electrically activated and redistributed.
• the N-type 902 and P-type 903 gate electrodes are patterned as shown in the process step 900 illustrated in FIG. 9.
• the gate electrodes are formed using a two mask dual in-situ doped poly process, as explained in U.S. provisional application number 60/381,240, filed May 16, 2002.
• an in- situ doped N-type polysilicon layer having a thickness of approximately 500 A is deposited.
• the NMOS active regions are masked, and the exposed polysilicon in the PMOS active regions is partially etched.
• a second etch, highly selective to the underlying gate oxide 901 is used to remove the remaining N-type doped polysilicon in the PMOS active regions.
• an in-situ doped P-type polysilicon layer having a thickness of approximately 1500 A is deposited.
• the N-type 902 and P- type 903 gate electrodes are patterned as shown in the process step 900 illustrated in FIG. 9.
• the resulting in-situ doped polysilicon gate 902 for the N-type device is thicker than the gate 903 of the P-type device.
• the substrate is optionally annealed to distribute the dopants uniformly throughout the N-type 902 and P- type 903 gate electrodes.
• a thin oxide (approximately 100 A) is then thermally grown on the horizontal surface 1002 and sidewalls 1003 of the silicon gate electrodes.
• An anisotropic etch is then used to remove the oxide layers on the horizontal surfaces 1002 (and thus expose the silicon 1004), while preserving the sidewall oxide 1001 on the vertical surfaces.
• a thin sidewall spacer oxide 1001 is formed, as shown in the process step 1000 illustrated in FIG. 10.
• a thin sidewall spacer insulator 1001 may comprise an oxy-nitride layer or a nitride layer.
• An oxy-nitride layer is a material comprising both oxygen and nitrogen.
• the next step encompasses forming the metal silicide source and drain electrodes.
• the wafer is patterned using an appropriate masking layer 1110 by lithographic techniques such that the P-type active regions of the N-type device 1101 are exposed.
• the masking layer 1110 is a silicide exclusion mask oxide layer.
• a silicide exclusion mask oxide is deposited.
• Photoresist is deposited next, followed by patterning the photoresist, etching the silicide exclusion mask oxide layer 1110 by using for example a buffered oxide etch, and stripping the photoresist so that the N-type active regions are covered by the silicide exclusion mask oxide and thereby are protected from silicide formation.
• the wet etch such as a buffered oxide etch, should preferentially etch deposited oxide with a rate substantially greater than the etch rate for the thermally grown sidewall oxide or other exemplary materials that may be used to provide a gate sidewall insulator spacer.
• the gate sidewall insulator of a conventional device is much thicker than that of a Schottky barrier MOS device. This makes the conventional MOS sidewall less susceptible to damage during wet chemical etches, making integration of silicide exclusion mask steps with a conventional CMOS process more straightforward.
• An appropriate metal for a N-type device silicide for example Erbium
• a N-type device silicide for example Erbium
• the wafer is then annealed for a specified time at a specified temperature (for example, 450 °C for 30 minutes) so that, at all places where the metal is in direct contact with the silicon, a chemical reaction takes place that converts the metal to a metal silicide at a source electrode 1102, a metal silicide at a drain electrode 1103, and a metal silicide at a gate electrode 1104.
• a wet chemical etch e.g. HNO3 or H2SO4 for Erbium
• HNO3 or H2SO4 for Erbium is then used to remove the unreacted metal while leaving the metal-silicide untouched as shown in the process step 1100 as illustrated in FIG. il.
• an appropriate metal for an N-type device silicide for example Erbium
• a second appropriate metal for example Titanium, approximately 50 A
• the wafer is then annealed for a specified time at a specified temperature (for example, 450 °C for 30 minutes) so that, at all places where the metal is in direct contact with the silicon, a chemical reaction takes place that converts both the first and second metal layers to metal silicides at a source electrode 1102, a metal silicides at a drain electrode 1103, and metal silicides at a gate electrode 1104.
• a wet chemical etch (Sulfuric Peroxide) is then used to remove the unreacted metal while leaving the metal-silicides untouched.
• a second metal for example Titanium
• a bottom surface of the Erbium Silicide is in contact with the semiconductor substrate and a top surface of the Erbium Silicide is in contact with the Titanium Silicide.
• the second silicide provides improved manufacturability by providing a more robust etch stop for later metallization processing steps, reduces the net resistivity of the source and drain electrodes and is more stable in room temperature oxidizing ambients, as explained in U.S. provisional application serial number 60/381,238, filed May 16, 2002.
• CMOS complementary metal-oxide-semiconductor
• substrate temperatures for example, less than 700 °C
• impurity doped source/drain fabrication processes that require much higher temperatures (for example, greater than 1000 °C )
• other non-standard materials in silicon-based CMOS such as high K dielectrics, metal gates or strained silicon, can be more easily integrated into the CMOS fabrication process of the present invention, as explained in U.S. provisional application number
• the wafer is patterned again with an appropriate masking layer by lithographic techniques such that the N-type active regions of the P-type device 1201 are exposed.
• the masking layer is a silicide exclusion mask oxide layer.
• a silicide exclusion mask oxide is deposited.
• Photoresist is deposited next, followed by patterning the photoresist, etching the silicide exclusion mask oxide layer by using, for example, a buffered oxide etch, and stripping the photoresist so that the P-type active regions and N- type devices 1101 are covered by the silicide exclusion mask oxide and thereby are protected from silicide formation.
• the wet etch should preferentially etch deposited oxide with a rate substantially greater than the etch rate for the thermally grown sidewall oxide or other exemplary materials that may be used to provide a gate sidewall insulator spacer.
• An appropriate metal for a P-type device silicide for example Platinum
• a metal layer across the wafer approximately 200 A
• the wafer is then annealed for a specified time at a specified temperature (for example, 400 °C for 45 minutes) so that, at all places where the metal is in direct contact with the silicon, a chemical reaction takes place that converts the metal to a metal silicide at a drain electrode 1202, a metal silicide at a source electrode 1203, and a metal silicide at a gate electrode 1204. It is important that the exposed, partially etched, sidewall spacer oxide 1001 provides complete protection of the gate electrode during the silicide-forming anneal.
• a wet chemical etch (aqua regia for Platinum) is then used to remove the unreacted metal while leaving the metal-silicide untouched as shown in the process step 1200 as illustrated in FIG. 12.
• the processes described with reference to process step 1100 (as shown in FIG. 11) and process step 1200 (as shown in FIG. 12) comprise an exemplary embodiment of a dual silicide exclusion mask process for Schottky barrier CMOS.
• the dual silicides could be provided by another exemplary embodiment in which only one silicide exclusion mask is used. For example, An appropriate metal for an N-type device is deposited. Then a silicide exclusion masking layer is provided using lithographic techniques, thereby exposing the N-type active regions of the P-type device.
• a second metal appropriate for P-type device is deposited.
• the wafer is then annealed for a specific time at a specific temperature such that, at all places where the first metal is in direct contact with the silicon, a chemical reaction takes place that converts the metal to a metal silicide at a source electrode 1102, a metal silicide at a drain electrode 1103, and a metal silicide at a gate electrode 1104. Further, during the anneal, the second metal diffuses through the first metal, thereby forming a metal silicide at a source electrode 1202, a metal silicide at a drain electrode 1203, and a metal silicide at a gate electrode 1204.
• CMOS inverter circuit 1300 As shown in FIG. 13, electrical conductor lines are added to connect the gate electrodes 902 and 903 to form an input Vg 1301 for the CMOS circuit 1300 and to connect the drain electrodes 1103 and 1202 to form an output V 0 1302 for the CMOS circuit 1300. Electrical conductor lines are also added to connect the NMOS source electrode 1102 to Vss 1303 and connect the PMOS source electrode 1202 to the supply voltage V dd 1304.
• FIG. 13 shows a cross-sectional view of an exemplary embodiment of the invention, as exemplified by two final complementary MOSFET structures (1300).
• This embodiment comprises an NMOS device 1101 fabricated with Erbium Silicide for the source/drain regions 1102, 1103, and a PMOS device 1201 fabricated with Platinum Silicide for the source/drain regions 1202, 1203.
• the Schottky (or Schottky-like) barriers (1312, 1313, 1322, 1323) that exist along the interface of the corresponding metal source/drain 1102,1103,1202,1203 and the silicon substrate 601 act as an inherent pocket or halo implant and does so without added parasitic capacitance.
• Metal silicide source/drain extensions may be used for the NMOS and PMOS source and drain regions (1102, 1103, 1202, 1203) to further enhance the performance of the Schottky barrier CMOS device, as explained in U.S. provisional patent application number 60/381,321, filed May 16, 2002.
• the metal source/drain (which replaces the conventional impurity doped source/drain) has a natural, very consistent and atomically abrupt Scotty barrier (1312, 1313, 1322, 1323) with the silicon substrate 601 whose position and magnitude are independent of channel length, and because this barrier essentially plays the role of the halo/pocket implant (making these implants unnecessary), statistical variations due to random placement of atoms during the source/drain and halo/pocket implants are essentially eliminated. This fact remains true and even becomes more true as the channel length is reduced.
• the parasitic bipolar gain is a direct result of using opposite doping types for the source/drain and substrate regions, and can result in latch-up and other deleterious effects.
• the source/drain electrodes are constructed of metal, thereby providing Schottky barrier contacts with the semiconductor substrate, this parasitic gain is eliminated.
• having no parasitic bipolar gain eliminates the need for well implants electrically contacted via ohmic contacts to V d and ground power supplies for PMOS and NMOS devices, respectively, resulting in reduced processing steps, lower costs and improved yields. Because Schottky barrier CMOS is not susceptible to parasitic bipolar action, it could also find application in the field of Power MOSFET devices, as previously disclosed in U.S. provisional application number 60/381,237, filed May 16, 2002.
• Indium 702 and Arsenic 607 layers are used as the channel and substrate dopants for the NMOS and PMOS devices, respectively. These dopant atoms are used due to their relatively low rates of diffusion through the silicon lattice (compared to Phosphorous and Boron, the other two possible candidates for channel and substrate dopants). This allows for greater thermal budget during fabrication of the device, and therefore less statistical variation in the characteristics of the finished product. It is important to understand that the regions having channel and substrate dopants 607, 702 are not electrically connected to ohmic contacts.
• the gate electrodes 902, 903 are fabricated from Boron and Phosphorous doped polysilicon films for the P-type and N-type devices, respectively. In this instance, Boron and Phosphorous are used due to their large solid-solubilities (compared to Arsenic and Indium).
• the gate electrodes may be less than 100 nm in width (corresponding to the channel length L), as it is in this regime that the advantages of the Schottky barrier architecture over the conventional architecture become apparent. These include simplified processing due to the absence of need for pocket implants, and the resulting reduction in yield loss, capacitance and statistical variations in finished products.
• Devices are separated from each other by an insulating layer, such as a thermally grown oxide (called a Field Oxide) 803 that works in conjunction with channel and substrate dopants to electrically isolate the devices from each other.
• a thermally grown oxide called a Field Oxide 803 that works in conjunction with channel and substrate dopants to electrically isolate the devices from each other.
• This field oxide 803 may be provided for by a conventional process, such as LOCOS, producing a partially recessed field oxide 803, or a simpler device isolation process, such as a simple thin, non-recessed or shallow oxide.
• the shallow field oxide sometimes referred to as an oxide window, does not extend into the substrate to a depth substantially lower than the source-drain junction depth. Use of a shallow field oxide window results in additional reduced processing steps, lower costs and improved yields.
• the field oxide 1403 is a simple thin oxide that is not substantially recessed into the epitaxial semiconductor substrate 601.
• optional well implants 1405, 1406 not electrically contacted to ohmic contacts may be used to isolate the PMOS and NMOS devices, respectively. It is significant to note that well implants electrically connected to ohmic contacts are not required for the PMOS or NMOS devices in the inverter circuit. If optional well implants are used, an additional Arsenic implant step would be provided for during process step 600 illustrated in FIG. 6 resulting in an Arsenic well 1405, and an additional Indium implant step would be provided for during process step 700 illustrated in FIG. 7 resulting in an Indium well 1406. The well implants 1405, 1406 are not required to be electrically contacted to ohmic contacts.
• FIG. 15 shows a top view of a preferred exemplary embodiment of the invention, as exemplified by a Schottky barrier CMOS inverting circuit and its typical operating and biasing conditions.
• the PMOS device 1502 and NMOS device 1505 have optional well implants 1520, 1521 when using the simple thin oxide for device isolation.
• the well implants 1520, 1521 are not electrically connected to ohmic contacts.
• N-type device 1505 is "on” and the P-type device 1502 is "off. That is, a channel region of the N-type device 1505 conducts while a channel region of the P-type device 1502 does not conduct. The result being that the output voltage V 0 1512 changes to the low value V ss 1506. The opposite occurs when V g 1509 is low (usually V ss 1506).
• the N-type device 1505 is now “off and the P-type device 1502 "on”, and the output voltage V 0 1512 changes to that of the P-type source, or V dd 1503, effectively providing an inverting function.
• the Schottky barrier CMOS circuit may be operated at reduced temperature to further enhance the power and speed performance, as explained in U.S. provisional application number 60/388,659, filed May 16, 2002.
• CMOS inverter circuit is merely one exemplary way of using complimentary Schottky barrier PMOS and NMOS transistors, and that many variations exist for combining PMOS and/or NMOS transistors in an integrated circuit, without departing from the spirit and scope of the present invention.
• the present invention is intended to cover a CMOS device including any of the various permutations of features disclosed herein or disclosed in the materials that have been incorporated by reference, and a CMOS fabrication process including any permutation of the fabrication techniques disclosed herein or disclosed in the materials that have been incorporated by reference.

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