EP1552394A1 - Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs - Google Patents

Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs

Info

Publication number
EP1552394A1
EP1552394A1 EP03807784A EP03807784A EP1552394A1 EP 1552394 A1 EP1552394 A1 EP 1552394A1 EP 03807784 A EP03807784 A EP 03807784A EP 03807784 A EP03807784 A EP 03807784A EP 1552394 A1 EP1552394 A1 EP 1552394A1
Authority
EP
European Patent Office
Prior art keywords
cpu
operating mode
instructions
module
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03807784A
Other languages
German (de)
English (en)
Inventor
Anton Weber
Dirk Schnabel
Pavel Peleska
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP02020602A external-priority patent/EP1398699A1/fr
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to EP03807784A priority Critical patent/EP1552394A1/fr
Publication of EP1552394A1 publication Critical patent/EP1552394A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1691—Temporal synchronisation or re-synchronisation of redundant processing components using a quantum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level

Definitions

  • Event synchronization method especially for processors of fault-tolerant systems
  • processor boards In many cases, up to a few hundred so-called processor boards are used in telecommunications systems, data centers and other high-availability systems to provide the necessary computing power.
  • a processor board typically consists of a processor or CPU (Central Processing Unit), a chip set, main memory and peripheral components.
  • CPU Central Processing Unit
  • the probability of a hardware defect of a typical processor board occurring per year is in the single-digit percentage range. Due to the large number of processor boards combined into a system, there is a very high probability of a failure of any hardware component in relation to the year, whereby such an individual failure, if suitable precautions are not taken, can cause the failure of the entire system.
  • Known solutions to comply with such high system availability requirements provide redundant system components. The known methods can be divided into two main groups: software-based methods and hardware-based methods.
  • the basic principle of hardware-based methods is based on encapsulating the redundancy at the hardware level so that this is transparent to the software.
  • the main advantage of a redundancy managed by the hardware itself is that the application software is not affected by the redundancy principle and therefore any software can be used in most cases. .
  • Lockstep means that identical hardware, e.g. two boards, operated in isochronous mode.
  • Hardware mechanisms ensure that the redundant hardware experiences identical input stimuli at a given point in time and must therefore come to identical results.
  • the results of the redundant components are compared; in the event of a deviation, an error is identified and suitable measures are initiated (alarm operator, partial or complete safety shutdown, system restart).
  • Cyclically deterministic behavior means that these components have identical results at identical clocks if there is no error - Deliver times when the components receive identical stimuli at identical clock times. Intermittent deterministic behavior also requires the use of isochronous interfaces. In many cases, asynchronous interfaces cause a certain degree of unsharpness in the system, as a result of which the clock-synchronous overall behavior of the system cannot be maintained.
  • asynchronous interfaces offer technological advantages in increasing performance, which makes clock-synchronous operation according to the lockstep process impossible.
  • modern CPUs increasingly use mechanisms that make clock-synchronous operation impossible.
  • These are, for example, internal corrective measures that are not visible to the outside, e.g. Correction of an internal, correctable error in accessing the cache memory, which can lead to a slight delay in command processing, or the speculative execution of commands.
  • Another example is the future increasing implementation of CPU-internal clock-free execution units, which allow considerable advantages in terms of speed and power dissipation, but prevent a clock-synchronous or deterministic work of the CPU.
  • European patent application 02020602 discloses a method for the synchronization of external events which are supplied to and influence a CPU, accordingly the external NEN events are temporarily stored, the stored external events being called up in a separate operating mode of the CPU for processing by an execution unit and the CPU entering this operating mode in response to the fulfillment of a condition that can be predetermined or specified by commands. This process is also called "emulated lockstep operation".
  • EP 02020602 advantageously provides that the switch to the separate operating mode is carried out if a comparator element of the CPU determines the correspondence of a counter with a maximum instruction register (MIR), the content of the MIR being specifiable by commands and the counter contains the number of instructions executed by the execution unit since the last change to the separate operating mode.
  • MIR maximum instruction register
  • This object is achieved by a method for synchronizing external events according to the features of patent claim 1, by a processor according to the features of patent claim 6 and by a system according to the features of patent claim 7.
  • Advantageous further developments are specified in the dependent claims.
  • a method for the synchronization of external events which are supplied to and influence a module CPU, the module CPU being provided for the parallel processing of a first number of instructions, accordingly the external events are temporarily stored, the external events stored in a separate operating mode of the module can be called up for processing by at least one execution unit EU of the module and - the module enters this operating mode after a predeterminable second number MIC of instructions has been processed by a counter (IC) executing the number of executions by the execution unit Instructions are determined since the last time the separate operating mode was exited, the module is placed in a single instruction execution mode if the counter IC is greater than or equal to the difference between the second number of instructions and a third number MD of instructions, which is determined from the first number of instructions, the module remains in the single instruction execution mode until the counter IC reaches the second number MIC of instructions, whereupon the module switches to the separate operating mode and the counter when the separate operating mode is exited IC is reinitialized.
  • the third number of instructions mentioned is based on the maximum number of instructions executed in parallel and serves to compensate for the blurring explained when stopping CPUs with the ability to process instructions in parallel.
  • the third number is preferably chosen to be equal to or greater than the first number of instructions executed in parallel.
  • the method according to the invention can be implemented by software, by microcode or by specialized hardware.
  • the counter IC is monitored by a monitoring software module, the number of instructions executed by the monitoring software module is recorded separately and subtracted from the counter IC.
  • the invention further provides a processor module CPU which has at least the following: at least one execution unit EU, - at least one counter element IC for counting the instructions executed by the execution unit since the last change to a separate operating mode, - at least one register element MIR, the content of which MIC is predefined by commands or is predetermined, - at least one comparator element K and at least one
  • Control element S for switching the execution unit EU into a single instruction execution mode in response to the counting element IC reaching a predeterminable value, which is smaller than the value of the register element MIR, and for switching the execution unit into the separate operating mode in response to the correspondence of the counting element IC with the register element MIR, whereby external events, which are temporarily stored in the separate operating mode and are to be supplied to the processor module CPU and influence the processor module CPU, are called up by the processor module CPU.
  • processors can advantageously be combined to form a system, the system additionally having a connection L0, Ll between at least two of the processor modules CPU which execute an identical instruction sequence, the connection being provided for transmitting synchronization information of the separate operating modes ,
  • Invention takes into account the fact that modern CPUs with the ability to process instructions in parallel cannot always be stopped after an exact number of instructions.
  • the CPUs can be operated with different clock frequencies.
  • the CPUs can behave differently with regard to the speculative execution of instructions, since only the completed instructions are evaluated. - Different CPU-internal execution times of identical CPUs, for example due to corrections after data corruption of alpha particles, only lead to the synchronization mode being reached at slightly different times.
  • FIG. 1 shows a flow diagram of the method according to the invention.
  • FIG. 2 schematically shows a processor module according to the invention.
  • FIG. 3 shows schematically an inventive system consisting of two processor modules according to FIG. 2.
  • FIG. 1 the inventive method is shown graphically as a flow chart. The following values must be defined or initialized before the process begins: - A counter IC (instruction counter), which contains the number of instructions or machine commands processed by the CPU.
  • IC instruction counter
  • a number of MICs (Maximum Instruction Counter) according to which the CPU is to switch to the special operating mode for processing external events.
  • MD Maximum Deviation
  • the process begins by comparing the current value of the command counter IC with the difference between the values MIC and MD (block 11). If the value of the command counter is less than this difference, command processing continues in the normal operating mode; parallel execution of instructions is possible. If the value of the command counter reaches or exceeds the difference between MIC and MD, a register d is loaded with the difference between MIC and MD (block 12), and the process enters a loop, at the beginning of which there is a query as to whether the register d has reached the value MIC (block 13). In this loop, the command is processed in single step mode.
  • the process enters the separate operating mode.
  • the separate operating mode first checks whether an interrupt request has been received during the processing of the MIC commands and has been buffered by all redundant CPUs for processing at the same time (blocks 16/17). If interrupt requests have been received, these are processed (block 18), this processing being carried out by all redundant CPUs at an identical point in the program processing and all registers, memory contents, .. being identical. This step is skipped if there are no interrupt requests.
  • the separate operating mode is ended, and the normal operating mode with parallel processing of instructions is resumed after the reset of the command counter IC (block 19).
  • An interrupt request can then be processed.
  • the interrupt routine is not processed in a separate operating mode, but in normal mode. Only the interrupt vector is read in special operating mode, then the special mode is exited again. Whether the interrupt is then processed depends, for example, on whether interrupts are currently permitted. Interrupts are not permitted if an interrupt is being processed and / or an "interrupt flag" has been cleared.
  • the method according to the invention can be used directly as a sequence of instructions, i.e. as software.
  • the software ensures that an interrupt is presented at identical points in the instruction execution of several processors by programming an instruction counter in the CPU so that it receives an exception, e.g. Debug exception, or a high-priority, non-lockable interrupt, e.g. the unmaskable interrupt NMI, caused by the desired number MIC of instructions to be processed minus the "stop blur" MD.
  • the software then run reads the instruction counter to determine where the processor has actually stopped. This software is designed so that the execution of your own instructions is corrected accordingly. If the software determines that the CPU has stopped after, for example, 999 instructions, the desired 100th instruction is executed subsequently by single-step operation, controlled by the exception software. This happens with all redundant CPUs, so that all CPUs were subsequently stopped at the identical position in the code.
  • the CPU / CPUs must be presented with any interrupt request.
  • the CPU can read a register of the interrupt controller, whereupon this releases a masked interrupt signal.
  • the CPU recognizes an interrupt request based on this interrupt signal and sends an interrupt acknowledge cycle to the interrupt controller.
  • the interrupt controller then supplies the interrupt vector and again masks the interrupt signal.
  • the software can read a register whose
  • the process can also be implemented in the form of microcode instructions.
  • modern CPUs have extensive options for controlling the execution of commands using microcode. These options are often used, for example, to correct or bypass design errors.
  • the microcode is changed in such a way that the CPU interrupts normal command execution after the desired number of instructions MIC to be processed minus the “stopping blur” MD and branches into the microcode.
  • the microcode reads out the number of executed instructions IC and controls the execution via single step in such a way that the command execution is stopped at the desired location MIC.
  • An interrupt signal masked by microcode is released by microcode, and if an interrupt is pending, the CPU is switched to the corresponding interrupt routine. branch. The interrupt is then masked again using microcode. - Alternatively, the CPU can be prompted to generate an interrupt acknowledge cycle and to read an interrupt vector. This is then presented to the CPU by microcode so that it branches into the corresponding interrupt routine after leaving the separate mode.
  • code translation software could take place.
  • Some CPUs have a simple, but very fast, mostly superscalar RISC or VLIW processor core.
  • the actual command set, e.g. IA-32 is transformed into simple code by code translation software and executed by the RISC / VLIW processor.
  • the code translation software carries out the task of the method, analogously to the implementation in microcode.
  • the interrupt requests are presented in the same way as for the microcode implementation.
  • the most efficient implementation of the method according to the invention is a hardware implementation, shown in FIG. 2.
  • a processor-internal hardware unit S stops parallel execution of the command at the desired location minus the unsharpness, the instruction counter status IC is determined, and the execution unit EU is determined by the processor-internal hardware unit S. brought to the desired position in the code by means of single step or single step ES.
  • the main advantage of this procedure is the significantly reduced negative impact on performance.
  • FIG. 2 shows a processor block CPU according to the invention in a schematic representation. Only the components relevant to this invention are shown.
  • the CPU comprises one or more execution units EU, at least one comparator K, at least one counter IC for counting the instructions executed by the execution unit EU, a controller S and at least one register element MIR, Its content can be specified by commands or can be predefined. Connections from / to an interrupt register (FIG. 3) are also shown schematically.
  • the external events influencing the program flow are not fed directly to the CPU, but are initially buffered by suitably designed hardware.
  • the method can be implemented in the CPU shown in FIG. 2 by loading the register MIR with the difference between the value MIC and the value MD.
  • the comparator K compares the number of operations carried out with this register value and signals the result of this comparison to the control unit S.
  • the comparator can also transmit to the control only an event that is generated when the value of the IC reaches the value of the MIR Has. If this event has occurred or if the two registers have been signaled to be identical, the controller S queries the command counter again in order to read the number of instructions actually executed.
  • the control can initiate the execution of instructions individually by the control, signaled via the line ES to the execution unit, until the value of the command counter reaches the predetermined value MIC reached .
  • the controller S has the option of incrementing the command counter IC if the command counter does not automatically count the instructions executed in the single step.
  • the controller S of each redundant CPU generates an interrupt enable signal IF which is fed to an interrupt module. Thereupon, if necessary, a buffered interrupt request is reported to all redundant CPUs via the interrupt line INT.
  • the controller S generates an interrupt for its own CPU, whereupon the execution units send an interrupt acknowledge cycle to the interrupt module. if interrupts are allowed in command processing at this time.
  • control S generates an interrupt enable signal IF which is logically ANDed with the interrupt signal INT, i.e. the circuit logic must be selected accordingly if there are inverted signals or if the interrupt signal is presented on several lines.
  • the interrupt enable signal can also be sent outside the CPU e.g. are transmitted to the interrupt register. Any interrupts present on the interrupt line INT are thus released, and the usual interrupt handling can take place, e.g. Read the interrupt vector, execute the .interrupt routine, etc.
  • the cancellation of the single-step mode and the separate operating mode and the continuation of the command processing in the normal mode are signaled to the execution unit, and the command counter is reset via a signal CL.
  • the control can be implemented directly as hardware or in the form of microcode.
  • FIG. 3 shows an interconnection of two CPUs as described above in connection with FIG. 2.
  • the first processor CPU0 and the second processor CPU1 are shown without the details from FIG. 2.
  • the processors each exchange addresses and data via a bus A / D with assigned interrupt blocks, which among other things Include interrupt registers IR0, IR1.
  • the interrupt blocks receive interrupts INTl .. INTn, for example from input / output blocks I / O, store the corresponding characteristic data and forward the interrupts INT to the processors.
  • the interrupts are only accepted by the processors at certain points in the execution of the command. This is described in detail in connection with FIG. 2.
  • the interrupt enable signal explained in this context can also be used to signal to the interrupt module assigned to each processor that the interrupt handling can be started.
  • the interrupt modules which are connected via connections L0, L1, can exchange this information and can only release the interrupt handling, for example, by transmitting the interrupt vector to the processors when all processors generate an interrupt enable signal.
  • CPUs that have SMT (Simultaneous Multi Threading) capabilities must have a separate controller for each virtual CPU or thread.
  • the CPU has the comparator or comparator K, which compares the number of commands executed, that is to say the counter IC, with the register MIR and, in the case of equality, for example generates an interrupt request which specifies the command execution based on the number of commands carried out by the register MIR - given instructions interrupts and the CPU switches to another operating mode.
  • suitable microcode is executed, for example, or an interrupt service routine is branched out, or hardware signals indicate that this synchronization point has been reached.
  • the external events are then presented to the redundant CPUs in such a way that after leaving this operating mode, all CPUs can evaluate these events in the same way and thus subsequently execute the same commands.
  • the CPU branches into an interrupt service routine in which the status of interrupt signals kept away from the CPU by the hardware described is queried in such a way that a redundant CPU, which may query this at a slightly later point in time that receives identical information.
  • the counter IC When leaving the separate operating mode, the counter IC is reset. Then the program jumps back to the point at which the interruption occurred due to the reaching of the counter value IC specified by the register MIR. The CPU will then again execute the number of machine instructions specified by the register MIR and, when the register value MIR has been reached, change the mode by means of the counter IC and thereby enable the acceptance of external events.
  • the CPU registers MIR are advantageously designed in such a way that they can be written to by software or microcode, in order to ensure that interrupt handling takes place at appropriate intervals for different areas of application by correspondingly specifying the number of instructions to be executed between the time windows for the interrupt handling becomes.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

Selon l'invention, des systèmes redondants sont pourvus de cartes électroniques de traitement, souvent agencées de manière identique et qui fonctionnent en mode synchrone. La condition de base pour la mise en oeuvre d'un système en mode bloqué est le comportement déterministe de tous les composants contenus dans une carte, tels que l'unité centrale, la série de puces, la mémoire centrale etc. Selon l'invention, le comportement déterministe est caractérisé en ce que les composants livrent des résultats identiques à des moments identiques sans défauts, lorsque les composants contiennent des stimuli identiques à des moments identiques. Un comportement déterministe suppose également l'utilisation d'interfaces synchrones. Les interfaces asynchrones provoquent dans le système, dans de nombreux cas, une certaine incertitude temporelle, le comportement général synchrone du système ne pouvant, de ce fait, pas être maintenu. L'objectif de l'invention est de mettre en oeuvre un fonctionnement en mode synchrone. A cet effet, l'invention concerne un procédé de synchronisation d'événements extérieurs, qui sont transmis à un processeur (unité centrale) et qui influencent ce dernier. Par conséquent, les événements externes sont mis en mémoire tampon et les processeurs sont présentés à une place identique dans l'exécution d'instructions. Les problèmes inhérents à la capacité des processeurs modernes, notamment la prise en charge parallèle des instructions, sont évités, du fait que l'exécution parallèle des processeurs est empêchée, avant que la place souhaitée soit atteinte dans la prise en charge des instructions, puis cette place est atteinte exactement dans un mode pas à pas.
EP03807784A 2002-09-12 2003-08-07 Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs Withdrawn EP1552394A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP03807784A EP1552394A1 (fr) 2002-09-12 2003-08-07 Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
EP02020602A EP1398699A1 (fr) 2002-09-12 2002-09-12 Méthode pour synchroniser des évènements, en particulier pour des systèmes à tolérance de fautes
EP02020602 2002-09-12
EP02027848 2002-12-12
EP02027848A EP1398701A1 (fr) 2002-09-12 2002-12-12 Méthode pour synchronizer des évèments, en particulier pour des systèmes à tolerance de fautes
PCT/EP2003/008794 WO2004034261A1 (fr) 2002-09-12 2003-08-07 Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs
EP03807784A EP1552394A1 (fr) 2002-09-12 2003-08-07 Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs

Publications (1)

Publication Number Publication Date
EP1552394A1 true EP1552394A1 (fr) 2005-07-13

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Application Number Title Priority Date Filing Date
EP02027848A Withdrawn EP1398701A1 (fr) 2002-09-12 2002-12-12 Méthode pour synchronizer des évèments, en particulier pour des systèmes à tolerance de fautes
EP03807784A Withdrawn EP1552394A1 (fr) 2002-09-12 2003-08-07 Procede de synchronisation d'evenements, en particulier pour des systemes tolerant aux erreurs de processeurs

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP02027848A Withdrawn EP1398701A1 (fr) 2002-09-12 2002-12-12 Méthode pour synchronizer des évèments, en particulier pour des systèmes à tolerance de fautes

Country Status (6)

Country Link
US (1) US20050229035A1 (fr)
EP (2) EP1398701A1 (fr)
CN (1) CN1639691A (fr)
AU (1) AU2003251697A1 (fr)
CA (1) CA2498596A1 (fr)
WO (1) WO2004034261A1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231554B2 (en) * 2002-03-25 2007-06-12 Availigent, Inc. Transparent consistent active replication of multithreaded application programs
US7305582B1 (en) * 2002-08-30 2007-12-04 Availigent, Inc. Consistent asynchronous checkpointing of multithreaded application programs based on active replication
US7206964B2 (en) * 2002-08-30 2007-04-17 Availigent, Inc. Consistent asynchronous checkpointing of multithreaded application programs based on semi-active or passive replication
EP1398700A1 (fr) * 2002-09-12 2004-03-17 Siemens Aktiengesellschaft Méthode et circuit intégré pour la synchronisation d'unités redondantes de traitement des informations
DE102004038590A1 (de) * 2004-08-06 2006-03-16 Robert Bosch Gmbh Verfahren zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Zweirechnersystems sowie entsprechende Verzögerungseinheit
JP4289293B2 (ja) * 2004-12-20 2009-07-01 日本電気株式会社 起動制御方法、二重化プラットフォームシステム及び情報処理装置
JP2006178636A (ja) * 2004-12-21 2006-07-06 Nec Corp フォールトトレラントコンピュータ、およびその制御方法
US20060271812A1 (en) * 2005-05-26 2006-11-30 David Horton Systems and methods for providing redundant application servers
GB0602641D0 (en) * 2006-02-09 2006-03-22 Eads Defence And Security Syst High speed data processing system
FR2912526B1 (fr) * 2007-02-13 2009-04-17 Thales Sa Procede de maintien du synchronisme d'execution entre plusieurs processeurs asynchrones fonctionnant en parallele de maniere redondante.
US9086977B2 (en) 2011-04-19 2015-07-21 Freescale Semiconductor, Inc. Cache memory with dynamic lockstep support
US9208036B2 (en) 2011-04-19 2015-12-08 Freescale Semiconductor, Inc. Dynamic lockstep cache memory replacement logic
US9176828B2 (en) * 2012-09-04 2015-11-03 Opshub, Inc. System and method for merging results from multiple runs based on run inputs
US9176830B2 (en) * 2013-05-24 2015-11-03 Hyundai Motor Company Method for determining software error in virtualization based integrated control system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3235762A1 (de) * 1982-09-28 1984-03-29 Fried. Krupp Gmbh, 4300 Essen Verfahren und vorrichtung zur synchronisation von datenverarbeitungsanlagen
CA2003338A1 (fr) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronisation d'un ordinateur insensible aux defaillances a processeurs multiples
US5226152A (en) * 1990-12-07 1993-07-06 Motorola, Inc. Functional lockstep arrangement for redundant processors
DE19625195A1 (de) * 1996-06-24 1998-01-02 Siemens Ag Synchronisationsverfahren
JP2001523855A (ja) * 1997-11-14 2001-11-27 マラソン テクノロジーズ コーポレイション 故障回復／耐故障計算機
DE19943790C2 (de) * 1999-09-13 2001-11-15 Ericsson Telefon Ab L M Verfahren und Vorrichtung zur Bestimmung eines Synchronisationsfehlers in einem Netzwerkknoten
US6802024B2 (en) * 2001-12-13 2004-10-05 Intel Corporation Deterministic preemption points in operating system execution

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004034261A1 *

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Publication number Publication date
US20050229035A1 (en) 2005-10-13
WO2004034261A1 (fr) 2004-04-22
AU2003251697A1 (en) 2004-05-04
EP1398701A1 (fr) 2004-03-17
CA2498596A1 (fr) 2004-04-22
CN1639691A (zh) 2005-07-13

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