EP1556899A1 - Composant electronique a composant electronique passif integre et procede de fabrication dudit composant - Google Patents

Composant electronique a composant electronique passif integre et procede de fabrication dudit composant

Info

Publication number
EP1556899A1
EP1556899A1 EP03753282A EP03753282A EP1556899A1 EP 1556899 A1 EP1556899 A1 EP 1556899A1 EP 03753282 A EP03753282 A EP 03753282A EP 03753282 A EP03753282 A EP 03753282A EP 1556899 A1 EP1556899 A1 EP 1556899A1
Authority
EP
European Patent Office
Prior art keywords
electrically conductive
electronic component
conductive structure
insulation layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03753282A
Other languages
German (de)
English (en)
Other versions
EP1556899B1 (fr
Inventor
Hans-Joachim Barth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1556899A1 publication Critical patent/EP1556899A1/fr
Application granted granted Critical
Publication of EP1556899B1 publication Critical patent/EP1556899B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Definitions

  • the invention relates to an electronic component with an integrated electronic component and a method for producing this electronic component.
  • a capacitance structure for an integrated circuit is known from US Pat. No. 5,583,359. There is a plurality of metal plates which form the electrodes of one
  • Form stack capacitor separated by dielectric layers, arranged one above the other.
  • a metal line insulated from the respective plate is arranged in each level of a metal plate.
  • the metal lines are contacted from both sides with via connections, whereby on the one hand all the odd-numbered plates and on the other hand all even-numbered plates positioned in the stack are electrically connected to one another.
  • the capacitance surface is thus formed by the plate surfaces.
  • An alternative embodiment of the electrodes is given in that the plates are designed as strip-shaped lines which are arranged parallel to one another.
  • dielectric regions are formed whose materials have low dielectric constants (e.g. SiLK (organic material with a dielectric constant of 2.65), Black Diamond, Coral (both carbon-doped oxides with a dielectric constant less than 3) or porous formations of these dielectrics) it is necessary to form mechanical reinforcements in order to avoid damage due to the low hardness of these dielectric materials when the component is subjected to mechanical force.
  • SiLK organic material with a dielectric constant of 2.65
  • Black Diamond both carbon-doped oxides with a dielectric constant less than 3
  • porous formations of these dielectrics it is necessary to form mechanical reinforcements in order to avoid damage due to the low hardness of these dielectric materials when the component is subjected to mechanical force.
  • the object of the invention is therefore to provide an electronic component with an integrated passive electronic component and a method for its production, which can be produced relatively inexpensively and in a space-saving manner and is robust against the action of mechanical force.
  • This object is achieved by an electronic component with the features of patent claim 1 and by a method which has the steps according to patent claim 18.
  • An electronic component according to the invention has a first insulation layer on which an upper metal layer is formed.
  • the upper metal layer is designed in particular as an electrically conductive bond ad layer, to which, for example, aluminum or gold wires for electrically connecting the contact areas of the electronic component or the chip to the contact tracks of a housing in which the electronic component is mounted, be bonded.
  • An electrically conductive structure is integrated in the first insulation layer, which mechanically stabilizes the first insulation layer when subjected to mechanical force, in particular when bonding the upper metal layer and / or assembling the electronic component.
  • the electrically conductive structure is additionally designed as a passive electronic component.
  • the electrically conductive structure in the electronic component serves on the one hand as a mechanical support structure when the component is subjected to mechanical force, in particular as a mechanical support structure for the first insulation layer, and on the other hand as a passive component of the electronic component.
  • This single structure with a double function reduces the process steps during manufacture and thus the manufacturing costs, since no separate manufacture of mechanical support or stability structure and passive component structures is required.
  • the first insulation layer is a dielectric layer made of a material.
  • ren dielectric constant has a value less than 4, formed.
  • the dielectric constant of SiLK, an organic material is 2.65.
  • Other materials can be, for example, coral or black diamonds, which are carbon-doped oxides and have a dielectric value of less than 3. Due to the small modulus and the low hardness of these materials, even relatively low mechanical forces can lead to damage, so that in this case the integrated electrically conductive structure proves to be particularly advantageous as mechanical stabilization.
  • the first insulation layer can also be formed as a multilayer system, in which the individual layers also have higher dielectric constants than 4 in some cases. In this case it is essential that the multilayer system has an average dielectric constant, the value of which is less than 4, in particular less than 3.
  • the electrically conductive structure is arranged essentially vertically below a bonding area of the upper metal layer.
  • the bonding area which essentially designates that area of the upper metal layer in which the electrical connections, in particular the contact wires, for making the electrical contact with the contact tracks of the housing are arranged, can be implemented in a variety of ways. Optimized mechanical stability can be made possible by the direct arrangement of the electrically conductive structure below this bonding area. It is particularly preferred if the dimensions of the electrically conductive structure in a plane parallel to the upper metal layer have at least the dimensions of the bonding area. Regardless of where a bonding or mechanical force acts on the bonding area, the first insulation layer or the entire electronic component can therefore be protected against mechanical damage or destruction.
  • the electrically conductive structure is arranged in the first insulation layer such that the electrically conductive structure is essentially flush with the horizontal planes of the first insulation layer.
  • the electrically conductive structure is thus formed in the first insulation layer in such a way that partial regions of the horizontal surfaces of the first insulation layer are formed by surface regions of the electrically conductive structure.
  • the electrically conductive structure is formed in the vertical direction with maximum expansion in the first insulation layer (first insulation layer and electrically conductive structure have essentially identical dimensions in the vertical direction). This can further improve the mechanical stability, since there is no mechanically less stable or "soft" area of the first insulation layer below the bonding area, which is not supported by the electrically conductive structure.
  • a further advantageous embodiment is characterized in that the electrically conductive structure has a supply voltage potential by means of via connections via a metal strip formed in a further metallization level, in particular contact metal strips, and by means of via connections via a further metal strip formed in a metallization level Ground potential are connected.
  • both contact strips are formed in a second insulation layer, which is made of a material with a high mechanical stability compared to the mechanical stability of the material of the first insulation layer.
  • the elastic modulus of the material of the second insulation layer preferably has a value greater than 15 gigapascals, in particular a value greater than 20 gigapascals, or a hardness greater than 4.
  • the electronic component is additionally stabilized when subjected to mechanical force, in particular on the bonding -Area of the upper metal layer.
  • An oxide layer or a layer made of FSG (fluorosilicate glass) dielectric can be formed as the second insulation layer.
  • an electrically conductive shielding layer is formed between the upper metal layer and the electrically conductive structure.
  • the electrically conductive shielding layer is insulated both from the upper metal layer and from the electrically conductive structure.
  • the shielding layer can advantageously be formed as a metal layer, which is preferably connected to ground potential. It can thereby be achieved that the signals applied to the upper metal layer cannot couple into the underlying electrically conductive structure and the signals applied to the electrically conductive structure or to the passive component cannot couple into the upper metal layer.
  • the shielding layer in a third insulation layer, the third insulation layer being arranged between the upper metal layer and the first insulation layer. Since the third insulation layer is preferably designed as an oxide layer, a further mechanical reinforcement of the first insulation layer can be achieved.
  • the shielding layer can be designed as a coherent plate or as a lattice structure.
  • a particularly effective electrical shielding can be achieved if the shielding layer is more advantageous Is designed in such a way that the surface of the shielding layer facing the electrically conductive structure is at least as large as the surface of the electrically conductive structure facing the shielding layer.
  • the shielding layer is preferably formed on the electrically conductive structure such that when the shielding layer is viewed from above, the outline of the surface of the shielding layer covers the outline of the surface of the electrically conductive structure.
  • the electrically conductive structure is designed as a capacitance structure and / or as an inductance structure. It can be provided that the electrically conductive structure is produced entirely as a capacitance or completely as an inductor. However, the electrically conductive structure can also consist of several sub-structures, one sub-structure being arranged as a capacitance and another sub-structure as an inductor in the first insulation layer.
  • a preferred exemplary embodiment of the electrically conductive structure is characterized in that at least one partial structure is designed as a capacitance structure, which extends over at least two metallization levels and metal strips arranged parallel to one another and electrically insulated from one another are formed in each metallization level.
  • the metal strips of the first metallization level are arranged substantially congruently to the metal strips of the second metallization level and are electrically connected to one another in the vertical direction by means of via connections.
  • a further advantageous exemplary embodiment is given in that at least one partial structure of the electrically conductive structure is designed as an inductance structure and has at least one metallization level in which a spiral-shaped metal track is formed.
  • the upper metal layer can be contacted via a contact hole in the second insulation layer with an electrically conductive region formed below it, in particular in the third insulation layer.
  • the contact hole is preferably arranged in the area outside the bonding area of the upper metal layer and, like the electrically conductive area, can be arranged horizontally offset from the electrically conductive structure.
  • the electronic component according to the invention is arranged on a substrate in an integrated circuit.
  • an electrically conductive structure is formed in a first insulation layer as at least one passive electronic component and as a mechanical stabilization structure for supporting the first insulation layer when subjected to mechanical forces.
  • An upper metal layer which is formed in particular as an electrically conductive bond ad layer, is produced on the first insulation layer, and mechanical forces are exerted on it, in particular when bonding or when mounting the electronic component.
  • the first insulation layer is formed from a material with a dielectric constant less than 4, in particular less than 3. Particularly in the case of such mechanically unstable and relatively sensitive materials in relation to the action of mechanical force, a considerable improvement in the mechanical stability can thereby be achieved. It is particularly advantageous to form the electrically conductive structure below a bonding area of the upper metal layer, since large mechanical forces and damage and destruction result from the assembly or bonding of the electronic component, particularly in the area below the bonding area being able to lead.
  • FIG. 1 shows a sectional illustration of an electronic component according to the invention
  • FIG. 2 shows a perspective illustration of a first exemplary embodiment of an electrically conductive structure of the electronic component according to the invention
  • FIG. 3 shows a plan view of a second exemplary embodiment of an electrically conductive structure of the electronic component according to the invention
  • FIG. 4 shows a perspective illustration of a section of the electrically conductive structure according to FIG. 3.
  • An electronic component EB (FIG. 1) has a first insulation layer 1, which in the exemplary embodiment is formed from a material with a low dielectric constant.
  • An electrically conductive structure 2 is integrated into this first insulation layer 1.
  • the electrically conductive Structure 2 is designed as a capacitance structure and is constructed from the metal strips Mll to M33.
  • the metal strips Ml l M33 to extend in the z direction parallel to each other, wherein the metal strip to Mll M13, the metal strips are formed M21 to M23 and M31 to M33, the metal strips in each case in a metallization.
  • the metal strips Mll, M21 and M31 are arranged congruently to one another and electrically connected to one another by means of via connections V.
  • the metal strips M12, M22 and M32 are connected to a supply voltage potential - direct or alternating voltage.
  • the metal strips M12, M22 and M32 are connected to ground potential.
  • the capacitance structure is arranged in the first insulation layer 1 such that the
  • a further insulation layer 4b Adjacent to the first insulation layer 1 is a further insulation layer 4b, which is formed from a material with a high mechanical stability compared to the mechanical stability of the material of the first insulation layer 1. Components, for example transistors, are formed in this insulation layer 4b. This layer 4b is formed on a substrate, not shown.
  • Structure 2 which is designed as a capacitance structure, can also be designed in a variety of ways in addition to the shape shown in the exemplary embodiment.
  • the structures in Aparicio, R. and Hajimiri, A. are further design options: Capacity Limits and Matching Properties of Integrated Capacitors; IEEE Journal of Solid-State Circuits, Vol. 37, No. 3, 2002, pp. 384 - 393, which are shown there in FIGS 10 are shown in perspective.
  • the capacitance structure 2 can also be implemented as a grid structure or as a MOS structure in a semiconductor component.
  • An electrically conductive shielding layer 3 is formed on this structure 2 as a metal layer, which is arranged in a third insulation layer 4a.
  • the shielding layer 3 designed as a plate is arranged in the third insulation layer 4a such that the structure 2 is arranged completely below the shielding layer 3.
  • the third insulation layer 4a is designed as an oxide layer.
  • An upper metal layer 5 is formed on the third insulation layer 4a as a bond pad layer.
  • the bond pad layer 5 is connected to an electrically conductive region 7 via a contact hole 6 formed in the third insulation layer 4a. Both the contact hole 6 and the electrically conductive region 7 are arranged outside a bonding region BB of the bond pad layer 5.
  • the structure 2 is arranged essentially below the bonding area BB.
  • the bonding area BB is produced by removing, for example by exposure or etching, the layer 10 formed on the bond pad layer 5 or the oxide and nitride layers 8 and 9.
  • layer 10 is designed as a PSPI layer (photo-sensitive polyemide layer).
  • the shielding layer 3 is connected to ground potential, so that coupling of a signal applied to the bond pad layer 5 into the structure 2 or coupling of a signal applied to the structure 2 into the bond pad layer 5 can be prevented , If no shielding layer 3 is formed in the exemplary embodiment shown (FIG. 1), provision can also be made for the electrically conductive region 7 to be formed in the metallization plane in which the metal strips M31 to M33 are also arranged.
  • FIG. 2 shows a perspective illustration of the capacitance structure 2, the metal strips Mll, M21 and M31, the metal strips M12, M22 and M32 and the metal strips M13, M23 and M33 viewed in the y direction via only one via each. Connection V are contacted.
  • the electrical connection of the metal strips M12, M22 and M32 with ground potential and the electrical connection of the metal strips Mll, M21, M31, M13, M23 and M33 with supply voltage potential is carried out via via not shown
  • connections and not shown metal strips KM can both be formed in a second insulation layer, not shown, which has a higher mechanical stability than the first insulation layer 1 (FIG. 1).
  • the second insulation layer can be identical to the third insulation layer 4 shown in FIG. 1.
  • the material of the second insulation layer has a higher mechanical stability than the material of the first insulation layer 1.
  • the second insulation layer can, for example, be an oxide layer or a
  • FIG. 3 shows a top view (viewed in the negative y direction) of a further exemplary embodiment of an electrically conductive structure 2 of an electronic component according to the invention.
  • the electrically conductive structure 2 is designed as an inductance structure.
  • a spiral metal sheet MB4 which has a rectangular shape.
  • the metal track MB4 is integrated in the first insulation layer 1, which is not shown in this FIG. 3.
  • the inductance structure in the form of the spiral-shaped metal track MB4 can also be formed in several metallization levels, whereby, as in the exemplary embodiment of the capacitance structure according to FIGS.
  • an essential point of the invention can also be seen here, inter alia, in that the entire Metal track MB4 extends in the first insulation layer 1.
  • the metal track MB4 is contacted at its inner end of the spiral by means of via connections V with a contact metal strip KM, which is connected to a supply voltage potential.
  • the contact metal strip KM is produced in a higher metallization level (viewed in the y direction in accordance with FIGS. 1, 2 and 4) than the metallization level in which the metal track MB4 is formed and is formed in the second insulation layer.
  • a higher-level metallization level is understood here to mean such a metallization level which, viewed in the same direction, is further away from a substrate of an integrated circuit on which the electronic component EB according to the invention is arranged than the metallization level in which the electrically conductive structure 2 in Form of the capacitance structure and / or the inductance structure is formed.
  • the second insulation layer can be identical to the third insulation layer 4a shown in FIG. 1.
  • the outer second end of the spiral-shaped metal track MB4 is also electrically connected to a ground potential by a via connection (not shown) and a further contact metal strip KM (not shown).
  • This further metal strip KM can be arranged in the first insulation layer 1 (FIG. 1) or in the second or in a possibly higher insulation layer (viewed in the positive y direction).
  • the top view of the geometrical surface design of the electrically conductive structure 2 is of secondary importance for the invention (FIG. 3).
  • the spiral metal path according to FIG. 3 can also be square.
  • the capacitance structure according to FIG. 2 can have a rectangular or square outline, for example, in a plan view in the negative y direction.
  • the geometric surface design in particular the outline and thus the dimensions of the electrically conductive structure, is selected such that the surface of the bonding region BB of the first metal layer 5 is completely in it when projected onto the outline surface of the electrically conductive structure Outline area of the electrically conductive structure is included.
  • FIG. 4 shows a perspective sectional illustration of the area I shown in FIG. 3.
  • an electrically conductive structure 2 designed as an inductance structure is integrated in the first insulation layer 1 and is formed in four metallization levels.
  • One of the metal tracks MB1 to MB4 is formed in each of the metallization levels, each of which is electrically contacted via via connections V.
  • the via connections can be designed as vertical columns or as elongated strands running parallel to the metal tracks MB1 to MB4. Due to the so-called hierarchical interconnect technology, the metal tracks MB1 to MB4 can be formed with increasing distance (positive y-direction) to substrate S with a larger cross-section (xy-plane) and with increasing distance (positive y-direction) to one another.
  • the second insulation layer (not shown), in which the contact metal strip KM is arranged, can be formed directly adjacent to the first insulation layer 1.
  • Layers 3 to 10 corresponding to FIG. 1 can be arranged above this.
  • the inductance structure 2 in the form of the metal coils MB1 to MB4 is also such formed that the surface areas of the metal sheet MB4 and the surface areas of the metal sheet MB1 are flat (viewed in the xz plane) with the surface of the first insulation layer 1.
  • the course of the metal track MB4 within the first insulation layer 1 is dashed and shown as an example for the course of the metal tracks MB1 to MB3.
  • the first insulation layer 1 directly adjoins the insulation layer 4b, the insulation layer 4b being formed on the substrate S.
  • the electrically conductive structure 2 can be designed such that it has a first partial structure corresponding to a capacitance structure according to the exemplary embodiment in FIGS. 1 or 2 and a second partial structure corresponding to an inductance structure according to the exemplary embodiment in the figures 3 or 4.
  • a mechanical stabilization structure and two passive electronic components can be realized with the electrically conductive structure.
  • the substructures can be arranged next to one another or one above the other.
  • the electrically conductive structure can be implemented in a variety of ways and is not limited to the exemplary embodiments shown.
  • the electrically conductive structure can also be formed in two or more than four metallization levels.
  • the insulation layers can each be made up of several layers. It can also be provided that the capacitance structure according to FIGS. 1 and 2 is formed only in one metallization level and, for example, only the metal strips M11, M12 and M13 are produced.
  • the electronic component according to the invention and the method for producing the electronic component by means of the suitable formation (shaping) and arrangement of a single electrically conductive one formed in an insulation layer, in particular a dielectric layer made of a material with a low dielectric constant Structure both a passive component and a mechanical support or stabilization structure for the electronic component EB, in particular for the insulation layer in which the electrically conductive structure is formed, against damage caused by mechanical force, for example when bonding or assembling the component in one Housing.
  • the area under the bond pad layer that is otherwise essentially not required in the electronic component EB is optimally utilized, which results in a component topology with minimized dimensions and optimized functional use.
  • the electrically conductive structure has a double function on the one hand in the form of at least one passive electronic component and on the other hand as a mechanical stabilization structure for the electronic component EB and in particular for the first insulation layer.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

L'invention concerne un composant électronique (EB) présentant une première couche d'isolation (1) sur laquelle est déposée une première couche métallique (5). Cette première couche d'isolation (1) intègre une structure électroconductrice (2) qui stabilise mécaniquement cette couche d'isolation (1) lors de la métallisation et/ou de l'assemblage du composant (EB), ladite structure étant conçue en tant que composant électronique passif.
EP03753282.7A 2002-10-22 2003-09-09 Composant electronique a composant electronique passif integre et procede de fabrication dudit composant Expired - Lifetime EP1556899B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10249192 2002-10-22
DE10249192A DE10249192A1 (de) 2002-10-22 2002-10-22 Elektronisches Bauelement mit integriertem passiven elektronischen Bauelement und Verfahren zu dessen Herstellung
PCT/DE2003/002987 WO2004040646A1 (fr) 2002-10-22 2003-09-09 Composant electronique a composant electronique passif integre et procede de fabrication dudit composant

Publications (2)

Publication Number Publication Date
EP1556899A1 true EP1556899A1 (fr) 2005-07-27
EP1556899B1 EP1556899B1 (fr) 2015-08-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP03753282.7A Expired - Lifetime EP1556899B1 (fr) 2002-10-22 2003-09-09 Composant electronique a composant electronique passif integre et procede de fabrication dudit composant

Country Status (8)

Country Link
US (1) US7193263B2 (fr)
EP (1) EP1556899B1 (fr)
JP (1) JP4391419B2 (fr)
KR (1) KR100815655B1 (fr)
CN (1) CN100459112C (fr)
DE (1) DE10249192A1 (fr)
TW (1) TWI241635B (fr)
WO (1) WO2004040646A1 (fr)

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DE102005045056B4 (de) 2005-09-21 2007-06-21 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Kondensator
DE102005045059B4 (de) * 2005-09-21 2011-05-19 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Spule sowie Verfahren zur Herstellung
JP5090688B2 (ja) * 2006-08-17 2012-12-05 ルネサスエレクトロニクス株式会社 半導体装置
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US7193263B2 (en) 2007-03-20
DE10249192A1 (de) 2004-05-13
TW200421449A (en) 2004-10-16
KR100815655B1 (ko) 2008-03-20
JP4391419B2 (ja) 2009-12-24
JP2006504274A (ja) 2006-02-02
EP1556899B1 (fr) 2015-08-12
TWI241635B (en) 2005-10-11
KR20050071600A (ko) 2005-07-07
WO2004040646A1 (fr) 2004-05-13
CN100459112C (zh) 2009-02-04
US20050199934A1 (en) 2005-09-15
CN1689156A (zh) 2005-10-26

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