EP1596277A1 - Detecteur de mises en forme - Google Patents

Detecteur de mises en forme Download PDF

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Publication number
EP1596277A1
EP1596277A1 EP04712708A EP04712708A EP1596277A1 EP 1596277 A1 EP1596277 A1 EP 1596277A1 EP 04712708 A EP04712708 A EP 04712708A EP 04712708 A EP04712708 A EP 04712708A EP 1596277 A1 EP1596277 A1 EP 1596277A1
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Prior art keywords
pattern
detection
signal
data
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP04712708A
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German (de)
English (en)
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EP1596277A4 (fr
Inventor
Hiroyuki Sony Lsi Design Inc. OTAKE
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Sony Corp
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Sony Corp
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Publication of EP1596277A1 publication Critical patent/EP1596277A1/fr
Publication of EP1596277A4 publication Critical patent/EP1596277A4/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/02—Indexing scheme relating to groups G06F7/02 - G06F7/026
    • G06F2207/025—String search, i.e. pattern matching, e.g. find identical word or best match in a string

Definitions

  • the present invention relates to a pattern detection apparatus.
  • the present invention relates to a pattern detection apparatus (a pattern search apparatus) detecting (searching) whether or not data having a predetermined pattern exists in data stores in a memory or data inputted from the outside.
  • Kokai Japanese unexamined patent publication
  • Kokai Japanese unexamined patent publication
  • Kokai Japanese unexamined patent publication
  • Kokai Japanese unexamined patent publication
  • No. H9 Japanese unexamined patent publication
  • search usually (hereinafter, described as a detection target pattern or an entry pattern) by using the detection target pattern in a pattern detection circuit (pattern search apparatus) to detect whether or not data having a predetermined pattern exists in data of search target.
  • data is read out sequentially with moving a readout address in a memory space in which data to become a detection target is stored, and the data is compared whether or not it agrees with an entry pattern.
  • the readout address when agreeing is stored in storage means as a detection position (or a match position).
  • This match position shows in which position of the memory space data having an arrangement equivalent to the entry pattern exists.
  • desired data processing is performed by using the match position as a mark.
  • a comparison circuit and a detection position registration circuit are included.
  • stored data is read out sequentially from a memory space of a search target and the readout data is compared whether or not it agrees with an entry pattern. Then, a detection agreement signal (a hit signal) is outputted from the comparison circuit when agreeing with the comparison target.
  • the detection position storage circuit is composed of a register, a memory and so on. When receiving the hit signal from the comparison circuit, the detection position storage circuit holds a count value from a search position, namely, the readout address at that time or a predetermined reference position in the register, the memory and so on.
  • a register having bit widths of number of the hit signals or a memory having a capacity of number of the hit signals becomes necessary.
  • number of the match position is defined as m
  • a register having bit widths of a total of 2 n ⁇ m or a memory of a total of 2 n ⁇ m addresses becomes necessary.
  • an amount of a hardware resource (resource) such as a register and a memory which is necessary to store the match positions also increases.
  • a compressed and coded data series (hereinafter, referred to as a bit stream or a data stream) is performed in a system layer and a video layer respectively.
  • a bit stream of MPEG is placed as one byte code for every system layer or video layer following a head of three bytes identification code [0x000001] as exemplified in FIG. 3A and FIG. 4 to FIG. 7.
  • a plurality of kinds of a system identification code is defined as a system layer and a plurality of a start code (start code) is defined as a video layer.
  • pattern detection is performed by using a detected stream ID as an entry pattern. Further, in detection of a video layer, pattern detection is performed by using a start code desired to be detected as an entry pattern.
  • a bit stream is read out from a memory sequentially with defining the data [0x000001] as an entry pattern and pattern detection is performed. Then, following detection of the data [0x000001], pattern detection is performed by defining one byte code, for example, a stream ID of a system layer or a start code of a video layer as an entry pattern. For this reason, a large amount of register or memory becomes necessary to store match positions. Further, a quite large amount of hardware resource is necessary to store entry patterns.
  • a hardware resource for holding match positions can be reduced by performing processing sequentially for every hit, although, the overhead for pattern detection and condition branching after hitting becomes large. For reducing this overhead, pattern detection of a certain large unit becomes necessary. For attaining this, a mechanism performing pattern detection with assembling a memory space which becomes a detection target in a pattern detection circuit to some degree becomes necessary, however, this is not equipped usually, therefore there is a disadvantage that reduction of the overhead of pattern detection cannot be realized.
  • the present invention was made in consideration of such a circumstance, the object is to provide a pattern detection circuit enabling to save a resource for storing a detection pattern and a detection position and enabling to reduce the overhead of processing after pattern is detected when detecting data having a desired pattern from a memory space becomes a search target by pattern matching.
  • a pattern detection circuit of the present invention has detection pattern storage means of storing an entry pattern to become a detection target, flag storage means of storing a flag signal corresponding to each the entry pattern, comparison means of comparing inputted data with the entry pattern stored in the detection pattern storage means, and detection position storage means of storing the detection position in response to a flag signal corresponding to the entry pattern stored in the flag storage means when the inputted data is corresponding to the entry pattern as a result of a comparison by the comparison means.
  • the pattern detection apparatus of the present invention has additionally detection position storage control means setting a pattern detection window signal in an active state, when showing that the flag signal corresponding to the entry pattern stores a detection position, and setting the pattern detection window signal in an inactive state, when showing that the flag signal corresponding to the entry pattern does not store a detection position, in the case of judging that the input data and the entry pattern agree.
  • the detection position storage means stores a detection position of the entry pattern when the pattern detection window signal is in an active state, and does not store a detection position of the entry pattern when the pattern detection window signal is in an inactive state.
  • the input data is moving image data and audio data compressed and coded in accordance with the MPEG standard, and the entry pattern is set in response to identification data showing a head of packets included in the compressed and coded data.
  • a flag signal is set for every entry pattern of a search target.
  • Input data and an entry pattern are compared by comparison means, as a result of the comparison, in the case that the input data agrees with the entry pattern in accordance with whether or not the flag signal corresponding to the entry pattern is effective, namely, whether or not the flag signal shows storage of a detection position, the entry pattern and the detection position are stored when showing the storage of the detection position, and, on the contrary, the storage of the detection position is not performed when showing that the flag signal does not store the detection position. For this reason, it becomes possible to specify a necessary registered detection position preliminarily, and it becomes possible to utilize a resource of storage means storing the detection position efficiently.
  • FIG. 1 is a block diagram showing an embodiment of a pattern detection apparatus according to the present invention.
  • a pattern detection apparatus 100 of the present embodiment has a plurality of comparison units 120-1 to 120-N (N > 0, N is an integer), a pattern detection/non-detection control unit 130 and a detection position registration unit 140.
  • a memory/bit stream interface (MEM/BS-I/F: Bitstream I/F, hereinafter, memory/BS-I/F) 110 provides input data IND and a readout pointer RDP, for example, read out from storage means to the pattern detection apparatus 100. It is a video signal coded by the MPEG illustrated in FIG. 3A as the input data IND, and it is an address of the video signal and so on as the readout pointer RDP.
  • the first comparison unit 120-1 has a comparator 122, an entry pattern holding unit 124 holding a detection target pattern or the entry pattern ETP1 and a flag holding unit holding a flag FLG1.
  • Number of the comparison units 120-1 to 120-N is corresponding to the entry pattern ETP1 to ETPN to become the detection target.
  • the entry pattern ETP1 to ETPN and the flag FLG1 to ETPN correspond one-on-one such as the entry pattern ETP1 and the flag FLG1.
  • the entry patterns ETP1 to ETPN are patterns to become targets of detection among data included in the input data IND. A detailed exemplification of the entry patterns ETP1 to ETPN will be described by referring to FIG. 3A.
  • Each of the flags FLG1 to FLGN is corresponding to each of the entry patterns ETP1 to ETPN and, for example, as amplified by referring FIG. 7, is composed of set data SET including a set use signal of a set/reset flip-flop 133 in the pattern detection/non-detection control unit 130 illustrated in FIG. 2 and reset data (or clear data CLR) that is a reset use signal.
  • the comparator 122 compares the input data IND inputted from the memory/BS-I/F 110 outside of the pattern detection apparatus 100 and the first entry pattern ETP1 inputted from the entry pattern holding unit 124 and outputs a first hit signal HIT1 in response to a result of the comparison.
  • the comparator 122 outputs, for example, a high level (1) hit signal HIT1 when the input data IND and the first entry pattern ETP1 are corresponding, and outputs a low level (0) hit signal HIT1 in the case of disagreement.
  • the entry pattern holding unit 124 stores the first entry pattern ETP1 inputted from the outside of the pattern detection apparatus 100, reads out the stored first entry pattern ETP1 and outputs it to the comparator 122.
  • the flag holding unit 126 holds a flag signal FLG1 inputted from the outside of the pattern detection apparatus 100 and outputs the held first flag FLG1 as a first control signal CTL1 when the first hit signal HIT1 that is a comparison result of the comparator 122 is in a high level.
  • the control signal CTL1 is composed of the set signal and the clear signal as well as the flag FLG 1.
  • the pattern detection-non-detection control unit 130 generates a pattern detection window signal PDW controlling the registration of a detected match position in response to the control signals CTL1 to CTLN outputted from the comparator 120-1 to 120-N.
  • a pattern detection window signal PDW controlling the registration of a detected match position in response to the control signals CTL1 to CTLN outputted from the comparator 120-1 to 120-N.
  • An example of the pattern detection window signal PDW is shown in FIG. 3B.
  • each of a plurality of the comparison units 120-1 to 120-N is composed of the comparator 122, the entry pattern holding unit 124 and the flag holding unit 126.
  • each the comparison unit a comparison of the inputted input data IND and the held entry patterns ETP1 to ETPN is performed, based on the result, the hit signals HIT1 to HITN and the control signals CTL1 to CTLN are outputted.
  • a plurality of the flags FLG1 to FLGN define control information for generation of the pattern detection window signal PDW about the corresponding entry patterns ETP1 to ETPN respectively.
  • the pattern detection/non-detection control unit 130 generates a holding enable signal HEB in response to the hit signals HIT1 to HITN and the control signals CTL1 to CTLN from a plurality of comparison units 120-1 to 120-N and outputs it to the detection position registration unit 140 storing (registering) the readout pointer RDP outputted from the memory/BS-I/F 110.
  • FIG. 2 shows a configuration example of the pattern detection/non-detection control unit 130.
  • the pattern detection/non-detection control unit 130 has OR gates 131, 132-1 and 132-2, a reset/set type flip-flop 133 and an AND gate 134.
  • the OR gate 131 operates logical addition (OR) of a plurality of the hit signals HIT1 to HITN outputted from a plurality of the comparison unit 120-1 to 120-N and outputs, for example, the high level (1) hit signal HIT to an AND gate 134 if there is a high level hit signal even at one among a plurality of hit signals HIT1 to HITN as a result of the operation.
  • the OR gate 131 outputs the low level (0) hit signal HIT when all of a plurality of the hit signals HIT1 to HITN are in a low level.
  • the OR gate 132-1 operates logical addition of a plurality of set signals SET1 to SETN included in a plurality of the control signals CTL1 to CTLN outputted from a plurality of the comparison units 120-1 to 120-N.
  • the OR gate 132-1 inputs it to a set signal input terminal S of the RS flip-flop 133 as, for example, a high level (1) set signal SET.
  • the OR gate 132-1 outputs the low level (0) set signal SET when all of a plurality of the set signals SET1 to SETN are in a low level.
  • the OR gate 132-2 operates logical addition of clear signals CLR1 to CLRN included in a plurality of the control signals CTL1 to CTLN outputted from a plurality of the comparison units 120-1 to 120-N. As a result of the operation, if there is a high level clear signal even at one among a plurality of clear signals CLR1 to CLRN, the OR gate 132-2 inputs it to a reset signal input terminal R of the RS flip-flop 133 as, for example, a high level (1) reset signal RST. On the other hand, the OR gate 132-2 outputs the low level (0) clear signal CLR when all of a plurality of the clear signals CLR1 to CLRN are in a low level.
  • the RS flip-flop 133 outputs the pattern detection window signal PDW in response to the set signal SET inputted from the OR gate 132-1 and the reset signal RST inputted from the OR gate 132-2. Namely, the RS flip-flop 133 outputs a high level (1) pattern detection window signal PDW when the high level (1) set signal SET is applied to the set signal input terminal S, and defines the pattern detection window signal PDW to a low level (0) when the high level (1) reset signal RST is applied to the reset signal input terminal R.
  • the AND gate 134 operates logical multiplication of the hit signal HIT from the OR gate 131 and the pattern detection window signal PDW from the RS flip-flop 133, and outputs the high level (1) holding enable signal HEB to the detection position registration unit 140 only when the hit signal HIT and the pattern detection window signal PDW are in a high level together.
  • a high level hit signal HIT is outputted from the OR gate 131.
  • the set signal SET is outputted by the OR gate 132-1.
  • an active state for example, a high level pattern detection window signal is outputted from the RS flip-flop 133.
  • the hit signal HIT outputted from the OR gate 131 is outputted as the holding enable signal HED via the AND gate 134.
  • the reset signal RST is outputted by the OR gate 132-2.
  • an inactive state for example, a low level pattern detection window signal is outputted from the RS flip-flop 133.
  • output of the AND gate 134 is also held in a low level, at this time, the hit signal HIT outputted from the OR gate 131 is ignored (becomes invalid state).
  • the detection position registration unit 140 has a plurality of registers 1 to M.
  • the detection position registration unit 140 performs a registration of the readout pointer RDP outputted from the memory/BS-I/F 110 with defining it as a detection position that data agreeing with the entry pattern existed in accordance with the holding enable signal HEB from the pattern detection/non-detection control unit 130.
  • the holding enable signal HEB from the pattern detection/non-detection control unit 130 is monitored, when the holding enable signal HEB is in a high level of an active state, the readout pointer RDP outputted from the memory/BS-I/F 110 is stored in the register 1 to the register M sequentially.
  • the holding enable signal HEB is generated in response to a plurality of the control signals HIT1 to HITN and a plurality of control signals CTL1 to CTLN from a plurality of the comparator 120-1 to 120-N, and supplied to the detection position registration unit 140.
  • the detection position registration unit 140 stores the readout pointer RDP inputted from the memory/BS-I/F 110 in a corresponding register among the register 1 to the register M when the holding enable signal HEB is in a high level of an active level.
  • the registration of the detection position can be performed in the register 1 to the register M for only a necessary pattern among the detected entry patterns.
  • a hardware resource of the pattern detection apparatus 100 can be used effectively.
  • the input data IND inputted from the memory/BS-I/F 110 to the pattern detection apparatus 100 of the present invention is moving image or audio data compressed and coded in accordance with a predetermined coding standard, for example, the MPEG standard.
  • the compressed and coded data is read out from the memory or the other recording media, and supplied to the pattern detection apparatus 100 of the present invention in a from of becoming the bit stream, namely, a series of contiguous data via the memory/BS-I/F 110.
  • the readout pointer RDP showing a detection position is also outputted at the same time as the bit stream.
  • the readout pointer RDP is a count value increasing by a predetermined unit at the time of a pointer of reading out the data IND from the memory (for example, a readout address) or a predetermined time point as a starting point.
  • the bit stream compressed and coded in accordance with the MPEG standard is separated by a packet unit as shown in FIG. 3A.
  • FIG. 3A an example of moving image and audio data in accordance with the MPEG standard is shown.
  • PES_packet a PES packet
  • system header Following a system header start code showing a start of the system header, attribute information and so on is included.
  • the PES packet composed of the video data, namely the compressed and coded moving image data
  • the PES packet composed of the audio data, namely the compressed and coded audio data.
  • a video stream start code or an audio stream start code showing a start of the packet is arranged.
  • FIG. 4 shows an example of a stream identification number (stream ID) of the system layer.
  • FIG. 5 shows an example of the start code of the video layer. Note that, the stream ID or the start code shown in FIG. 4 and FIG. 5 is arranged following a three byte code [0x000001].
  • FIG. 6 is a view showing the entry pattern for detecting the start code of each layer.
  • the entry pattern for detecting the packet start code is 32 bits (four bytes) data [0x000001ba]
  • the entry pattern for detecting the system header start code is four bytes data [0x000001bb].
  • the entry pattern for detecting the audio stream start code becomes four bytes data [0x000001c-] or [0x000001d-], and the entry pattern for detecting the video stream start code becomes four bytes data [0x000001e-].
  • a hyphen "-" means either of four bytes data [0 to 9 and a to f (a corresponds to 10 in the decimal notation and f corresponds to 15)] in the hexadecimal notation.
  • the entry patterns ETP1 to ETPN desired to be detected preliminarily and the flag signals corresponding to them are set.
  • the entry patterns are held by the entry pattern holding unit 124 and the flag signals are held by the flag holding unit 126. Therefore, in each comparison unit, a comparison between the input data IND provided from the memory/BS-I/F 110 and the entry patterns is performed by the comparator 122. As a result, when the input data IND and the entry pattern agree, the hit signal HIT1 is outputted, then, the flag FLG1 held by the flag 126 is outputted as the control signal.
  • FIG. 7 shows an example of the entry patterns ETP1 to ETPN desired to be detected and the flag signals FLG1 to FLGN corresponding to each entry pattern in the pattern detection apparatus 100 of the present embodiment.
  • the flag signals FLG1 to FLGN are composed of, for example, two bits data, and these two bits are the set signal SET and the clear signal (or the reset signal) CLR controlling the RS flip-flop as shown in FIG. 7.
  • the flag signal is held by the flag holding unit 126 shown in FIG. 1.
  • the flag holding unit 126 generates the control signals CTL1 to CTLN, namely, the set signals SET1 to SETN and the clear signals CLR1 to CLRN in response to the flag signals FLG1 to FLGN.
  • the flag signal takes four states of (1, 1), (1, 0), (0, 1) and (0, 0).
  • the contents of each state are as follows.
  • the packet start code namely, the flag signal corresponding to a 32 bits entry pattern [0x000001ba] is set as (1, 0).
  • the video stream start code namely, the flag signal corresponding to an entry pattern [0x00000e-] is set as (0, 1).
  • the audio stream code namely the flag signal corresponding to an entry pattern [0x000001c-] or [0x000001d-] is set as (0, 1) together.
  • the flag signal corresponding to an entry pattern [0x000001b-] is set as (0, 0).
  • the pattern detection apparatus 100 of the present embodiment detects a data series agreeing with the entry pattern from the inputted data stream, and further registers each detection position, namely, match position in the corresponding register of the detection position registration unit 140 in response to the flag signal corresponding to each entry pattern.
  • the pattern detection/non-detection control unit 130 when a data series agreeing with the packet start code, namely, the entry pattern [0x000001ba] is detected, since the flag signal corresponding to the entry pattern is (1, 0), in the pattern detection/non-detection control unit 130, the pattern detection window signal PDW is held in an active state, for example, a high level, in response to this, the holding enable signal HEB in an active state is outputted by the pattern detection/non-detection control unit 130. Consequently, in the detection position registration unit 140, the match position corresponding to the packet start code is registered in the corresponding register.
  • a PES packet is inputted following a packet header having the packet start code as a head.
  • a video stream start code is arranged in the head of the PES packet. Namely, the video stream start code that is in the head of the EPS packet is detected by the entry pattern [0x000001e-].
  • the pattern detection/non-detection control unit 130 since the pattern detection window signal PDW is in an active state, the holding enable signal HEB is outputted in response to the hit signal HIT as shown FIG. 3. In response to this, in the detection position registration unit 140, the match position is registered. Further, as shown in FIG.
  • the pattern detection window signal PDW is changed to an inactive state, for example, a low level as shown in FIG. 3. Therefore, since the hit signal HIT detected in response to the entry pattern, for example, a user data start code [0x000001b2], a group start code [0x000001b8] and so on becomes invalid in a period of the PES packet, a registration of the match positions corresponding to these entry patterns is not performed.
  • the pattern detection apparatus 100 of the present embodiment when the entry pattern [0x000001ba] corresponding to the packet start code is detected, since the pattern detection window signal PDW is set in an active state in response to the flag signal (1, 0) corresponding to the entry pattern, the holding enable signal HEB is outputted in response to the hit signal HIT by the pattern detection/non-detection control unit 130. For this reason, in the detection position registration unit 140, the match position in response to the entry pattern is registered in the register. Then, when the video stream code in the head of the PES packet is detected, since the flag signal corresponding to the entry pattern [0x000001e-] is set as (0, 1), the pattern detection window signal PDW is set in an inactive state. Even if the hit signal HIT is outputted after this time in response to this, since a registration of the match position is not performed, only necessary match positions are registered, the efficiency of the hardware resource, foe example, the register, of the detection position registration unit 140 can be improved.
  • the pattern detection apparatus 100 of the present embodiment in the case that the PES packet of the video stream is inputted following the packet start code as mentioned above, and even in the case that the PES packet of the system header and the audio stream is inputted following the packet start code, in the pattern detection/non-detection control unit 130, the pattern detection window signal PDW is controlled correctly, and a registration of the match positions can be performed for only necessary hit signals.
  • the packet stream code in the head of the packet header is detected by the entry pattern [0x000001ba]. Then, the detected match position is registered in the register in the detection position registration unit 140. Further, since the flag signal corresponding to the entry pattern at this time is (1, 0), the pattern detection windows signal PDW is set in an active state in the detection unit is set in an active state in the pattern detection/non-detection control unit 130.
  • the system header start code in the head of the system header is detected by the entry pattern [0x000001b-]. Further, as shown in FIG. 7, since the flag signal corresponding to the entry pattern [0x000001b-] is (0, 0), by this detection, a state of the pattern detection window signal PDW of the pattern detection/non-detection control unit 130 does not change and it is held in an active state.
  • the audio stream start code in the head of that is detected by the entry pattern [0s000001c-] or [0x000001d-].
  • the flag signal corresponding to the entry pattern [0x000001c-] or [0x000001d-] is (0, 1).
  • the pattern detection window signal PDW of the pattern detection/non-detection control unit 130 is changed to an inactive state. Therefore, even if a hit signal HIT is obtained by the other entry pattern in a period of the PES packet of the audio stream, the holding enable signal is not outputted and a registration of the match position is not performed.
  • each comparison unit an entry pattern desired to be detected and a flag signal corresponding to the entry pattern are stored by the entry pattern holding unit 124 and the flag holding unit 126, the input data IND and the entry pattern held by the entry pattern holding unit 124 are compared by the comparator 122, when agreeing, a hit signal is outputted, the control signal is outputted in response to the flag signal held by the flag holding unit 126, the holding enable signal HEB is outputted in response to the hit signal and the control signal in the pattern detection/non-detection control unit 130 only when a necessary entry pattern is detected, and in response to this, the entry pattern and the detection position are registered in the detection position registration unit 140. Therefore, the detection position for only necessary hit detections can be registered, and it becomes possible to utilize a resource of hardware such efficiently as a register in the detection position registration unit 140 for registering the detection position.
  • a plurality of the register 1 to the register M in the detection position registration unit 140 can be replaced to semiconductor storage apparatuses such as a RAM.
  • the entry pattern holding unit 124 and the flag holding unit 126 can be configured by a semiconductor memory and so on.
  • the flag holding unit 126 may only have a function outputting the held flag FLG1 when the first hit signal HIT1 is outputted from the comparator 122, namely, a gate function.
  • the entry pattern holding unit 124 and the flag holding unit 126 are realized with a semiconductor memory
  • the entry pattern holding unit 124 and the flag holding unit 126 in each of the comparison units 120-1 to 120-N can be realized with one semiconductor memory. Therefore, the configuration example of FIG. 1 is conceptual, actually, a plurality of the entry pattern holding units 124 and a plurality of the flag holding units 126 in a plurality of the comparison units 120-1 to 120-N can be configured with one semiconductor memory and so on.
  • pattern detection apparatus of the present invention illustrated in FIG. 1 can be configured as one semiconductor integrated apparatus.
  • an application target of the pattern detection apparatus of the present invention is not limited to the video signal and so on.
  • the case that two or more data to be a search target is extracted from among data stored in the memory may be acceptable.
  • the readout pointer RDP described by referring to FIG. 1 corresponds to a readout address of the memory and so on.
  • the pattern detection apparatus of the present invention since in response to the flag signals set corresponding to each of the entry patterns (search target pattern), only necessary match positions are registered and other match positions can be discarded, a resource of the circuit registering the match positions (detection positions), namely, the register and the memory storing the entry patterns and the match positions corresponding to them can be used efficiently.
  • the pattern detection can be performed only in a necessary space, an agreement detection signal can be ignored in a zone unnecessary of detecting, and the overhead of the processing can be reduced.

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EP04712708A 2003-02-21 2004-02-19 Detecteur de mises en forme Withdrawn EP1596277A4 (fr)

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JP2003044407A JP3807379B2 (ja) 2003-02-21 2003-02-21 パターン検出回路
JP2003044407 2003-02-21
PCT/JP2004/001894 WO2004084062A1 (fr) 2003-02-21 2004-02-19 Detecteur de mises en forme

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EP1596277A1 true EP1596277A1 (fr) 2005-11-16
EP1596277A4 EP1596277A4 (fr) 2008-07-02

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JP (1) JP3807379B2 (fr)
KR (1) KR20050108343A (fr)
CN (1) CN100530075C (fr)
WO (1) WO2004084062A1 (fr)

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WO2004084062A1 (fr) 2004-09-30
CN1751289A (zh) 2006-03-22
EP1596277A4 (fr) 2008-07-02
JP2004266370A (ja) 2004-09-24
KR20050108343A (ko) 2005-11-16
CN100530075C (zh) 2009-08-19
JP3807379B2 (ja) 2006-08-09

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