EP1597756A2 - Technique de liaison pour semi-conducteurs de puissance presentant des zones de connexion etendues - Google Patents

Technique de liaison pour semi-conducteurs de puissance presentant des zones de connexion etendues

Info

Publication number
EP1597756A2
EP1597756A2 EP04704561A EP04704561A EP1597756A2 EP 1597756 A2 EP1597756 A2 EP 1597756A2 EP 04704561 A EP04704561 A EP 04704561A EP 04704561 A EP04704561 A EP 04704561A EP 1597756 A2 EP1597756 A2 EP 1597756A2
Authority
EP
European Patent Office
Prior art keywords
layer
component
insulating material
electrically insulating
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04704561A
Other languages
German (de)
English (en)
Inventor
Norbert Seliger
Karl Weidner
Jörg ZAPF
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP1597756A2 publication Critical patent/EP1597756A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the chip surface is contacted via a solder that is introduced through holes in a ceramic plate.
  • the contacts are made using soldered copper posts.
  • DCB Direct Copper Bonding
  • Power semiconductors are applied to a film stretched in a frame.
  • the object of the invention is to provide a method for contacting one or more electrical contact surfaces of a component located on a substrate, which is suitable for power electronics and in which there is the possibility of contacting adapted to high powers.
  • the electrical contact surface of the component is at least partially exposed.
  • a window is opened with more than 60% of the size of the side and / or surface of the component on which the window is opened, in particular more than 80%.
  • the method is therefore particularly suitable for power components for which a contact window and a contact area of appropriate size are provided when contacting a flat conductor.
  • the window is opened in particular on the largest and / or on the side of the component facing away from the substrate and preferably has an absolute size of more than 50 mm 2 , in particular more than 70 mm 2 or even more than 100 mm 2 .
  • the layer of electrically insulating material can also be applied in such a way that the contact surface of the component remains at least partially free - by a window with more than 60% of the size of the side and / or surface of the Component is open, on which the window is open, in particular more than 80%.
  • the complete or partial release already during application can be realized particularly advantageously if the layer of electrically insulating material is applied in the form of a film. Then a film with one or more corresponding openings or windows can be used from the outset, which can be produced beforehand, for example, by inexpensive punching or cutting.
  • a layer of electrically conductive material is applied to the layer of electrically insulating material and the electrical contact surface of the component.
  • the layer of electrically insulating material is therefore a carrier layer for the layer of electrically conductive material.
  • the size of the window should not be more than 99.9% of the size of the side and / or area of the component on which the window is opened, in particular not more than 99% and more preferably not more than 95%.
  • the substrate For contacting the component with the substrate, the substrate preferably has an electrical contact surface which remains free and / or is exposed and to which the layer of electrically conductive material is likewise applied.
  • the contact surface of the component is connected to the contact surface of the substrate via the layer of electrically conductive material.
  • the contact area of the component and the contact area of the substrate are preferably approximately the same size in order to ensure a continuous current flow.
  • the substrate and the component form a surface contour.
  • the layer of electrically insulating material is applied in particular on the substrate and the component in such a way that the layer of electrically insulating material follows the surface contour formed from the substrate and the component, that is to say that the layer of electrically insulating material corresponds to the surface contour formed from the substrate and component runs on the surface contour. If, on the other hand, logic chips are embedded in a polymer according to the prior art, only the underside of the polymer layer follows the surface contour, but not the polymer layer itself. Because the layer of electrically insulating material follows the surface contour formed from the substrate and the component, there are two advantages, in particular if a power component is used as the component.
  • the layer of electrically insulating material is not so thick that it would be problematic to expose and contact contact surfaces on the substrate's conductor tracks.
  • the thickness of the layer of electrically insulating material above the substrate in its rectilinear region deviates by less than 50% from its thickness above the component in its rectilinear region, in particular by less than 20%.
  • the thicknesses are preferably approximately the same, that is to say deviate from one another by less than 5% or even less than 1%.
  • the percentages relate in particular to the thickness of the layer above the component in its rectilinear area, which accordingly indicates 100%.
  • the rectilinear area is used because the layer in the inner edges of the substrate and the component is generally thicker, and generally thinner over the edges of the component facing away from the substrate.
  • any substrates on an organic or inorganic basis can be used as substrates.
  • substrates are, for example, PCB (Printed Circuit Board), DCB, IM (Insulated Metal), HTCC (High Temperature Cofired Ceramics) and LTCC (Low Temperature Cofired Ceramics) substrates.
  • the layer of electrically insulating material is in particular made of plastic. Depending on the further processing, it can be photosensitive or non-photosensitive.
  • curtain casting dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating, laminating a film.
  • the layer of electrically insulating material is not a film.
  • the lamination is advantageously carried out in a vacuum press. Vacuum deep drawing, hydraulic vacuum pressing, vacuum gas pressure pressing or similar laminating processes are also conceivable. The pressure is advantageously applied isostatically.
  • the lamination is carried out, for example, at temperatures from 100 ° C to 250 ° C and a pressure of 1 bar to 10 bar.
  • the exact process parameters of the lamination, i.e. pressure, temperature, time etc. depend among other things on the topology of the substrate, the plastic material of the film and the thickness of the film.
  • the film can consist of any thermoplastics, thermosets and mixtures thereof.
  • the film is preferably and advantageously a film made from a plastic material based on polyimide (PI), polyethylene (PE), polyphenol, polyether ether ketone (PEEK) and / or epoxy.
  • PI polyimide
  • PE polyethylene
  • PEEK polyether ether ketone
  • the film can have an adhesive coating to improve the adhesion to the surface.
  • the substrate surface can also be coated with an adhesion promoter, preferably silane compounds.
  • a tempering step is carried out in particular. Through temperature treatment and cross-linking adhesion, thermal, physical and mechanical properties of the film on the surface are improved.
  • the layer of electrically conductive material that is to say for two-dimensional contact
  • physical or chemical deposition of the electrically conductive material is advantageously carried out.
  • Such physical processes are sputtering and vapor deposition (Physical Vapor Deposition, PVD).
  • Chemical deposition can be carried out from the gaseous phase (Chemical Vapor Deposition, CVD) and / or liquid phase (Liquid Phase Chemical Vapor Deposition). It is also conceivable that a thin electrically conductive partial layer, for example made of titanium / copper, is first applied by one of these methods, on which a thicker electrically conductive partial layer, for example made of copper, is then deposited.
  • a substrate with a surface is used, which with one or more semiconductor chips, in particular
  • Power semiconductor chips is fitted, on each of which there is or are one or more contact surfaces to be contacted, and the layer of electrically insulating material is applied to this surface under vacuum, so that the layer of electrically insulating material covers this surface including each semiconductor chip and each Contact area closely covered and adheres to this surface including each semiconductor chip.
  • the layer of electrically insulating material is designed so that a height difference of up to 1000 ⁇ m can be overcome.
  • the height difference is caused, among other things, by the topology of the substrate and by the semiconductor chips arranged on the substrate.
  • the thickness of the layer of electrically insulating material can be 10 ⁇ m to 500 ⁇ m.
  • a layer of electrically insulating material with a thickness of 25 to 150 ⁇ m is preferably applied.
  • the application is repeated until a certain thickness of the layer of electrically insulating material is reached.
  • partial layers made of electrically insulating material of smaller thickness are processed to form a layer made of electrically insulating material of higher thickness.
  • These partial layers made of electrically insulating material advantageously consist of a type of plastic material. It is also conceivable that the partial layers of electrically insulating material consist of several different plastic materials. The result is a layer made of partial layers of electrically insulating material.
  • a window in the layer of electrically insulating material is opened by laser ablation to expose the electrical contact surface of the component.
  • a wavelength of a laser used for this is between 0.1 ⁇ m and 11 ⁇ m.
  • the power of the laser is between 1 W and 100 W.
  • a C0 laser with a wavelength of 9.24 ⁇ m is preferably used.
  • the windows are opened without damaging a chip contact made of aluminum, gold or copper, which may be under the layer of electrically insulating material.
  • a photosensitive layer made of electrically insulating material is used and a window is opened by a photolithographic process to expose the electrical contact surface of the component.
  • the photolithographic process includes exposing the photosensitive layer electrically insulating material and developing and thus removing the exposed or unexposed areas of the layer of electrically insulating material.
  • a cleaning step is optionally carried out in which remnants of the layer of electrically insulating material are removed.
  • the cleaning step is carried out, for example, by wet chemistry. In particular, a plasma cleaning process is also conceivable.
  • a layer of several partial layers of different, electrically conductive material arranged one above the other is used.
  • different metal layers are applied one above the other.
  • the number of sub-layers or metal layers is, in particular, 2 to 5.
  • a sub-layer functioning as a diffusion barrier can be integrated, for example, by the electrically conductive layer composed of a plurality of sub-layers.
  • Such a sub-layer consists, for example, of one
  • Titanium-tungsten alloy TiW
  • a partial layer that promotes or improves adhesion is advantageously applied directly to the surface to be contacted.
  • Such a partial layer consists, for example, of titanium.
  • At least one conductor track is produced from the electrically conductive material after the two-dimensional contacting and / or on the layer.
  • the conductor track can be applied to the layer.
  • the layer is structured to produce the conductor track.
  • the conductor track is used, for example, to make electrical contact with a semiconductor chip.
  • the structuring is usually carried out in a photolithographic process.
  • a photoresist can be applied to the electrically conductive layer, dried and then exposed and developed.
  • a tempering step may follow in order to stabilize the applied photoresist against subsequent treatment processes.
  • Conventional positive and negative resists (coating materials) can be used as photoresist.
  • the photo lacquer is applied, for example, by a spraying or dipping process.
  • another structurable material can be used with one or more of the following
  • Procedures are applied: curtain pouring, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating, laminating a film.
  • photosensitive foils can also be used, which are laminated on and exposed and developed in a manner comparable to the applied photoresist layer.
  • the following can be used to produce the conductor track: in a first sub-step, the electrically conductive layer is structured and in a subsequent sub-step a further metallization is applied to the conductor track produced.
  • the conductor track is reinforced.
  • copper is electrodeposited to a thickness of 1 ⁇ m to 400 ⁇ m on the conductor track produced by structuring.
  • the photoresist layer or the laminated film or the structurable material used alternatively is then removed. This can be done, for example, with an organic solvent, a alkaline developer or the like. Subsequent differential etching removes the flat, metallically conductive layer that is not reinforced with the metallization.
  • the reinforced conductor track is retained.
  • the steps of laminating, exposing, contacting and generating the conductor track are carried out several times to produce a multilayer device.
  • the invention advantageously provides a novel technology for the electrical contacting and wiring of connection pads or contact surfaces which are arranged on semiconductor chips, in particular on power semiconductor chips.
  • the flat connection and the special insulation result in a low-inductance connection in order to enable fast and low-loss switching.
  • An electrical insulation layer is produced by applying the layer of electrically insulating material.
  • the production of the insulation layer by applying the layer of electrically insulating material according to the invention offers the following advantages: Use at high temperatures. With a suitable choice of material, a layer of electrically insulating material is heat-resistant up to 300 ° C.
  • DCB substrates can be processed in the benefit.
  • the entire chip contact area can be used so that high currents can be derived.
  • the chips can be controlled homogeneously due to the flat contact.
  • the inductance of the contact in a contact area is smaller due to the areal geometry than with thick wire bonding.
  • Preferred and advantageous configurations of the device result from the preferred configurations of the method.
  • Figure 1 shows a method for contacting a power semiconductor.
  • the substrate of the example is generally designated 1 in FIG.
  • This substrate 1 has, for example, a DCB substrate, which consists of a substrate layer 10 made of ceramic material, a layer 12 made of copper applied to a lower surface of the substrate layer 10 and one on a side facing away from the lower surface Surface of the substrate layer 10 applied layer 11 consists of copper.
  • the layer 11 on the upper surface of the substrate layer 10 is in some areas up to the upper surface of the
  • Substrate layer 10 removed down so that the upper surface is exposed there.
  • Conductor tracks are formed on the substrate by the layers 11 and 12 made of copper.
  • One or more semiconductor chips 2 which may be the same and / or different from one another, are applied to the surface of the remaining layer 11 of copper facing away from the substrate layer 10.
  • the semiconductor chip 2 which is preferably a
  • the power semiconductor chip is in contact with a contact surface, not shown, which is present on a lower surface of the semiconductor chip 2 facing the layer 11 of copper, the area of the upper surface of the layer 11 of copper.
  • this contact surface with the
  • the contact area on the lower surface of this semiconductor chip 2 is the contact area of a collector or
  • the drain contact and the contact on the upper surface of the semiconductor chip 2 are an emitter or source contact, the contact area of which is the contact area 210.
  • the entire upper surface of the substrate 1 equipped with the semiconductor chip 2 is due to the exposed parts of the upper surface of the substrate layer 10, the upper one Surface of the layer 11 of copper outside of the semiconductor chips 2 and given by the free surface of each semiconductor chip 2 itself, which is determined by the upper surface and the side surface of this chip 2.
  • a layer 3 of electrically insulating plastic material is applied under vacuum to the entire surface of the substrate 1 equipped with the semiconductor chip 2, so that the layer 3 of electrically insulating material tightly contacts the surface of the substrate 1 equipped with the semiconductor chip 2 covered and adheres to this surface.
  • the layer 3 of electrically insulating material follows that through the exposed parts of the upper surface of the substrate layer 10, the upper surface of the layer 11 of copper outside the semiconductor chips 2 and through the free surface of each semiconductor chip 2 itself, through the upper surface and the lateral surface of this chip 2 is determined, given surface contour.
  • the layer 3 made of electrically insulating material is preferably applied in step 301 using one or more of the following procedures: curtain casting, dipping, in particular one-sided dipping, spraying, in particular electrostatic spraying, printing, in particular screen printing, overmolding, dispensing, spin coating.
  • the layer 3 made of electrically insulating material can also be applied particularly well by laminating on a film, in particular a film made of a plastic material based on polyamide or epoxy. A tempering step can follow for better adhesion.
  • the layer 3 made of electrically insulating material serves as an insulator and as a carrier for a layer 4 made of electrically conductive material that is applied further on.
  • Typical thicknesses of the layer 3 made of electrically insulating material are in the range of 25-150 ⁇ m, whereby larger thicknesses can also be achieved from layer sequences of thinner partial layers made of electrically insulating material. This advantageously enables insulation field strengths in the range of a few 10 kV / m to be achieved.
  • each contact surface to be contacted is exposed by opening a respective window 31 in the layer 3 made of electrically insulating material.
  • a contact area to be contacted is not only a contact area 210 on a semiconductor chip 2, but can also be any region of the upper surface of the layer 11 made of copper or another metal which is exposed by opening a window 31 in the layer 3 made of electrically insulating material.
  • the size of the window that is opened for contacting the contact area (210) is more than 60% of the size of the component, in particular more than 80%.
  • One of the windows 31 in the layer 3 made of electrically insulating material is preferably opened by laser ablation.
  • each exposed contact surface 210 of the component and exposed contact surface 112 of the substrate is surface-contacted with a layer 4 of electrically conductive material, preferably metal, by metallizing and structuring the exposed contact surfaces 210 and 112 using the usual methods and thus making planar contact become.
  • the layer 4 made of electrically conductive material can be applied over the entire area both to each contact surface 210 and 112 and also to the upper surface of the layer 3 made of electrically insulating material facing away from the surface of the substrate 1 and can then be structured photolithographically, for example, such that each contact surface 210 and 112 remains in contact with the surface and conductor tracks 4, 6 are formed running over the contact surfaces 210 and 112 and the layer 3 of insulating material.
  • step 303 Sputtering a Ti adhesive layer of approximately 100 nm in thickness and a Cu conductive layer 4 of approximately 200 nm in thickness.
  • a mask is applied, which leaves the contact areas 210 and 112 and areas for the conductor tracks 4, 6 running over the contact areas 210 and 112 and the layer 3 of ' insulating material, and then the layer 4 of the electrically conductive material over the entire surface of the mask and the contact surfaces 210 and 112 and those free of the mask Areas is applied.
  • the mask with the layer 4 located thereon is then removed, so that only the surface-contacted contact areas 210 and 112 and the conductor tracks 4, 6 running over the contact areas 210 and 112 and the layer 3 made of insulating material remain on the mask-free areas.
  • a device is then made of a substrate 1 with component 2 with a surface on which electrical contact surfaces 210, 112 are arranged, in which an insulator in the form of a layer 3 of electrically insulating material is applied to the surface is close to the surface and adheres to the surface and in which the layer 3 of electrically insulating material has windows 31 at the contact surfaces 210 and 112, in which this contact surface 210, 112 is free of the layer 3 of electrically insulating material and has a flat surface a layer 4 and for example additionally with a layer 6 made of electrically conductive material.
  • Special designs of this device result from the above description.

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé consistant à appliquer une couche d'un matériau électro-isolant sur un substrat et un composant surmontant ce substrat, de façon que ladite couche suive le contour de la surface formée par le substrat et le composant.
EP04704561A 2003-02-28 2004-01-23 Technique de liaison pour semi-conducteurs de puissance presentant des zones de connexion etendues Withdrawn EP1597756A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10308977 2003-02-28
DE10308977 2003-02-28
PCT/EP2004/000574 WO2004077547A2 (fr) 2003-02-28 2004-01-23 Technique de liaison pour semi-conducteurs de puissance presentant des zones de connexion etendues

Publications (1)

Publication Number Publication Date
EP1597756A2 true EP1597756A2 (fr) 2005-11-23

Family

ID=32920648

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04704561A Withdrawn EP1597756A2 (fr) 2003-02-28 2004-01-23 Technique de liaison pour semi-conducteurs de puissance presentant des zones de connexion etendues

Country Status (4)

Country Link
US (1) US7427532B2 (fr)
EP (1) EP1597756A2 (fr)
CN (1) CN100468670C (fr)
WO (1) WO2004077547A2 (fr)

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WO2004077548A2 (fr) * 2003-02-28 2004-09-10 Siemens Aktiengesellschaft Technique des connexions destinee a des semi-conducteurs de puissance et utilisant une matiere electriquement isolante qui suit les contours de surface
DE10308928B4 (de) * 2003-02-28 2009-06-18 Siemens Ag Verfahren zum Herstellen freitragender Kontaktierungsstrukturen eines ungehäusten Bauelements
DE102004057494A1 (de) * 2004-11-29 2006-06-08 Siemens Ag Metallisierte Folie zur flächigen Kontaktierung
DE102004057497B4 (de) * 2004-11-29 2012-01-12 Siemens Ag Wärmeaustauschvorrichtung und Verfahren zum Herstellen der Wärmeaustauschvorrichtung sowie Anordnung eines Bauelements und der Wärmeaustauschvorrichtung und Verfahren zum Herstellen der Anordnung
US7727813B2 (en) 2007-11-26 2010-06-01 Infineon Technologies Ag Method for making a device including placing a semiconductor chip on a substrate
US7982292B2 (en) * 2008-08-25 2011-07-19 Infineon Technologies Ag Semiconductor device
DE102009036418B4 (de) * 2009-08-06 2011-06-22 Siemens Aktiengesellschaft, 80333 Wellenleiter, insbesondere beim Dielektrikum-Wand-Beschleuniger
DE102018214778A1 (de) * 2018-08-30 2020-03-05 Siemens Aktiengesellschaft Verfahren zur Fertigung von Leiterbahnen und Elektronikmodul
CN115241148A (zh) * 2022-07-29 2022-10-25 志豪微电子(惠州)有限公司 智能功率模块及封装工艺

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Also Published As

Publication number Publication date
WO2004077547A2 (fr) 2004-09-10
US7427532B2 (en) 2008-09-23
CN100468670C (zh) 2009-03-11
WO2004077547A3 (fr) 2005-05-19
CN1799134A (zh) 2006-07-05
US20060252253A1 (en) 2006-11-09

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