Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/30—Monitoring
  • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
  • G06F11/3466—Performance evaluation by tracing or monitoring
  • G06F11/348—Circuit details, i.e. tracer hardware
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing

Definitions

• the present invention relates to microprocessor testing. It relates more particularly to a method and a device for transmitting digital data between a test circuit integrated in a microprocessor chip and an analysis tool.
• FIG. 1 schematically represents an integrated circuit 10 comprising a microprocessor ( ⁇ P) 12, an internal memory (MEM) 14 and input / output terminals (I / O) 16.
• the microprocessor 12 is intended to execute a program or software stored in memory 14. Under the control of the program, the microprocessor 12 can process data supplied by the input / output terminals 16 or stored in memory 14 and supply data by the input / output terminals 16
• a monitoring circuit 18 (TEST) is generally integrated into the integrated circuit 10.
• the monitoring circuit 18 is suitable for reading specific data supplied by the microprocessor .12 during the course of a program, and possibly performing processing on the data read.
• Monitoring terminals 22 connect the monitoring circuit 18 to an analysis tool 24.
• the analysis tool 24 can perform processing of the signals received, for example as a function of commands supplied by a user, and provide a detailed analysis of the operation of the microprocessor 12. In particular, the analysis tool 24 can determine the sequence of program instructions actually executed by the microprocessor 12.
• the number of monitoring terminals 22 for a conventional monitoring circuit 18 can be of the same order of magnitude as the number of input / output terminals 16 of the microprocessor 12, for example from 200 to 400.
• the monitoring terminals 22 as well as the connections of the monitoring circuit 18 occupy a large surface area of silicon, which leads to an undesirable increase in the cost of the circuit.
• a first version of the integrated circuit 10 including the monitoring circuit 18 and the monitoring terminals 22 is produced in small quantities to carry out the development of the microprocessor 12. After this development, a version of the integrated circuit 10 cleared of the monitoring circuit 18 and of the monitoring terminals 22 is marketed. This involves the production of two versions of the integrated circuit, which is labor intensive and relatively expensive. In addition, the final chip is not identical to the chip tested.
• monitoring circuit 18 which occupies a reduced surface area and requires only a reduced number of monitoring terminals 22, which reduces the cost of the monitoring circuit 18.
• the monitoring circuit 18 can then be left on the integrated circuit 10 finally marketed.
• the standard IEEE-ISTO-5001 in preparation offers in its version of 1999, accessible for example on the site www.ieee-isto.org/Nexus5001, a particular protocol for the exchange of messages between a monitoring circuit 18 and a analysis tool 24 for a monitoring circuit 18 requiring only a reduced number of monitoring terminals 22.
• a message indicates the occurrence of a jump during the course of the program executed by the microprocessor 12.
• a jump corresponds on the passage from an initial instruction which has just been executed by the program to a destination instruction other than the instruction which follows the initial instruction in the sequence of instructions forming the program.
• the analysis tool 24 seeks to reconstruct the sequence of instructions executed by the microprocessor 12. The reconstructed sequence of instructions can then be compared to a sequence of instructions theoretically executed by the microprocessor 12 so as to determine errors during the operation of the microprocessor 12.
• FIG. 2 represents a general example of a digital message transmitted by the monitoring circuit 18 according to the IEEE-ISTO-5001 standard.
• the message includes a series of fields each corresponding to a fixed or variable number of bits.
• the least significant bits of the message are located on the left of the figure, and the most significant bits on the right of the figure.
• a first Tcode field represents an identifier of the message. For each identifier given, the number of fields making up the message is fixed.
• the IEEE-ISTO-5001 standard provides two possible identifiers for jump messages. A first identifier corresponds to a so-called "explicit" jump.
• An explicit jump results from a direct jump instruction executed by the microprocessor 12 which results in a jump to a program instruction whose address, or data representative of the address, is explicitly indicated in the jump instruction.
• a second identifier corresponds to the other types of jumps, called "implicit jumps", which can occur during the execution of a program by the microprocessor 12.
• the jump message comprises a second SRC field comprising a number of bits variable according to the use of the monitoring circuit 18.
• the SRC field is used when the monitoring circuit 18 simultaneously exchanges data with several microprocessors or when the monitoring circuit 18 exchanges data with the same microprocessor 12 which simultaneously executes several programs.
• the SRC field may include no bits.
• the jump message comprises a third ICT field comprising a variable number of bits and corresponding to the number of instructions executed by the microprocessor 12 since the last instruction executed for which the monitoring circuit 18 transmitted a message explicit or implicit jump.
• the jump message includes a fourth ADDR field comprising a variable number of bits and representing the address of the jump destination instruction.
• the value of the ADDR field corresponds, for example, to the difference between the address of the destination instruction and the address of the last instruction executed by the microprocessor 12.
• An indirect jump instruction is a jump instruction which does not include data representative of the address of the destination instruction of the jump but a reference to a register in which said representative data is stored.
• An implicit jump can also correspond to a jump imposed by the very structure of the microprocessor 12.
• a jump is then performed although the last instruction of the program executed by the microprocessor 12 is not an indirect jump instruction.
• An interruption corresponds, when certain conditions for triggering an interruption are fulfilled, to a forced stop of the execution of the program, to the execution of an interrupt routine then to the possible resumption of the execution of the program.
• An interrupt jump therefore takes place from a program instruction to the first instruction of the interrupt routine.
• An example of the condition for triggering an interruption is the reception by the microprocessor of a signal indicating that the level of charge of batteries supplying the microprocessor 12 is below a determined threshold.
• a circuit jump corresponds to a jump imposed by the very structure of the microprocessor 12 when certain conditions are fulfilled from an initial instruction of the program to a destination instruction also belonging to the program. Circuit hopping is frequently used to effect the repetition of a small number of instructions a certain number of times by the microprocessor 12.
• the instruction of the sequence of instructions reconstituted by the analysis tool 24 corresponding to the message received by the analysis tool 24 is not an indirect jump instruction, there is no it is not possible with certainty to determine whether the implicit jump message received actually corresponds to a jump imposed by the microprocessor or if the received message corresponds to an indirect jump and that the sequence of instructions reconstructed by the analysis tool 24 is incorrect, for example offset from the sequence of instructions actually executed by the microprocessor 12.
• the present invention provides a method of transmitting digital messages making it possible to limit certain ambiguities during the reconstruction by the analysis tool of the sequence of instructions executed by the microprocessor regardless of the type of jump performed by the microprocessor.
• the present invention further provides a method of transmitting digital messages which does little to modify the jump messages provided for by the IEEE-ISTO-5001 standard.
• the present invention provides a method of transmitting digital messages, during the execution of a sequence of instructions by the microprocessor, by output terminals of a monitoring circuit integrated into the microprocessor, at least one of said digital messages being representative of characteristic data stored by the monitoring circuit upon detection of a jump in the execution of the sequence d instructions from an initial instruction to a destination instruction different from the instruction following the initial instruction in the sequence of instructions, the method comprising the steps consisting, for the transmission of a digital message, of determining whether the jump is associated with a jump instruction of the sequence of instructions for which data representative of the address of the jump destination instruction is explicitly indicated in the instruction; if so, assigning a first value to a first set of bits of the digital message, and if not, assigning a second value to the first set of bits; if the first set of bits is at the second value, assigning to a second set of bits of the digital message a third value identifying the jump among several types of hops; and transmit the digital message.
• the method further comprises the step consisting in assigning to a third set of bits of the digital message a value corresponding to the number of instructions executed by the microprocessor since the last instruction executed in the sequence of instructions corresponding to a digital message associated with a jump.
• the method further comprises the step consisting, if the first set of bits is at the second value, in assigning to a fourth set of bits of the digital message a value representative of the address of the destination instruction.
• a type of jump corresponds to a jump resulting from a jump instruction of the sequence of instructions containing the reference of a register in which is stored data representative of the address of the destination instruction.
• a type of jump corresponds to a jump forced by the microprocessor, the destination instruction corresponding to an instruction from a series of specific instructions not belonging to the sequence of instructions.
• a type of jump corresponds to a jump forced by the microprocessor, the destination instruction being an instruction of the sequence of instructions.
• the present invention also provides a device for transmitting digital messages between a monitoring circuit integrated into a microprocessor and an analysis tool via output terminals comprising means for detecting a jump during the execution of 'a sequence of instructions by the microprocessor; means for memorizing data characteristic of the detected jump; means for determining a digital message from the stored characteristic data, the digital message comprising a first set of bits fixed at a first value if the jump is associated with a jump instruction of the sequence of instructions for which a datum representative of the address of the jump destination instruction is explicitly indicated in the instruction, and set to a second value otherwise; and means for transmitting the determined digital message, in which, when the first set of bits is set to the second value, the determining means is adapted to include a second set of bits in the digital message set to a third value identifying the jump among several types of jumps.
• FIG. 1 previously described, very schematically represents the architecture of a chip integrating a microprocessor and a monitoring circuit
• FIG. 2 represents an example of a conventional implicit jump message sent by a monitoring circuit
• FIG. 3 represents an example of an implicit jump message sent by a monitoring circuit according to the invention.
• the present invention plans to keep the explicit jump message already provided for by the IEEE-ISTO-5001 standard.
• the present invention provides to add to the implicit jump message provided by the IEEE-ISTO-5001 standard an additional field specifying the nature of the implicit jump in order to modify the IEEE-ISTO-5001 standard as little as possible.
• FIG. 3 represents an example of an implicit jump message according to the invention.
• the message includes on the side of the least significant bits the Tcode field which, as has been previously explained, has a specific value for an implicit jump.
• the implicit jump message includes a second SRC field which, as explained above, has a variable number of bits and indicates whether the monitoring circuit
• the implicit jump message according to the invention comprises a third BType field having a variable number of bits and indicating the different possible implicit jumps.
• the BType field can comprise two bits, which makes it possible to code a first value corresponding to a jump resulting from an indirect jump instruction, a second value corresponding to a jump resulting from an interruption and a third value corresponding to a circuit break.
• the number of bits depends on the number of types of implicit jumps that one wishes to be able to distinguish by the analysis tool 24.
• the implicit jump message also includes a third ICNT field.
• the ICNT field comprises a variable number of bits and is equal to the number of instructions which separates the instruction executed by the microprocessor 12 to which a jump was made from the last instruction executed by the program which gave rise to the transmission of d a jump message by the monitoring circuit 18.
• the implicit jump message finally comprises a fourth field ADDR corresponding to a datum representative of the address of the instruction for the destination of the jump.
• the ADDR field generally designates an instruction of a routine stored in the memory 14 which does not belong to the program executed by the microprocessor 12.
• the analysis tool 24 can differentiate the different types of implicit jumps in order to remove any ambiguities during the reconstruction of the sequence of instructions executed by the microprocessor 12.
• the present invention has the advantage of modifying as little as possible the implicit jump message provided for by the IEEE-ISTO-5001 standard. Indeed, it provides for the addition of a single field of variable length in the message initially provided for by the IEEE-ISTO-5001 standard, the other fields remaining unchanged.

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• General Engineering & Computer Science (AREA)
• Quality & Reliability (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Debugging And Monitoring (AREA)
• Test And Diagnosis Of Digital Computers (AREA)

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• 2002
  • 2002-11-14 WO PCT/FR2002/003908 patent/WO2004046929A1/fr not_active Ceased
  • 2002-11-14 EP EP02788057A patent/EP1599801A1/de not_active Withdrawn
  • 2002-11-14 JP JP2004552769A patent/JP2006506720A/ja active Pending
  • 2002-11-14 US US10/535,065 patent/US20060155971A1/en not_active Abandoned

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