EP1602017A2 - Procede d'exploitation d'un microprocesseur et systeme de microprocesseur - Google Patents

Procede d'exploitation d'un microprocesseur et systeme de microprocesseur

Info

Publication number
EP1602017A2
EP1602017A2 EP04709578A EP04709578A EP1602017A2 EP 1602017 A2 EP1602017 A2 EP 1602017A2 EP 04709578 A EP04709578 A EP 04709578A EP 04709578 A EP04709578 A EP 04709578A EP 1602017 A2 EP1602017 A2 EP 1602017A2
Authority
EP
European Patent Office
Prior art keywords
program
jump
command
microprocessor
random bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04709578A
Other languages
German (de)
English (en)
Inventor
Berndt Gammel
Steffen Sonnekalb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=32920746&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP1602017(A2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1602017A2 publication Critical patent/EP1602017A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack

Definitions

  • the present invention relates to a method for operating a microprocessor and a microprocessor arrangement according to the independent claims 1 and 9.
  • DPA Differential Power Analysis
  • Programs always have several program or code sequences that are independent of one another and whose order in processing is interchangeable.
  • the program flow was previously used to protect against the above types of attacks randomly changed by software. For example, command sequences were interchanged by permutation, redundant command sequences were inserted or several different code sequences that lead to the same result were introduced.
  • this requires the use of a random generator that generates undeterminable random bits that are software-evaluated at corresponding branch points within the program, for example in order to branch to the corresponding code sequence in the case of a jump instruction.
  • Another method of protection against this type of attack is a randomly controlled program delay, in which dummy code sequences, the execution time of which is determined with the aid of a random generator, are inserted into the current program code.
  • a method known from published WO / 9963419 describes the control of a "wait-state connection" of a circuit by a random generator, the operation of the circuit being stopped or restarted as a function of the number generated by the random generator, and thus uniform processing cycles be prevented.
  • the object of the invention is to provide a method for operating a microprocessor or a microprocessor arrangement with which adequate security is ensured with minimal program expenditure.
  • This object is achieved by a method or a microprocessor arrangement in which at least one program Branch and / or program delay is provided, which is random bit-controlled for the modulation of a program run and implemented as a hardware-based command.
  • the modulation of a program sequence is controlled in an advantageous manner in that, for example, a bit randomly generated by a pseudo-random generator with a non-determinable bit of a real one generated physical
  • Random generator is linked to a random bit, which is used by the hardware-based instructions of the microprocessor in order to randomly execute program branches and / or program delays.
  • Instructions are advantageously introduced which have a variable execution time by randomly changing the runtime of the instructions via the parameters assigned to the instructions, which, for example, indicate operating cycles. Commands can also be inserted into the program flow which carry out an empty operation and have no influence on the result of a code sequence.
  • Randomly controlled program branches are advantageously implemented by jump commands with at least one jump target.
  • the jump is carried out or not depending on the value of a random bit.
  • the sequence of the code sequences to be processed can be varied in a random bit-controlled manner.
  • the destination addresses do not necessarily have to be processed if they achieve the same result. If these code sequences have, for example, different runtime profiles, the time behavior for achieving a result when the program is run again cannot be determined, so that the attack methods described above do not produce any usable information.
  • a jump instruction (“jumble") is implemented, the jump instruction specifying a jump destination:
  • the jump is carried out or not. If, for example, the random bit is set, ie has the value "1”, the jump operation to address "address1" is carried out, where code sequence 2 is processed and then the common code sequence "common code sequence” is processed under address “address2" becomes. Code sequence 1 can include a dummy operation here that has no influence on the result. In the event that the random bit is not set, ie has the value "0”, the jump to address "adressl” is not carried out, but the program flow is linear with the code sequence "code sequence 1" and subsequent jump to address "address2" continued. In the next exemplary embodiment, a jump instruction (“jumble") is implemented, the jump instruction branching into three jump destinations:
  • the sequence of processing the code sequences "code sequence 1, code sequence 2 and code sequence 3" at the addresses “addrl, addr2 and addr3" of the jump destinations can be interchanged, since they are not functionally dependent on one another.
  • the code sequences equivalent to the result to be achieved do not necessarily all have to be processed, so that an address can be jumped to under random bit control, under which the corresponding code sequence is processed and the program sequence is then continued under the address "address4".
  • the fact that the code sequences have different runtime behavior and that each time the program is run again jumps to a different address it is not possible to analyze the data obtained by interception processes.
  • the random bit-controlled sequence when all code sequences have to be processed also does not provide any usable data.
  • the following exemplary embodiment shows a jump command with two possible jump targets, which is implemented as a "jumblecall" call command and implements a context change by a jump: Jumblecall ⁇ addl>, ⁇ addr2>
  • the command can be executed either to one or to both jump destinations.
  • a "return" command is executed which restores the previous context.
  • the random bit-controlled parameters ⁇ n> and ⁇ m> specify the upper and lower limits of possible operation cycles, so that a variable run length of the command is achieved. In order to achieve a variable execution time of a command, whereby the parameters can be assigned to any command, only one parameter could also be specified as an upper limit. If the parameters have the value "0”, the command is executed in an optimal period. If the parameters have a value other than "0", up to ⁇ n> or ⁇ m> cycles are required to execute this command.
  • the command "jumpleadd" of the following exemplary embodiment can also be used for all commands:
  • This command also extends the execution time randomly.
  • the parameters determining the runtime of a command do not necessarily have to be specified for each individual command. These parameters can be stored in a configuration register, which is accessed, for example, using a configuration command "jumple_config ⁇ opl> ⁇ op2>.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne un procédé permettant d'exploiter un microprocesseur, selon lequel il est prévu au moins un branchement de programme et/ou une temporisation de programme, qui, pour assurer la modulation du déroulement d'un programme, sont régulés par bits aléatoires et sont mis en oeuvre et sauvegardés sous forme de commande matérielle. Ledit procédé se caractérise en ce qu'à chaque passage d'un programme défini, il y ait une durée d'exécution du programme, différente, dans chaque cas, de celle de passages de programmes antérieurs. L'invention concerne en outre un système de microprocesseur permettant de mettre ledit procédé en oeuvre.
EP04709578A 2003-03-12 2004-02-10 Procede d'exploitation d'un microprocesseur et systeme de microprocesseur Withdrawn EP1602017A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10310781A DE10310781A1 (de) 2003-03-12 2003-03-12 Verfahren zum Betreiben eines Mikroprozessors und eine Mikroprozessoranordnung
DE10310781 2003-03-12
PCT/DE2004/000241 WO2004081971A2 (fr) 2003-03-12 2004-02-10 Procede d'exploitation d'un microprocesseur et systeme de microprocesseur

Publications (1)

Publication Number Publication Date
EP1602017A2 true EP1602017A2 (fr) 2005-12-07

Family

ID=32920746

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04709578A Withdrawn EP1602017A2 (fr) 2003-03-12 2004-02-10 Procede d'exploitation d'un microprocesseur et systeme de microprocesseur

Country Status (4)

Country Link
US (1) US20060101513A1 (fr)
EP (1) EP1602017A2 (fr)
DE (1) DE10310781A1 (fr)
WO (1) WO2004081971A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006038879A1 (de) 2006-08-18 2008-02-21 Giesecke & Devrient Gmbh Verfahren und Vorrichtung zur nebenläufigen Ausführung von Prozessen
EP2234031A1 (fr) * 2009-03-24 2010-09-29 SafeNet, Inc. Obscurcissement
GB2494731B (en) 2011-09-06 2013-11-20 Nds Ltd Preventing data extraction by sidechannel attack
US10432511B2 (en) 2015-03-12 2019-10-01 Nec Corporation Method for forwarding data in a network, forwarding element for forwarding data, and a network for forwarding data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999063696A1 (fr) * 1998-06-03 1999-12-09 Cryptography Research, Inc. Utilisation d'informations non previsibles pour reduire au maximum les fuites provenant des cartes a puces et autres systemes cryptographiques

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Publication number Priority date Publication date Assignee Title
DE4408507A1 (de) * 1994-03-14 1995-09-28 Heidelberg Instruments Mikrotechnik Gmbh Lithografisches Verfahren
IL110181A (en) * 1994-06-30 1998-02-08 Softchip Israel Ltd Install microprocessor and peripherals
US5732138A (en) * 1996-01-29 1998-03-24 Silicon Graphics, Inc. Method for seeding a pseudo-random number generator with a cryptographic hash of a digitization of a chaotic system
US6009543A (en) * 1996-03-01 1999-12-28 Massachusetts Institute Of Technology Secure software system and related techniques
FR2745924B1 (fr) * 1996-03-07 1998-12-11 Bull Cp8 Circuit integre perfectionne et procede d'utilisation d'un tel circuit integre
CA2258338C (fr) * 1999-01-11 2009-02-24 Certicom Corp. Methode et dispositif pour minimiser l'effet d'agressions de puissance differentielles contre des processeurs
US6349393B1 (en) * 1999-01-29 2002-02-19 International Business Machines Corporation Method and apparatus for training an automated software test
FR2818772A1 (fr) * 2000-12-21 2002-06-28 Bull Cp8 Procede de securisation d'un operateur logique ou mathematique implante dans un module electronique a microprocesseur, ainsi que le module electronique et le systeme embarque associes
JP2003018143A (ja) * 2001-06-28 2003-01-17 Mitsubishi Electric Corp 情報処理装置
US6764808B2 (en) * 2002-02-27 2004-07-20 Advanced Micro Devices, Inc. Self-aligned pattern formation using wavelenghts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999063696A1 (fr) * 1998-06-03 1999-12-09 Cryptography Research, Inc. Utilisation d'informations non previsibles pour reduire au maximum les fuites provenant des cartes a puces et autres systemes cryptographiques

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J IRWIN ET AL: "Instruction stream mutation for non-deterministic processors", APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2002. PROC EEDINGS. THE IEEE INTERNATIONAL CONFERENCE ON 17-19 JULY 2002, 1 December 2001 (2001-12-01), XP055263776, ISBN: 978-0-7695-1712-4, Retrieved from the Internet <URL:http://www.cs.bris.ac.uk/Publications/Papers/1000604.pdf> [retrieved on 20160408] *

Also Published As

Publication number Publication date
US20060101513A1 (en) 2006-05-11
WO2004081971A2 (fr) 2004-09-23
DE10310781A1 (de) 2004-09-30
WO2004081971A3 (fr) 2005-03-31

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