EP1651969A2 - Methode et appareil pour lisser une consommation de courant dans un circuit integre - Google Patents

Methode et appareil pour lisser une consommation de courant dans un circuit integre

Info

Publication number
EP1651969A2
EP1651969A2 EP04778231A EP04778231A EP1651969A2 EP 1651969 A2 EP1651969 A2 EP 1651969A2 EP 04778231 A EP04778231 A EP 04778231A EP 04778231 A EP04778231 A EP 04778231A EP 1651969 A2 EP1651969 A2 EP 1651969A2
Authority
EP
European Patent Office
Prior art keywords
time period
processing time
output
during
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04778231A
Other languages
German (de)
English (en)
Other versions
EP1651969A4 (fr
Inventor
Alain Vergnes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0308735A external-priority patent/FR2857804B1/fr
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of EP1651969A2 publication Critical patent/EP1651969A2/fr
Publication of EP1651969A4 publication Critical patent/EP1651969A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack

Definitions

  • FIGURE 1 is schematic illustrating a prior art simplified microcontroller.
  • a microcontroller generally includes a microprocessor, memory, a peripheral module that provides communication, for example, Universal Asynchronous Receiver/Transmitter (UART), SPI, and USB, and an interrupt controller.
  • Microcontroller 100 includes microprocessor 102 coupled to memory 104.
  • Address decoder 106 receives and decodes addresses from microprocessor 102 for memory 104 and peripherals 108.
  • Address decoder 106 and peripherals 108 receive addresses on address bus 110 while address decoder 106 transmits select information on memory select 112 and peripheral select 114.
  • Data is transmitted between microprocessor 102, memory 104, and peripherals 108 on data bus 116.
  • a read or a write signal is transmitted between microprocessor 102 and memory 104 and peripherals 108 on read write signal 117.
  • Microcontroller 100 receives clock signal 118 and reset signal 120.
  • Input 122 includes, for example, timer triggers and UART input data while output 124 includes, for example, UART transmitter output data.
  • Interrupt controller 126 collects and processes interrupt signals from peripherals 108 along an interrupt line (not shown).
  • Peripherals 108 may be functional logic, for example UART, crypto-processing, digital signal processing (DSP), and digital filtering.
  • FIGURE 2 illustrates one example of a peripheral, a crypto-processor.
  • a crypto-processor if a buffer of data must be ciphered or deciphered, software divides the buffer into several parts. Each part represents data able to be processed during a processing time period. As soon as the part is input to the crypto-processor and/or a start signal is applied, the peripheral begins to process the part. After a period of clock cycles the processing period ends and the crypto-processor provides a ciphered/deciphered part that can be read back by the software.
  • the non-processing time period begins and an interrupt signal may be asserted to inform the microprocessor that the part is ready for reading and crypto-processor is ready to cipher/decipher a new part.
  • an interrupt signal may be asserted to inform the microprocessor that the part is ready for reading and crypto-processor is ready to cipher/decipher a new part.
  • the current increases due to operation of the combinatorial (for example AND, OR, INVERT, MUX, and XOR) and sequential (D flip flops, or DFFs) cells in the digital module that execute the algorithm.
  • DFFs sequential (D flip flops, or DFFs) cells in the digital module that execute the algorithm.
  • DFFs sequential (D flip flops, or DFFs) cells in the digital module that execute the algorithm.
  • DFFs sequential (D flip flops, or DFFs) cells in the digital module that execute the algorithm.
  • DFFs sequential (D flip flops, or DFFs) cells in the digital module that execute the algorithm.
  • DFFs sequential (D flip flops, or DFFs) cells in the digital module that execute the algorithm.
  • This value is not significant compared to the current consumed when processing is active.
  • User interface module 200 processes system data, for example address, data, read/write, and select signals, in order to generate commands and data for algorithm module 202.
  • Counter 108 receives a start signal from user interface 200 and organizes the data path into algorithm module 202.
  • a crypto algorithm may be represented as a basic combinatorial function concatenated several times to obtain the result.
  • a basic combinatorial function is implemented once and connected to storing means (DFFs or others).
  • DFFs storing means
  • a multiplexer is required to select the input of the algorithm function (data input or intermediate result) depending on a counter module n value (n being the number of iteration to perform to obtain the result, 16 for example in the Data Encryption Standard (DES)).
  • DES Data Encryption Standard
  • TDES Triple Data Encryption Standard
  • Counter 204 receives a start signal on start line 206.
  • the start signal triggers a first- cycle signal from counter 204 to multiplexer 208 in algorithm module 202.
  • Multiplexer 208 receives first-cycle signal and selects input from in-data line 210.
  • Input data then goes to combinatorial circuit 212, which, in combination with a key and a cipher, manipulates the input data.
  • Combinatorial circuit 212 begins processing upon receipt of the first-cycle signal and the input data, thus beginning the processing period.
  • Combinatorial circuit 212 transmits the manipulated input data to multiplexer 213.
  • multiplexer 213 receives processing period signal from counter 204 and therefore selects data from combinatorial circuit 212.
  • Multiplexer 213 transmits the manipulated input data to DFF 214, which then sends the manipulated data to output 216, multiplexers 208 and 213. For subsequent iterations, no first-cycle signal is transmitted to multiplexer 208, so multiplexer 208 selects the manipulated input data from DFFs 214 and sends it to combinatorial circuit 214, which again manipulates the input data.
  • Counter 204 keeps track of each iteration and counts down until the last iteration. At the last iteration, counter 204 sends a last-cycle signal to combinatorial circuit 212, indicating the end of the processing time period. Processing period signal from counter 108 triggers multiplexer 213 to select input from DFF 214 rather than combinatorial circuit 212.
  • FIGURE 3 is a graph illustrating a timing diagram and a current waveform representing activation of combinatorial circuit 212 during the processing period. When a buffer of data is processed, current consumption can be seen as a series of pulses. The low level period of this waveform represents the current consumption of the clock tree and the clock pin of the DFFs of the peripheral module. The high level period represents combinational circuit 212 switching current.
  • FIGURE 3 illustrates clock signal 300 and input data 305.
  • Input data 305 is available on input data line 210 (FIGURE 2) and represents part of the divided buffer of input data.
  • Start signal 310 is transmitted along start line 206 and triggers the beginning of processing time period 315.
  • Counter 204 counts down, in this case from 15 to zero for DES, with interval value 320.
  • First-cycle signal 325 transmits from counter 204 in conjunction with the first count on interval counter 320.
  • Last-cycle signal 330 transmits from counter 204 in conjunction with the last count on interval counter 320, and signals the end of processing time period 315 and the beginning of non-processing time period 335.
  • Combinatorial circuit 212 is driven with input data during processing time period 315, drawing more current than during non-processing time period 335. If a clock period is used to schedule the different steps of data processing, processing time period 315 may be detected or observed by non-intrusive methods like current consumption shape analysis. Each time data is processed the current increases to an active range of current, and then decreases to an inactive range of current during non-processing time period 335.
  • the invention consists of filling the non-processing time period with a current value close to the value (and shape) of the current during the processing time period.
  • the invention may be used in any circuit where digital logic modules are embodied.
  • the invention takes place in the digital part of an integrated circuit.
  • combinatorial logic operates and causes an increase in power consumption.
  • the increase in current is primarily due to cell switching, considering only the digital logic.
  • the total cell leakage current is low compared to this switching current.
  • the system and method reshapes current consumption in order to make current analysis more difficult.
  • FIGURE 1 is a prior art schematic illustrating a simplified microcontroller.
  • FIGURE 2 is a prior art schematic illustrating one example of a peripheral.
  • FIGURE 3 is a prior art graph illustrating a timing diagram and a current waveform for a peripheral from FIGURE 2.
  • FIGURE 4 is a schematic illustrating one embodiment of the invention in a microcontroller.
  • FIGURE 5 is a schematic illustrating one embodiment of the invention from FIGURE 4.
  • FIGURE 6 is a schematic illustrating a more detailed embodiment of the invention from FIGURE 5.
  • FIGURE 7 is a graph illustrating a timing diagram and a current waveform for one embodiment of the invention.
  • FIGURE 8 is a flow diagram illustrating a method of smoothing current in a digital logic module.
  • FIGURE 9 is a flow diagram illustrating a method of smoothing current in a digital logic module.
  • FIGURE 4 is a schematic illustrating one embodiment of the invention in a digital logic module, or a peripheral of a microcontroller.
  • Processing circuit 400 receives input from user interface 402 along input line 404.
  • Smoothing circuit 406 receives a start signal along start line 408 from user interface 402.
  • Smoothing circuit 406 transmits a first-cycle signal to processing circuit 400, which begins a processing time period.
  • processing circuit 400 is manipulating the input in order to produce a desired output, for example an encrypted or decrypted version of the input. Due to the manipulation, for example logic cell switching, processing circuit 400 draws an active range of current during the processing time period.
  • smoothing circuit 406 transmits a last-cycle signal to processing circuit 400 and the manipulated input is ready at output port 410 as output.
  • the end of the processing time period is the beginning of the non-processing time period.
  • Smoothing circuit 406 engages processing circuit 400 during the non-processing time period in order that processing circuit 400 draws the same range of current during the non-processing time period as during the processing time period. In one embodiment, operation of processing circuit 400 during the non-processing time period does not alter the output available at output port 410.
  • FIGURE 5 is a schematic illustrating a more detailed embodiment of the invention from FIGURE 4.
  • FIGURE 5 includes user interface 402, smoothing circuit 406 and processing circuit 400.
  • processing circuit 400 includes combinatorial circuit 500 coupled to multiplexer 510.
  • Multiplexer 510 receives input from input line 404. If multiplexer 510 also receives a first-cycle signal from smoothing circuit 406, then multiplexer 510 selects the input from input line 404 and sends it to combinatorial circuit 500.
  • Combinatorial circuit 500 manipulates the input and delivers the manipulated input to DFFs 520.
  • combinatorial circuit 500 receives a first-cycle signal and a last-cycle signal. In another embodiment, combinatorial circuit 500 does not receive first- cycle signal and/or last-cycle signal. First-cycle signal and last-cycle signal control data flow during the processing time period and the non-processing time period. DFFs 520 send the manipulated input to storage circuit 530 and to multiplexer 510.
  • multiplexer 510 does not receive a first-cycle signal so it transmits the manipulated input from DFFs 520 to combinatorial circuit 500.
  • Smoothing circuit 406 keeps track of the number of iterations necessary for the input to pass through combinatorial circuit 500.
  • DFFs 520 transmit each cycle of manipulated input to storage circuit 530.
  • storage circuit 530 receives an intermediate result that is not the desired output.
  • smoothing circuit 406 transmits a store signal to storage circuit 530. After storage circuit 530 receives the store signal it stores the desired output and makes it available at output port 410 throughout the non-processing time period.
  • storage circuit 530 continues to make the previously desired output available at output port 410 until the next store signal.
  • combinatorial circuit 500 continues to manipulate input supplied from multiplexer 510, despite having produced the desired output.
  • the desired output is stored in storage circuit 530, made available to output port 410 and not affected by the continued manipulation of combinatorial circuit 500 during the non- processing time period.
  • smoothing circuit 406 receives a start signal and sends a first-cycle signal to multiplexer 510, which then selects the input available on input line 404. The remainder of the next processing time period proceeds as described above.
  • storage circuit 530 comprises multiplexer 540 and DFFs 550.
  • Multiplexer 540 receives manipulated input from DFFs 520 and input from DFFs 550 during the processing time period. Until multiplexer 540 receives a store signal from smoothing circuit 406, multiplexer 540 selects input from DFFs 550 to output to DFFs 550. DFFs 550 make the input from multiplexer 540 available to output port 410 and multiplexer 540. The same value cycles between multiplexer 540 and DFFs 550 until the store signal toggles multiplexer 540 to select the desired output, available at the end of the processing time period. In one embodiment, assertion of first-cycle signal is removed during the non- processing time period.
  • FIGURE 6 is a schematic illustrating a more detailed embodiment of the invention from FIGURE 5.
  • One embodiment of smoothing circuit 406 is counter 600.
  • Counter 600 is one example of a circuit configured to track processing and non-processing time periods.
  • Counter 600 receives a reset signal and resets its count, in one example the count is 16 for DES, so counter 600 counts down from 15 to zero.
  • Counter 600 has multiplexer 605 that receives the start signal, so upon receiving the reset and start signal, counter 600 transmits a first-cycle signal and resets DFFs 610 at a count of 15. DFFs 610 transmit the count to a subtractor, or a decrementor (not shown), which reduces the count by one and multiplexer 605 selects the decremented count and transmits it to DFFs 610. The count is decremented to zero, which triggers transmission of the last-cycle signal.
  • Start signal toggles multiplexer 620 to select the assert, in this example a high input value of "one".
  • Multiplexer 620 passes the high input value to DFF 625, which transmits it to AND gate 630 and multiplexer 635.
  • Multiplexer 635 has a default select of the input from DFF 625, so multiplexer 635 transmits the high value to multiplexer 620.
  • the start signal is no longer asserted, so multiplexer 620 defaults to the input from multiplexer 635.
  • the high value continues cycling during the processing time period. At the end of the processing time period, last-cycle signal toggles multiplexer 635, causing multiplexer 635 to select the deassert, or low input value of zero in this example.
  • FIGURE 7 is a graph illustrating a timing diagram and a current waveform for one embodiment of the invention.
  • FIGURE 7 The signals and current in FIGURE 7 are described with respect to the circuit illustrated in FIGURE 4.
  • Each of user interface 402, smoothing circuit 406 and processing circuit 400 receive clock signal 700.
  • Processing circuit 400 receives input data 710 from user interface 402, and first-cycle signal 720 from smoothing circuit 406.
  • Start signal (not shown) has already issued from user interface 402 and began processing time period 730, which in this example is 16 clock cycles.
  • Processing circuit 400 manipulates the input and draws current 740 during processing time period 730.
  • smoothing circuit 406 transmits last-cycle signal and the desired output is made available at output port 410.
  • processing circuit 400 continues to manipulate it and draw current 740 during non-processing time period 760.
  • FIGURE 8 is a flow diagram illustrating a method of smoothing current consumption in a digital logic module having a processing circuit coupled to an output port.
  • receive an input receives a start signal when the input is available.
  • receive a start signal when the input is available.
  • trigger the beginning of the processing time period receives a start signal when the input is available.
  • receive a start signal when the input is available.
  • trigger the beginning of the processing time period receives a start signal when the input is available.
  • block 810 trigger the beginning of the processing time period.
  • drive the processing circuit to manipulate the input during a processing time period.
  • block 820 track the processing time period with a counter.
  • block 825 derive an output from the input manipulated during the processing time period.
  • block 830 generate a last-cycle signal indicating the end of the processing time period.
  • block 835 combine the last-cycle signal and the start signal into a store signal.
  • receive the store signal at the end of the processing period receive the store signal at the end of the processing period.
  • block 850 make the output available to the output port.
  • block 855 transmit an interrupt signal when the output is available, wherein the interrupt signal coincides with the end of the processing time period and the beginning of a non-processing time period.
  • block 860 drive the processing circuit to manipulate the input during the non-processing time period.
  • FIGURE 9 is a method of smoothing current consumption in a digital logic module having a processing circuit configured to receive an input and manipulate the input during a processing time period to produce an output. Production of the output is followed by a non- processing time period, wherein the processing circuit is further configured to draw an active range of current during the processing time period, and an inactive range of current during a non-processing time period.
  • block 920 generate a last-cycle signal at the end of the processing time period.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un système permettant de lisser une consommation de courant dans un module logique numérique. Un circuit de traitement est conçu pour recevoir une entrée et pour manipuler cette entrée lors d'une période de traitement, pour produire une sortie. Une période de non traitement suit la production de la sortie. Le circuit de traitement est également configuré pour tirer une plage active de courant lors de la période de traitement et une plage inactive de courant lors de la période de non traitement. Le système comprend un circuit de lissage relié au circuit de traitement et configuré pour s'engager dans le circuit de traitement lors de la période de non traitement. Le circuit de lissage est également configuré pour que le circuit de traitement tire une plage active de courant lors de la période de non traitement.
EP04778231A 2003-07-17 2004-07-12 Methode et appareil pour lisser une consommation de courant dans un circuit integre Withdrawn EP1651969A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0308735A FR2857804B1 (fr) 2003-07-17 2003-07-17 Procede et appareil pour lisser la consommation de courant d ans un circuit integre
US10/883,203 US6954866B2 (en) 2003-07-17 2004-06-30 Method and apparatus for smoothing current consumption in an integrated circuit
PCT/US2004/022626 WO2005010939A2 (fr) 2003-07-17 2004-07-12 Methode et appareil pour lisser une consommation de courant dans un circuit integre

Publications (2)

Publication Number Publication Date
EP1651969A2 true EP1651969A2 (fr) 2006-05-03
EP1651969A4 EP1651969A4 (fr) 2007-03-07

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Application Number Title Priority Date Filing Date
EP04778231A Withdrawn EP1651969A4 (fr) 2003-07-17 2004-07-12 Methode et appareil pour lisser une consommation de courant dans un circuit integre

Country Status (2)

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EP (1) EP1651969A4 (fr)
WO (1) WO2005010939A2 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312017B (zh) 2007-05-22 2012-05-30 香港应用科技研究院有限公司 影像显示装置及影像显示方法
EP2000936A1 (fr) * 2007-05-29 2008-12-10 Gemplus Jeton électronique comprenant plusieurs microprocesseurs et procédé pour la gestion de l'exécution de commandes sur plusieurs microprocesseurs

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086467A (en) * 1989-05-30 1992-02-04 Motorola, Inc. Dummy traffic generation
DE19505097C1 (de) * 1995-02-15 1996-06-05 Siemens Ag Verschlüsselungsvorrichtung
FR2784763B1 (fr) * 1998-10-16 2001-10-19 Gemplus Card Int Composant electronique et procede pour masquer l'execution d'instructions ou la manipulation de donnees

Also Published As

Publication number Publication date
EP1651969A4 (fr) 2007-03-07
WO2005010939A2 (fr) 2005-02-03
WO2005010939A3 (fr) 2005-11-17

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