Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
  • H10W20/058—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by depositing on sacrificial masks, e.g. using lift-off
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors

Definitions

• the present invention relates to the field of interconnections in microelectronic circuits or devices. It relates to an improved interconnection structure, for example of the Damascene or / and low dielectric constant type, as well as various production methods. These structures make it possible to interconnect metal lines in microelectronic devices and apply in particular to interconnections using copper as conductive materials.
• microelectronic device is meant any type of electronic circuit such as a chip, an integrated circuit, an electromechanical microsystem, etc.
• dielectric materials are materials commonly called “lo -k materials” (in French “materials of low dielectric constant k”).
• a “low-k” material is defined as a material having a dielectric constant k of less than 4.2, a value corresponding to the dielectric constant of the Si0 2 deposited by a plasma process.
• a material called "high-k” in French “high k" is a material with a dielectric constant greater than 4.2.
• Materials such as Si0 2 , materials of the USG type (USG for “undoped silicon glass”, in French “silicon oxide undoped”), materials of the SOG silicate or SOG siloxane type (SOG for “spin on glass”) , in French “silicon oxide deposited by rotation”) were previously used to form the insulating layer in interconnection structures.
• materials of low dielectric constant k with a structure Si x OF y called materials FSG (for "Fluorinated silicon glass", in French “silicon oxide doped with fluorine") of dielectric constant between 3 and 3.5, and with hydrogen-type materials silsesquioxane (HSQ) or methylsilsesquioxane (MSQ) or phenylsilsesquioxane.
• FSG for "Fluorinated silicon glass", in French “silicon oxide doped with fluorine
• HQ silsesquioxane
• MSQ methylsilsesquioxane
• phenylsilsesquioxane phenylsilsesquioxane
• the insulating layer is made based r a low dielectric constant material or "low-k"
• the latter is generally deposited in layers separated by an etch stop layer JPAR example base of Si0 2 or Si 3 N.
• the use of the dielectric material of low dielectric constant therefore generally complicates the process for producing the insulating layer produced subsequently.
• the insulating layer was inorganic in nature, based on materials such as Si0 2 , the masking and etching steps posed no problem.
• the realization of interconnection structures comprising an insulating layer based on a material of low dielectric constant proves to be much more complex.
• the masking step requires the use of a masking layer which is more selective with respect to the "low-k" material than a single layer of photosensitive resin.
• the masking layer is therefore generally a hard mask layer, for example made of Si0 2 , or SiC, or Si 3 N 4 coupled to a layer of openwork photosensitive resin.
• This process uses pickling or cleaning solutions or a plasma 0 2 which tend to modify the chemical nature of the insulating layer, by consuming the carbon included in an organic and porous dielectric material forming the insulating layer. This has the consequence of weakening the structure of the insulating layer. However, it turns out that the lower the dielectric constant of dielectric materials of organic and porous nature (criterion that one is looking for), the more fragile the structure of the initial insulating layer. Furthermore, the pickling or cleaning solutions or the plasma 0 2 tend to penetrate inside the possible porosities of the dielectric material, thus considerably modifying the nature and can cause "poisoning" phenomena of layers deposited subsequently. .
• a method for carrying out the stripping processes of the masking layer while reducing the alteration of the "low-k” insulating layer is mentioned in document [1] referenced at the end of this description.
• this method only partially reduces the deterioration of the insulating layer.
• the creation of interconnection structures, in particular of the Damascene type includes a step of deposition, for example by CVD method (CVD for "chemical vapor deposition” or “chemical vapor deposition”). ) or electrolysis of a metallic material. The metallic material then tends to diffuse through the walls of the holes and thus penetrate into the insulating layer.
• a known method consists in producing a “diffusion barrier” layer based for example on TiN or TaN on the walls of the vertical orifices and trenches.
• This diffusion barrier layer is produced for example by chemical vapor deposition (CVD) method, or for example by vapor deposition of an atomic layer (ALCVD, "A1CVD” meaning "atomic layer chemical vapor deposition” according to English terminology - Saxon) thanks to the use of precursor gases.
• CVD chemical vapor deposition
• A1CVD atomic layer
• these Precursor gases also tend to diffuse in the porosities of the dielectric material with low dielectric constant.
• the subject of the present invention is a method for producing an interconnection structure comprising: a) making an insulating layer on a microelectronic device based on a first dielectric material of density di and dielectric constant ki, and at least one hole in this layer, b) making on the hole walls , selective with respect to the microelectronic device, of a support layer, c) the deposition, in the hole, of a conductive material.
• the support layer holds the metal connection element and allows interconnections with metal connection elements having a high aspect ratio to be formed. The latter is carried out in step b), so as to surround the lateral faces of the metallic element, without interfering with the electrical connection between this element and the microelectronic device.
• the support layer is preferably made of a material with a density d 3 greater than the density di of the material forming the insulating layer. It can be made from a material with a dielectric constant k 3 > 4.2, therefore from a “high-k” type material, so that it does not lower the conductivity of the interconnection structure. .
• the support layer can also be made from a refractory material, so as to withstand high temperatures during subsequent process steps. This support layer can for example be made based on a metal oxide or a ceramic material. It can also be produced on the basis of a dielectric material chosen from the following materials: Hf0 2 , Zr0 2 , Ti0 2 , Y 2 0 3 , Cr0 2 .
• step b) can comprise: - the deposition of the support layer on the walls and at the bottom of the hole, - the removal of the. support layer at the bottom of the hole.
• step b) can advantageously comprise the deposition of the support layer, on the hole walls and which is selective with respect to the microelectronic device.
• the present invention also provides a method for producing an interconnection structure comprising at least one insulating layer based on a dielectric material with a low dielectric constant which is easier to produce than those according to the prior art.
• the invention leads to obtaining better quality interconnection structures than with the methods according to the prior art, in particular by allowing the material to have a low constant. dielectric to remain intact after its formation.
• the method can also comprise: at least partial removal of the first dielectric material and its replacement by a second dielectric material of dielectric constant k 2 ⁇ ki.
• the metallic connection element is produced in or through an insulating layer based on a first dielectric material of dielectric constant ki, for example of the type whose integration is known and without, for example, its etching being complex.
• This first dielectric material can be of mineral nature such as Si0 2, for example deposited by plasma, easy to work.
• a second dielectric material of low dielectric constant k 2 , generally having better insulation properties than the first, but generally also more complex to work with.
• the creation of interconnection structures with a low dielectric constant is first simplified. The quality of these structures is then improved, in particular by strengthening the solidity of the insulating layer.
• the dielectric material of low constant k 2 constituting the final insulating layer, is added at the end of the production process; it has therefore been preserved from masking, etching and stripping steps which may alter it.
• the support layer keeps the metal connection element when the first dielectric material is removed and then to support metal connection elements having high aspect ratios.
• the support layer also makes it possible to protect the metallic connection element against a chemical attack such as for example an attack with hydrofluoric acid, during the removal of the first dielectric material.
• the support layer is preferably insensitive to the process for removing the first dielectric material, for example produced by etching or chemical attack with hydrofluoric acid.
• the first dielectric material can be of inorganic nature.
• It can also be mineral in nature and can comprise one of the following materials: Si0 2 , fluorinated silicon oxide (FSG), undoped silicon oxide (USG), a plasma-deposited silicon oxide, a doped silicon oxide phosphorus (PSG) or boron doped (BPSG).
• FSG fluorinated silicon oxide
• USG undoped silicon oxide
• PSG doped silicon oxide phosphorus
• BPSG boron doped
• ki can be greater than or equal to 3 or
• the first dielectric material can be chosen for its simplicity of integration, more than for its insulating properties.
• Materials of a mineral nature such as Si0 2 , which are relatively easy to work with, generally have a dielectric constant greater than or equal to 3.
• the second dielectric material may comprise a polymer or be based on a polymer such as a poly (silsesquioxane) such as hydrogen silsesquioxane (HSQ) or an aromatic polymer such as SiLK®, FLARE®, VELOX®. It can also be organic in nature or based on an organic polymer such as polyarylether (PAE), or benzocyclobutene (BCB).
• the second dielectric material may be of mineral nature, for example based on a material based on nanoporous silicon oxide or on a fluorinated silicon oxide. It can include porosities. Thus, it can for example be based on a nanoporous silicon oxide, or on a porous polymer.
• the dielectric constant k 2 can be chosen to be less than 4.2, or 3.5, or 3 in which case it is a “low-k” type material having good insulating properties. The dielectric constant k 2 may even reach a value less than 2 depending on its nature (organic or inorganic, porous or not, etc.) and the deposition process used.
• the metallic connection element can comprise a metal or metal alloy based on a material chosen from the following materials: copper, tungsten, aluminum, silver, nickel, gold, zinc.
• a metal or metal alloy based on a material chosen from the following materials: copper, tungsten, aluminum, silver, nickel, gold, zinc.
• the removal of the first dielectric material it can be carried out by chemical etching using a solution based on hydrofluoric acid (HF) of given attack speed and concentration. Depending on the duration of the etching, the first dielectric material may be partially or completely removed.
• the replacement of the first dielectric material by the second dielectric material can understand the deposition of the second dielectric material by chemical vapor deposition (CVD) method, by centrifugation coating or by plasma assisted chemical vapor deposition (PECVD or “plasma enhanced CVD” according to English terminology).
• CVD chemical vapor deposition
• PECVD plasma assisted chemical vapor deposition
• the present invention also relates to an interconnection structure comprising: - at least one insulating layer based on a dielectric material covering said microelectronic device, - at least one metallic connection element formed in this insulating layer and in contact with said microelectronic device r - and at least one support layer based on a dielectric material, for example with a dielectric constant k 3 greater than or equal to 4.2, at least partially coating the metallic connection element.
• the insulating layer can be based on a dielectric material with a low dielectric constant k 2 of less than 4.2.
• the support layer may comprise a ceramic material or a metal oxide, or also a material from the following materials: Hf0 2 Zr0 2 , Ti0 2 , Y 2 0 3 , Cr0 2 .
• said interconnection structure according to the invention can be included in an electromechanical micro-system (MEMS).
• MEMS electromechanical micro-system
• FIGS. 4A-4H represent different stages of an example of a method for producing an interconnection structure with a low dielectric constant according to the invention
• FIG. 5 represents a microelectronic system according to the invention.
• the different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
• an interconnection structure of the Damascene type As illustrated in FIG. 1A, starting from an interconnection structure comprising at least one insulating layer 10 based on a material dielectric 13 of dielectric constant ki, for example greater than 3, or 3.5, or 4.2 and a connection element 12 formed in, or through, this insulating layer 10, the dielectric material is at least partially removed 13 of the insulating layer 10. This elimination is done for example by chemical etching based on hydrofluoric acid HF, for example of mass concentration less than 50%, and for a duration of the order of for example 1 to 2 minutes.
• hydrofluoric acid HF for example of mass concentration less than 50%
• This operation can be carried out for example in a deoxygenated bath obtained by bubbling nitrogen in order to avoid corrosion of the metallic connection element 12.
• the material 13 removed is replaced by a second dielectric material 16 of dielectric constant k 2 less than or equal to ki, for example by PECVD deposition or by coating by centrifugation.
• This second material 16 is preferably of the “low k” type, the constant k 2 being for example less than 4.2 or 3.5 or 3.
• This second dielectric material 16 can be based on a polymer such as '' a polyarylether (PAE), or an aromatic polymer such as SiLK ®, or FLARE ®, or VELOX ®. It can be organic.
• the final structure therefore comprises at least one metallic connection element 12 integrated into an insulating layer 10 based on a dielectric material 16 with a low dielectric constant. It allows the connection of the metallic connection element 12 with at least one conductive area 18 of a microelectronic device 14.
• FIG. 2A represents a perforated insulating layer 10 comprising one or more holes 22, based on a dielectric material 13 of density di, resting on a support or microelectronic device 14 before formation of at least one contact element.
• the holes 22 reveal conductive areas 18 of the support or device 14.
• the material of the insulating layer 10 has meanwhile any dielectric constant ki, for example greater than 3 or 3.5 or 4.2.
• the support layer 20 of thickness for example between 3 and 10 nanometers and resting on the insulating layer 10 and on the walls of the holes 22, without the bottom of the latter being covered.
• the support layer 20 can be produced by a selective deposition with respect to the support or microelectronic device 14, so as to cover only the insulating layer 10 and the walls of the holes 22, without covering the bottom of the latter (FIG. 2B). This deposition can be carried out for example by means of a chemical vapor deposition method of an atomic layer (ALCVD) or (ALD).
• the support layer 20 can be made from a material having a density d 3 greater than the density di of the dielectric material 13 and preferably insensitive to chemical attack such as etching with hydrofluoric acid.
• the material forming the support layer 20 may be a ceramic material, preferably of high mechanical strength, or a refractory material, or a metal oxide, or a material chosen from the following materials: HfO 2 , Zr0 2 , Ti0 2 , CrO 2 , Y 2 0 3 , AIN, ln 2 0 3 , Sn0 2 , Ga 2 0 3 , CdTe, HgTe, which are generally little or not sensitive to etching. hydrofluoric acid.
• the deposit ALD of the material forming the support layer 20, for example based on HfO 2 can be integrated over the entire surface of the insulating layer 10. This deposit can be preceded by a step of cleaning the holes 22 r for example using a solution based on ozone, hydrofluoric acid and hydrochloric acid. Said solution can also prepare the deposition of the support layer 20. In fact, it allows the creation of nucleation sites comprising the -OH structure to facilitate adhesion of the support layer 20.
• the support layer 20 can be used to hold the metallic connection element formed in the holes 22 of the perforated insulating layer 10, during an operation such as than that mentioned above (in connection with FIGS. 1A and 1B), elimination of at least part of the dielectric material 13.
• connection element metallic 12 for example by physical vapor deposition (PVD) of a conductive material.
• PVD physical vapor deposition
• FIG. 2C a connection element 12 as illustrated in FIG. 2C, which can itself be followed by a step of at least partial elimination of the layer 10 and replacement with a dielectric material of constant k 2 as explained above.
• the support layer 20 can be produced by deposition on the insulating layer 10, on the walls of the holes 22 and at the bottom of the latter (FIG. 3). In this case, the portion of the support layer 10 covering the bottom of the holes 22 is then etched before the step (previously described in connection with FIG. 2C) of forming the connection element 12.
• a protective layer 102 is deposited, for example based on a material such as SiC, Si 3 N 4 on at least one conductive zone 101, for example made of copper, flush on the surface of a microelectronic device 100.
• the microelectronic device 100 may be all or part of a chip r of a substrate, of an integrated circuit, of a MEMS (micro-electro-mechanical system).
• the conductive area 101 may for example be a line or a metal pad, for example made of copper.
• the protective layer 102 serves as a rampart to preserve the conductive area 101, for example during etching steps carried out subsequently.
• the insulating layer 103 is produced by at least one deposit, by example by a chemical vapor deposition (CVD) method, of a dielectric material 104 of dielectric constant ki.
• the dielectric material 104 can be of mineral nature, it is for example a material called "high-k" (in French "material of high dielectric constant”). It can also have a dielectric constant ki greater than 3 or 3.5 or between 3 and 3.5 or 3 and 4.2.
• the dielectric material 104 may for example be Si0 2 , or an undoped silicon oxide (USG), or a fluorinated silicon oxide (FSG), or a plasma-deposited silicon oxide (FIG. 4A). Then (FIG. 4B), one or more holes 105 are made in the insulating layer 103 revealing the protective layer 102 and in alignment with the conductive zone 101.
• the holes 105 comprise at least one vertical orifice 106, for example of depth between 100 to 1000 nanometers, or 10 to. 100 micrometers, revealing the protective layer 102.
• a horizontal trench 107 can also be produced as an extension of the vertical orifice. It is generally wider than the vertical opening.
• Holes are thus produced each comprising a first part in the form of one or more trenches, which correspond to the future location of horizontal conductive lines, and a second part in the form of one or more vertical orifices, which correspond to the future location of vertical conductive lines.
• the holes are, for example, produced by a process which comprises the steps consisting in first carrying out a photolithography using a layer of photosensitive resin, for example based on polyimide which is exposed, then which is develops to form a layer of openwork photosensitive resin. An anisotropic etching of the insulating layer is then carried out through the openwork photosensitive resin layer.
• the photosensitive resin layer is removed by the stripping or "pickling" process using, for example, a 0 2 / H 2 plasma.
• we can perform on the insulating layer by chemical layer deposition method atomic vapor phase (ALCVD) or (ALD), the deposition of a layer called “support layer” 108, for example between 3 and 10 nanometers thick, as already described above in connection with FIG. 2B.
• the support layer 108 can be used in particular to maintain a metallic connection element subsequently formed in the holes 105.
• the ALD deposition of the material forming the support layer 108 is preferably consistent throughout the surface of the insulating layer 103.
• the support layer can be produced selectively with respect to the protective layer 102 exposed by the vertical opening 106.
• the support layer can be formed 108, for example by selective deposition with respect to the protective layer 120 so as to cover the insulating layer 103 without covering the bottom of the holes 105 (FIG. 4C).
• the support layer is preferably made with a uniform thickness.
• the protective layer 102 is etched selectively, by a conventional method, at the bottom of the holes 105 (FIG. 3D), without reaching the support layer 108.
• a metallic material is deposited or electrolysed 109 based for example on copper, or tungsten, or aluminum, or silver, or nickel, or zinc, or gold, etc. to fill the holes 105.
• the deposition can be carried out by a method such as physical vapor deposition (PVD).
• PVD physical vapor deposition
• the support layer 108 covering the walls holes 105 can also serve as a metal diffusion barrier. It then protects the insulating layer 103 from the diffusion of the metallic material 109 during and after the electrolysis or the deposition of the metallic material.
• the deposition or electrolysis of metallic material 109 generally extends beyond the surface of the holes and completely covers the support layer 108 resting on the insulating layer 104 (FIG. 4E).
• a step of polishing the deposit of metallic material 109 and at least partially of the support layer 108 is then carried out until reaching the height of the mouth of the holes.
• the polishing can be carried out for example by chemical mechanical polishing method (CMP).
• CMP chemical mechanical polishing method
• the vertical opening of the filled holes forms at least one vertical conductive line 111. If there is also a horizontal trench, it forms, once filled, at least one horizontal conductive line 112.
• the set of conductive lines forms an element metal connection 110 which is interconnected with, for example, the conductive area 101 of the microelectronic device ( Figure 4F).
• This metallic connection element can have a high aspect ratio.
• An interconnection structure comprising at least one insulating layer 103 based on a dielectric material 104 of dielectric constant ki and at least one metallic connection element 110 has thus been produced.
• the dielectric material 104 of dielectric constant ki such as Si0 2
• HF hydrofluoric acid
• This operation can be carried out for example in an oxygen-free bath obtained by bubbling nitrogen in order to avoid corrosion of the metallic connection element.
• the metallic connection element is further protected from attack by the HF by the support layer 108, preferably little or not sensitive to this attack.
• the second dielectric material 113 is deposited for example by chemical vapor deposition method assisted by plasma (PECVD), or by coating by centrifugation. It is for example of the “low-k” or “low dielectric constant” type so that k 2 is for example less than 4.2 or 3.5 or 3.
• the second dielectric material can be based on a polymer such as a polyarylether (PAE), or an aromatic polymer such as SiLK®, or FLARE®, or VELOX®. It can be organic. It can be based on benzocyclobutene (PCB), based on polytetrafluoroethylene (PTFE) r based on a xerogel comprising a molecule of general formula R '- [Si (OMe) 3] n.
• the second dielectric material 113 of dielectric constant k 2 can also be for example of mineral nature such as a fluorinated silicon oxide. It can also include porosities 114 such as for example a nanoporous silicon oxide.
• the second dielectric material 113 can be deposited by coating by centrifugation.
• an interconnection structure has been formed comprising or comprising at least one insulating layer 103 based on a dielectric material 113 of low dielectric constant k 2 , at least one metallic connection element 110 formed in this insulating layer 103, and , optionally, at least one support layer 108.
• FIG. 5 represents a system comprising a first microelectronic device 100 and a second microelectronic device 200 connected to each other via an interconnection structure 300 according to the invention and comprising at least one insulating layer 103 based on a dielectric material 113 of low dielectric constant k 2 for example less than 4.2, at least one metallic connection element 110 formed in this insulating layer 103, and at least one support layer 108 coating the metallic connection element.
• the device 100 can be a chip or an integrated circuit or an electromechanical microsystem, or any type of electronic circuit. The same applies to the 200- Documents cited:

Landscapes

• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=34203545

Family Applications (1)

Country Status (4)

Families Citing this family (7)

Family Cites Families (7)

• 2003
  • 2003-09-16 FR FR0350547A patent/FR2859822B1/fr not_active Expired - Fee Related
• 2004
  • 2004-09-15 WO PCT/FR2004/050435 patent/WO2005029577A1/fr not_active Ceased
  • 2004-09-15 EP EP04816197A patent/EP1665370A1/de not_active Withdrawn
  • 2004-09-15 US US10/571,936 patent/US7947594B2/en not_active Expired - Fee Related

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events