EP1696390A2 - Procédé et dispositif de controller l'impression d'une imprimante à transfert thermique - Google Patents

Procédé et dispositif de controller l'impression d'une imprimante à transfert thermique Download PDF

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Publication number
EP1696390A2
EP1696390A2 EP06001375A EP06001375A EP1696390A2 EP 1696390 A2 EP1696390 A2 EP 1696390A2 EP 06001375 A EP06001375 A EP 06001375A EP 06001375 A EP06001375 A EP 06001375A EP 1696390 A2 EP1696390 A2 EP 1696390A2
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EP
European Patent Office
Prior art keywords
data
value
pixel
printing
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP06001375A
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German (de)
English (en)
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EP1696390A3 (fr
EP1696390B1 (fr
Inventor
Joachim Jauert
Dirk Rosenau
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Francotyp Postalia GmbH
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Francotyp Postalia GmbH
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Publication of EP1696390A2 publication Critical patent/EP1696390A2/fr
Publication of EP1696390A3 publication Critical patent/EP1696390A3/fr
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Publication of EP1696390B1 publication Critical patent/EP1696390B1/fr
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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00459—Details relating to mailpieces in a franking system
    • G07B17/00508—Printing or attaching on mailpieces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/35—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head
    • B41J2/355—Control circuits for heating-element selection
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00459—Details relating to mailpieces in a franking system
    • G07B17/00508—Printing or attaching on mailpieces
    • G07B2017/00516—Details of printing apparatus
    • G07B2017/00524—Printheads
    • G07B2017/0054—Thermal printhead
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
    • G07B17/00—Franking apparatus
    • G07B17/00459—Details relating to mailpieces in a franking system
    • G07B17/00508—Printing or attaching on mailpieces
    • G07B2017/00516—Details of printing apparatus
    • G07B2017/00556—Ensuring quality of print

Definitions

  • the invention relates to a method and an arrangement for controlling the printing of a thermal transfer printing apparatus, according to the preambles of claims 1 and 8.
  • the invention is used in devices with relative movement between a thermal transfer print head and the print material, especially in franking machines, addressing machines and other mail processing equipment.
  • a postage meter with a thermal transfer printing device has already been proposed, which allows a slight change of the print image information.
  • semipermanent and variable print image information are electronically stored as print data in a memory and read out into the thermal transfer printing apparatus for printing.
  • the print image includes a message and postal information including postage data for conveying the mail piece, for example, a postage stamp image, a postmark image with the post office delivery date and date, and an advertising stamp image.
  • the entire print image is microprocessor-controlled print image column wise imprinted by a single thermal transfer print head.
  • a printing of printing columns in an orthogonal arrangement to the transport direction takes place on a moving mailpiece.
  • the machine can thereby achieve a maximum throughput of mail of 2200 letters / hour at a print resolution of 203 dpi.
  • the franking machine T1000 has only a microprocessor for controlling a 30 mm wide thermal transfer print head with 240 heating elements for column-wise printing. All heating elements lie in a row, which is arranged orthogonal to the transport direction.
  • Thermal transfer printers use for printing a uniformly wide thermal transfer ribbon, which is arranged between a surface to be printed - for example, a mail piece - and the series of heating elements. The energy of an electrical pulse is converted at the resistance of the driven heating element into heat energy, which transfers to the thermal transfer ribbon.
  • Printing requires melting of a colored layer piece from the thermal transfer ribbon and application of the colored layer piece to the print material surface.
  • the printing takes place only when the impinged with the pulse heating element was brought to the pressure temperature, ie a higher than the preheating temperature.
  • a line is printed parallel to the movement or transport direction.
  • a bar is printed orthogonal to the direction of transport in a printing nip when electrical impulses are applied simultaneously to all heating elements in the row of heating elements for a predetermined limited period of time (pulse duration).
  • the pulse duration is subdividable into phases. Within the predetermined limited time duration (pulse duration), there exists a final phase (printing phase) in which the dots of a printing nip are printed.
  • the last phase is preceded by further phases of control of the heating elements in order to heat the latter to the pressure temperature.
  • the binary pixel data for Control of the heating elements of all printing columns are stored volatile in a pixel memory. At a low print resolution, the spacing of adjacent print columns is large and the binary pixel data of the print phase reflects the print image.
  • a long single pulse can be divided into several pulses whose pulse duration is the same and correspond to a specific heating phase. Usually several pulses are required to generate enough heat energy for melting a color layer piece under the heating element, which is printed on the surface of the mail piece as a dot (DE 38 33 746 A1).
  • a virtual column is to be understood here as a possibility of a further column in the printed image, which, however, is not visible since no dot is printed in the heating phase.
  • the binary pixel data for driving the heating elements when printing each printing column can be known to be encoded into image information and stored in the pixel memory in order to save storage space.
  • EP 578 042 B1 US 5,608,636
  • a method for controlling the column-wise printing of a postage indicia is known in which encoded image information is converted into binary signals for driving printing elements prior to the respective printing process, wherein the converted variable and unchangeable image data only during of printing. In this case, the decoding of the variable print data and providing the print data for a complete column in a register by a microprocessor.
  • the microprocessor's processing time is required in accordance with the proportion of the variable print data, the amount of postage throughput and the print resolution. This increases the bus load and limits the ability to print a franking stamp image faster on a franking.
  • the microprocessor can be relieved of pressure control hardware.
  • US 5,651,103 there is known in real time an apparatus and method for column-wise printing an image in which variable and fixed image data elements are interconnected and stored in a buffer for use in printing a column.
  • the variable and fixed image data elements reside in non-volatile memory, with a portion of the fixed image data elements being compressed.
  • the print image data are separated by a Hardware for the printing of each printing column composed of variable and invariable image data only before their printing, ie the image data for an impression are not in binary form in a memory area, but in a with EP 578 042 B1 for the T1000 disclosed methods comparable coded form.
  • variable image data items in the nonvolatile memory are identified and data corresponding to the variable image data items is transferred to the hardware to download, connect and then print the variable and fixed image data items.
  • the hardware proposed for this purpose requires a variable address register for each variable image data element. The number of variable pixels is thus limited by the number of address registers.
  • Modern franking machines should enable a so-called security impression, ie an impression of a special one Marking in addition to the above message.
  • a message authentication code or a signature is generated from the aforementioned message, and then a character string or a barcode is formed as a marker. If a security print is printed with such a mark, this allows a verification of the authenticity of the security print, for example in the post office or at the private carrier (US 5,953,426, US 6,041,704).
  • EP 1 378 820 A2 (US 6,733,194 B2) an arrangement for controlling the printing in a mail processing device is known, which has a print data control for pixel data processing during printing with a printhead and is connected via a BUS with a pixel memory.
  • the circuit arrangement has a DMA controller, a printer controller and at least one pixel data processing unit with two latches for data string data transfer from the pixel memory, wherein two latches are alternately described with data and be read out.
  • the aforementioned circuit arrangement is not suitable for controlling the printing of a thermal transfer printing apparatus. In order to create a FRANKIT-compatible franking machine with thermal transfer printing, the pressure data control would have to be changed accordingly, by which the microprocessor should be relieved.
  • the object of the invention is to provide a method and an inexpensive arrangement for controlling the printing of a thermal transfer printing device on a moving printing material with a high throughput and with a high-resolution thermal transfer print head, wherein the responsible for the control of the thermal transfer printing device microprocessor should be relieved.
  • variable picture elements should be almost unlimited, so that the variable printed image portion can be extensive and flexible for different postal requirements. Nevertheless, the arrangement for controlling the printing of a thermal transfer printing device should require as little memory as possible.
  • the method of controlling the printing of a thermal transfer printing device assumes that for printing a single dot, the maximum printing pulse duration at constant printing pulse voltage is a specific parameter for a particular thermal transfer ribbon and thermal transfer printing head system.
  • the maximum pressure pulse duration can be specified by the manufacturer of the system or thermal transfer print head or determined empirically by the manufacturer of the thermal transfer printing device.
  • the method is based on the idea that the preheat temperature and pressure temperature are closer to each other at higher print speeds than at low print speeds. Thus, in addition to higher speed of data processing, special accuracy and fineness of controllability of the thermal transfer printing apparatus become necessary.
  • pixel energy values are converted by means of a print data controller into a number of binary pixel data of the same value corresponding to the pixel energy value, wherein each binary pixel data value, for example equal to one, proceeds in successive phases (heating phase and / or one printing phase) of a pressure pulse duration is outputted from each heating element of a thermal transfer printing head as a constituent of a single printing pulse giving a printed dot located in the printing column of the printed image.
  • the pressure pulse duration may begin at different times for those heating elements to which a different pixel energy value is assigned, but ends for all driven heating elements of the row of heating elements at the same time. Thus, there are no printed dots that are in virtual columns.
  • the pulse duration of the single pressure pulse is proportional to the aforementioned number of binary pixel data with the value equal to one. At pixel energy level zero, no pulse is generated and thus no dot is printed in the printing phase.
  • the maximum necessary pulse duration of the control of a heating element for printing a pixel (Pixel's) as a pressure point (dot) is thereby decomposed into a defined maximum number M equal phases. In this way, a subsequent phase length of said parameter is defined, which describes the duration of each phase and thus a delivered during the phase part of the amount of energy required for printing at a constant pulse height.
  • the amount of energy required by each individual heating element of a high-resolution thermal transfer printhead when printing a dot located in the printing nip is supplied by the printing data controller.
  • the amount of energy required is determined in a manner known per se prior to printing in dependence on whether this heating element or adjacent heating elements are actuated by it during the printing of these printing gaps or have been activated when printing a preceding printing gap.
  • the required amount of energy determines the necessary pulse duration of the control of a heating element for printing a pixel (pixel) as a pressure point (dot).
  • the respectively required pulse duration is likewise divided by the defined phase length (duration) in order to determine a corresponding number of phases. This transformation allows the encoding of pixel energy values without significant loss of information.
  • the code is a binary code, for example a 4-bit per pixel quad.
  • the amount of energy of all the heating elements can be changed to the same extent before printing, the change being dependent on parameters such as the print head resistance, the printing speed and the print head temperature.
  • the process of energy value calculation is time consuming and therefore can not be done during printing.
  • a microprocessor is programmed by software for energy value calculation and encoding as well as providing pixel energy data.
  • the results of the energy value calculation and encoding are cached in a pixel energy store without the need to generate pixel data for virtual columns. This memory content (pixel energy data) is then decoded by the print data control during of printing to drive the printhead to produce binary pixel data for the virtual columns and the actual printing column.
  • the pressure pulse duration corresponds to a pixel energy value A, which can be predetermined for each pixel by an associated code (quadruple) that the maximum pressure pulse duration in a predetermined maximum number M of phases of each same phase length (duration) can be divided in that a phase count B is preset to a value M-1 which corresponds to the predetermined maximum number M of phases reduced by a value 'one', that the phase count B is decremented stepwise by a value 'one' and during each phase the number of phases selectable by the phase count B, for printing dot's of a print column, successively select all pixel energy values A and compare them with the current phase count B, generating binary pixel data of value 'one' if the phase count B is smaller as the respectively selected pixel energy value is A.
  • the energy values are coded, for example in 4-bits per pixel (quadruple), and stored in the pixel energy store.
  • the codes of the pixel energy values (quadruples) are stored in the pixel energy store word by word for a predetermined number of print columns. Starting with the code (quadruple) belonging to the first pixel of a printing column, the following code (quadruple) belonging to the respectively adjacent pixel of the printing column are stored one after the other.
  • the microprocessor is not additionally burdened by the provision of coded pixel data for virtual columns in the heat-up phases and the storage space requirement in the pixel energy storage is much less dependent on the number of heat-up phases before the actual printing phase.
  • a print data controller with pixel energy data processing for a high-resolution thermal transfer printhead is proposed, wherein at least one pixel energy data processing unit is controlled by a special controller to word-code the pixel energy values from the pixel energy store to a buffer for each print column and to generate binary pixel data for virtual columns and / or or for print columns which are serially transmitted to the shift register of the thermal transfer printhead, the pixel energy data processing unit outputting pixel data for each heater in each phase and thus providing the thermal transfer printhead for printing dots in a print image column.
  • a first variant of the print data control for a thermal transfer printhead having only one serial input and a number of 360 heating elements in the row two latches are provided in the print data control, alternately one of each of the direct memory access (DMA) latches having a number of 90 x 16 bit data words are loaded while the other is read out to transfer, in each phase, the codes (quadruples) of pixel energy data to each successive heater element in the row of 360 heaters, to a phase data processing unit for pixel energy data.
  • the loading and reading of the latches which are preferably designed as dual-port RAMs, preferably takes place via separate ports of the latches.
  • an encoder signal e triggers the alternately load and read the print data control latches to generate the pixel data per column in the print data control.
  • the encoder delivers a signal e with a pulse rate corresponding to the transport speed of the franking material.
  • the codes (quadruples) of pixel energy data for a complete print column become the print data controller for DMA printing loaded and cached there.
  • the at least one printhead drive pixel energy data conditioning unit has an output connected to the serial data input of the thermal transfer printhead shift register.
  • the pixel energy data is stored in the pixel energy storage so that, in synchronism with the encoder clock, the direct memory access can perform a certain number of cycles to load the pixel energy data for the next print column into the corresponding buffer.
  • the codes (quadruples) of pixel energy data of the same print column are sequentially read from the other of the two buffers. For the successive phases, therefore, the same codes (quadruples) are read out on pixel energy data.
  • a column counter is incremented in the print data controller. When a preset value is reached, printing stops.
  • the code (quadruples) of pixel energy data read from one of the two latches reaches a first parallel data input (4-bit) of the at least one phase data processing unit for pixel energy data.
  • the pixel energy data read out from the respective other of the two latches reaches as a code (quadruple) a second parallel data input (4-bit) of the at least one phase data processing unit for pixel energy data.
  • the phase data conditioning unit has a multiplexer connected to both parallel data inputs, whose parallel data output (4-bit) is connected to a first parallel data input (4-bit) of an evaluator logic.
  • the multiplexer is controlled by a switching signal which is output from the printer controller.
  • a value B of a phase counter goes to a second parallel data input (4-bit) of the evaluator logic of the at least one phase data conditioning unit for pixel energy data.
  • the parallel data output (4-bit) of the multiplexer supplies the value A.
  • the output of the evaluator logic supplies in the value range 'zero' up to the value A equal to the maximum number M of equal phases only one level with the logical value '1' if the value A is greater than the value B.
  • the respective value at the output of the evaluator logic is transferred to the shift register of the thermal transfer print head. If the output of the evaluator logic supplies a logic value '0', no associated heating element is activated.
  • the thermal transfer print head has two serial data inputs for separate shift registers.
  • two pixel energy data processing units are provided for the printhead drive, each having two latches.
  • the 180 codes (quadruples) of pixel energy data of one half of the printing column are alternately loaded into the respective first buffer of the two pixel energy data processing units and read from the respective second buffer memories of the two pixel energy data processing units for the printhead drive.
  • the output signals (SERIAL_DATA_OUT1, SERIAL_DATA_OUT2) of both phase data processing units for pixel energy data are shifted for each phase in the two shift registers of the thermal transfer print head and taken over for driving the heating elements in the driver register.
  • phase counter is decremented. If one of the outputs is logic '1', the associated heating element is activated in the subsequent phase. If it is logically '0', it will not be driven. When printing a column can thus be generated a number of different lengths of pressure pulses for each heating element.
  • the codes can be calculated relatively easily by the microprocessor. They also require less storage space than storing the complete print data for each phase in the pixel memory.
  • pixel energy data can be stored as code (quadruples) in the pixel energy storage in an optimal order, which relieves the microprocessor in the printed image change.
  • Data transfer via DMA also relieves the load on the microprocessor.
  • the 4-bit coded energy values can be easily copied into common image formats and additionally allow a simple check.
  • the bus load of the microprocessor is reduced because only once print data per DMA print data are loaded into the buffers of the pressure data control. There is no correspondingly high time requirement for the transmission of such data for heating phases.
  • the microprocessor is relieved, since with parameter changes (eg the temperature) only one register value of the pressure data control has to be changed and not all code (quadruples) in the pixel energy storage.
  • the amount of energy supplied to a heating element is determined by the pressure pulse duration. At a constant voltage level of the pressure pulse, it is proportional to the product of the number of phases and the phase duration for which the heating element is driven.
  • the power supply of the printhead can thus be done by a low-cost standard power supply with a fixed output voltage of 24 V and must not be adjustable.
  • the heaters for printing dot's of a print column can be driven without interruption. As a result, a high printing speed can be achieved.
  • FIG. 1 shows a simplified block diagram of the franking machine horril® as state of the art for the printing data control of a franking machine suitable for FRANKIT.
  • At least one microprocessor 6 ', one pixel memory RAM 7', one non-volatile memory NVM 8 'and one read-only memory FLASH 9' are connected to a print data controller 4 'via an address, data and control unit via a BUS 5'.
  • a postal security module PSD
  • the print data control consists of a pixel data processing unit 41 ', 42' and a special controller.
  • the latter comprises a DMA controller 43 ', an address generator 44' and a printer controller 45 ', to which an encoder 3' is connected, which detects the Druckguttransportterrorism.
  • the DMA controller 43 allows access to the binary pixel data stored in the pixel memory 7' in order to provide the latter data-string-wise to the pixel data processing unit 41 ', 42'.
  • the address generator 44 generates addresses which are supplied to the pixel data preparation unit 41', 42 'for selecting the binary pixel data from a buffered data string and grouping in the required order.
  • the printer controller 45 drives the pixel data preparation unit 41', 42 'to supply the binary pixel data in groups to a drive unit 11', 12 'of the ink jet print head 1', 2 '.
  • the printer controller 45 outputs a shift clock signal to both the pixel data processing units 41', 42 'and the pen driver boards 11', 12 ', which drive the inkjet printheads 1', 2 '.
  • FIG. 2 is a block diagram for controlling the printing of a postage meter with a print data controller for a thermal transfer print head.
  • At least one microprocessor 6, a pixel energy storage RAM 7, a non-volatile memory NVM 8, a read-only memory FLASH 9 and a postal security module (PSD) 10 are connected to the print data controller 4 in terms of address, data and control via a BUS 5.
  • the thermal transfer printhead 1 is connected to the print data controller 4, which assumes 16 bits of parallel data from the bus 5 in the case of a direct memory access and outputs serial binary data pixel by pixel to the thermal transfer printhead 1 on the output side.
  • An encoder 3 is connected to the print data controller 4 to trigger the buffering of the pixel energy data and the printing of the dots of the print columns, each thermal transfer print head being operated at a shift clock frequency of about 2.5 MHz.
  • the approximately 30 mm wide thermal transfer print head 1 is high-resolution and has an internal control electronics and a number of 360 heating elements, which are arranged in a row.
  • a first part of 180 heating elements is driven in parallel by a first shift register 11 via a first latch unit 12 and first driver unit 13.
  • a second part of 180 heating elements is driven in parallel by a second shift register 21 via a second latch unit 22 and second drive unit 23.
  • the print data controller 4 therefore has separate outputs for a first and second pixel energy data processing unit 41 and 42 and the associated controllers 43, 44, and 45.
  • the associated controllers 43, 44, and 45 are connected to the pixel energy data conditioning units 41 and 42 via address and control lines A & S. It is provided that a printer controller 45 with a DMA controller 43, with the thermal transfer printhead 1 and with an address generator 44 and that the latter with the pixel energy data processing unit 41, 42 is connected in terms of control.
  • the printer controller 45 is connected directly to the microprocessor 6 via the BUS 5.
  • the DMA controller 43 is connected to the microprocessor 6 via a control line for DMA control signals DMA ACK , DMA REQ .
  • the printer controller 45 is also in control communication with a sensor / motor controller 46 and an interrupt controller 47.
  • the sensor / motor controller 46 are on the one hand a start sensor S1, a scooter sensor S2, a flap sensor S3, an end sensor S4 and a thermistor 19 and on the other hand, a motor 2a for driving a roller, not shown for winding the consumed thermal transfer ribbon, a motor 2b for driving a counter-pressure roller for Druckgutbe emphasis during printing and a motor 2c for actuating the pressure mechanism of the counter-pressure roller to press the latter by means of the printed matter to the thermal transfer printing head 1 connected.
  • the interrupt controller 47 is connected via a control line 49 for an interrupt signal I directly to the microprocessor 6.
  • FIG. 3 shows a detail of the block diagram according to FIG. 2, with a circuit arrangement for controlling a pixel energy data processing unit.
  • the microprocessor 6, the pixel energy storage 7, the non-volatile memory 8 and the read-only memory (FLASH) 9 are connected to the address, data and control via the bus 5.
  • the printer controller 45 is also connected to the microprocessor 6 via the BUS 5.
  • the sensor / motor controller 46 and interrupt controller 47, which are also connected to the printer controller 45, have not been shown in detail in FIG. 3 for the sake of simplicity, but only as dashed lines.
  • the encoder 3 is connected to the printer controller 45 for outputting an encoder signal e.
  • the pixel energy data processing units 41 and 42 have the same structure and each consist of two latches 411, 412 and 421, 422 and a phase data processing unit 413 and 423.
  • the switching signal SO and the control signal SX are generated by the printer controller 45 and are via control lines to the - not shown - phase data processing unit 413 and connected to the phase data processing unit 423 shown.
  • the switching signal SO is also supplied via the control line to the DMA controller 43.
  • the latter is also connected to the printer controller 45 via control lines for DMA control signals (DMA start and DMA busy), the DMA controller 43 being supplied with the DMA start signal from the printer controller 45 and the DMA controller 43 being the DMA outputs a value of zero to the printer controller 45 to signal that the direct memory access is taking place and the DMA cycles have ended.
  • the DMA controller 43 generates address write signals AW as well as select signals Select-2.1 and Select-2.2 for the shown latches 421 and 422 of the second pixel energy data processing unit 42 and Select-1.1 and Select-1.2 for the latches 411 and 412 of the first pixel energy data processing unit 41, not shown Storing or reading out all quadruples of a pressure column.
  • the microprocessor 6 has a 32-bit data bus, a 16-bit memory is used to reduce manufacturing costs.
  • An internal DMA controller of the microprocessor 6 also allows the addressing of 16-bit data words.
  • the latches 411, 412 and 421, 422 are connected to the data bus.
  • the buffering of a print column in the direct memory access (DMA) thus requires that a buffering of each 45 * 16-bit data words is performed in succession in two latches, the latches are selected by the selection signals.
  • DMA direct memory access
  • the DMA controller 43 has means for generating and outputting selection signals Sel_1.1, Sel_1.2 or Set_2.1, Sel_2.2 depending on from the switching state of the switching signal SO in order to temporarily store the quadruples in the respectively first or respectively second of the two latches 411, 421 or 412, 422.
  • selection signals Sel_1.1, Sel_1.2 or Set_2.1, Sel_2.2 depending on from the switching state of the switching signal SO in order to temporarily store the quadruples in the respectively first or respectively second of the two latches 411, 421 or 412, 422.
  • the respective other latches for buffering the quadruples of a subsequent pressure column are successively also selected by the selection signals.
  • a 6-bit address write signal AW is supplied for wordwise addressing. The latter is in each case at a separate address input of the first and second latches 421 and 422.
  • a first select signal Sel_2.1 for pixel energy data for the second print column half is provided and applied to a separate control input of the first pixel data latch 421 for the second printhead.
  • a second select signal Sel_2.2 for pixel energy data for the second print column half is provided and applied to a separate control input of the second pixel energy data latch 422 for the second print column half.
  • the printer controller 45 has evaluation means for evaluating the address and control signals transmitted via bus 5, which are evaluated with regard to the occurrence of a print command and communicates with the DMA controller 43 via at least one control line. Triggered by a print command, the printer controller 45 delivers a first control signal DMA-start to the DMA controller 43. Then, a request signal DMA REQ is generated by the DMA controller 43 and sent to the microprocessor 6.
  • the microprocessor has an internal DMA controller (not shown) which, in the case of a direct memory access, applies a specific address to the pixel energy storage (RAM) 7, thereby enabling a word-by-word transfer of quads of the pixel energy data via bus 5 to the latches.
  • An address write signal AW is supplied to the latches by the DMA controller 43 for this purpose.
  • the Microprocessor 6 can read out, for example, a 16-bit-wide data word with pixel data via DMA from pixel energy storage RAM 7 and transmit it to the print data control unit.
  • the microprocessor 6 sends an acknowledgment signal DMA ACK to the DMA controller 43 to synchronize the generation of the address write signal AW in the DMA controller 43 with the DMA cycle of the microprocessor 6.
  • a 16-bit data word with 4 quadruplets of pixel energy data is put into a buffer.
  • Each of the four latches can provide a total of 180 x 4 bits for further data conditioning after every 45 DMA cycles.
  • a shift clock signal SCL of the printer controller 45 is connected to the thermal transfer printhead 1 and the address generator 44 via a control line.
  • the address generator 44 has means for generating and outputting address read signals AR.
  • the printer controller 45 outputs an address generator start signal AG-start to the address generator 44, which is supplied with the shift clock signal SCL of the printer controller 45 to generate read addresses AR, which allows reading the quadruples from those buffers into which no Quadruples are loaded and cached.
  • the address generator 44 may be supplied with a control signal other than the shift clock signal SCL of the printer controller 45 to generate read addresses AR.
  • A A 4 ⁇ 2 3 + A 3 ⁇ 2 2 + A 2 ⁇ 2 1 + A 1 ⁇ 2 0
  • B B 4 ⁇ 2 3 + B 3 ⁇ 2 2 + B 2 ⁇ 2 1 + B 1 ⁇ 2 0 ,
  • the latch control signal of the printer controller 45 is connected to a count input of the phase counter 48.
  • B binary coded value
  • B3 binary coded value
  • B1 binary coded value
  • FIG. 4 shows a detail of the circuit arrangement according to FIG. 3, with a circuit arrangement of the pixel energy data processing unit.
  • the first and second buffer memories 421 and 422 for pixel energy data for the second printing column half are, for example realized as dual port RAM's 4210 and 4220. The latter are selected for reading in the pixel energy data by the first or second selection signal Sel_2.1 or Sel_2.2 supplied by the DMA controller at a separate control input of the respectively first ports 4211 and 4221 of the first and second dual port RAMs 4210 or 4220 is present.
  • a first and a second selection signal Sel_2.1 or Sel_2.2 are alternately supplied by the DMA controller 43 for word-wise storage of pixel energy data for the second half of the printing column.
  • first pixel energy data processing unit 41 also includes a first and second latches 411 and 412, which are each connected on the input side to the low-order 16 bits of the data bus of the bus 5.
  • the address write signal AW supplied from the DMA controller 43 is also applied to each of a separate address input of the first and second buffer memories 411 and 412 for pixel energy data provided for the first print column half.
  • a first select signal Sel_1.1 for pixel energy data for the first print column half is provided and applied to a separate control input of the first pixel energy data latch 411 for the first print column half.
  • a second select signal Sel_1.2 for pixel energy data for the first print column half is provided for a subsequent print column and is applied to a separate control input of the second pixel energy data latch 412 which is the first print column half subsequent printing gaps are provided.
  • the previously read pixel energy data are then read out, for example, from the first and second dual port RAM 4210 and 4220, respectively.
  • an address read signal AR which is supplied by the address generator 44, is applied to the second port 4212 or 4222.
  • the first pixel energy data processing unit 41 of the first printing column half (not shown in detail in FIG. 2) has the same structure as the second pixel energy data processing unit 42 of the second printing column half shown in FIG.
  • the address read signal AR supplied from the address generator 44 is again applied to a separate address input of the first and second latches 421 and 422 of the second pixel energy data processing unit 42 for pixel energy data of the second print column half.
  • the parallel data outputs of the first and second pixel energy data latches 421 and 422 are applied to first and second inputs of a second phase data processing unit 423 for pixel energy data.
  • One half of the printed image is printed by half of the heating element row of the print head.
  • the internal printhead electronics for each half of the heating element series is also constructed in a similar way. Since the printer controller 45 has means for generating and outputting the switching signal SO, which drives the phase data processing unit 423, the pixel energy data can be selected from the output of the respective first or second of the two latches 421 and 422 for further data processing.
  • the phase data processing unit 423 has on the input side four switches 4231, 4232, 4233 and 4234 for the parallel data inputs and an evaluator logic 4235 with an output-side switch 4236.
  • the printer controller 45 controls via the switching signal SO, the four input-side switch 4231, 4232, 4233 and 4234 and the control signal SX the output side switch 4236th Die Switching by the switch 4231 takes place between the terminals H1 and K1 to an output P1.
  • the other switches 4232, 4233 and 4234 and 4236 are preferably constructed in the same way.
  • the switches can be realized for example by logic gates.
  • a 4-bit multiplexer Mux 2 is used for the input-side switch and controlled by the switching signal SO, which is output from the printer controller 45 and also applied to a control input of the DMA controller ( Figure 3).
  • the phase counter 48 is incremented by the LH edge of the latch signal and is preferably constructed as a down counter and preset to a count.
  • the binary output B supplying parallel output of the phase counter 48 and the binary value A supplying parallel output of the 4-bit multiplexer Mux 2 (or alternatively: the outputs of the input side switch or gate) are connected to two parallel data inputs of the evaluation logic 4235.
  • SX '0'.
  • the sequence control of the printer control will be explained in more detail below with reference to FIG.
  • the entire print data control can preferably be realized with an application specific circuit (ASIC) or programmable logic, such as Spartan II 2.5V FPGA from XILINX ( www.xilinx.com ).
  • Figure 5b shows a circuitry of evaluator logic 4235 constructed of NAND logic gates.
  • the gates G1 to G4 logically negate the binary coded values B4, B3, B2, B1, which is subsequently illustrated by the symbol N () or N [].
  • a value results at the output of the gates G9, G5, G11 and G17 '0'.
  • Ai ⁇ Bj results at the output of the gates G9, G5, G11 and G17 a value '1'.
  • the circuits for the evaluation of the values A3, B3 and A4, B4 each form an identically constructed stage, and the circuit arrangement of the evaluator logic 4235 is in principle expandable by such stages.
  • the gates G15 and G21 have the same dual function.
  • the gate formed by gate G21 is closed due to the value '0' output from the output of gate G20.
  • the function Y can in principle also be extended with further gates for a further digit of the binary coded number for pixel energy data.
  • the construction by means of NAND gates shown serves only as an embodiment and is not intended to preclude a structure with NOR or other logic gates.
  • FIG. 6 shows a flow chart for the flow control of the printer controller.
  • a step 102 is reached and in routine 100 of the sequence control all selection signals Sel_1.1, Sel_1.2, Sel_2.1, Set_2.2 are set to the value 'zero'.
  • a data word transmitted via the bus is evaluated with regard to the occurrence of a command for printing start. If the latter has not yet been issued, then it branches into a waiting loop.
  • the Start printing in a step 104 setting the column count V to the value 'zero'.
  • the switching signal SO is set to the value 'one' and output.
  • a second interrogation step 105 the encoder signal e is now evaluated with regard to the occurrence of an LH edge. If the latter has not yet occurred, a branch is made to a waiting loop.
  • a signal DMA start is output and a subroutine 300 is started, which sets certain selection signals Sel_1.1, Sel_1.2, Sel_2.1 or Sel_2.2 to the value 'one' to the binary pixel energy data from the RAM 7 in the latches of the pixel data processing units 41 and 42, which will be explained in more detail later with reference to FIG.
  • a control signal SX is output by the printer controller and a subroutine for generating and outputting 180 shift clocks SCL is started.
  • step 111 a DMA start signal is output and DMA control is enabled to restart the aforementioned subroutine 300 (FIG. 8).
  • step 112 a column pressure subroutine 500 is started (Fig. 7).
  • a sixth query step 115 it is evaluated whether the column count value V has reached a limit value U.
  • a predetermined limit value U is reached, the printing of the printed image, preferably a franking imprint, is ended. If this is not the case, then the fourth query step 109 is branched. Otherwise, the first interrogation step 103 is branched and the routine starts again as soon as a print start command is detected in the first interrogation step 103.
  • FIG. 7 shows a flow chart of the pressure column for a pressure column.
  • the latter is called as a column pressure subroutine 500 in the course of routine 100 of the scheduler to serially write all pixel data of a column into the shift registers of the thermal transfer printhead and generate latch pulses.
  • step 505 the printer controller 45 outputs the address generator start signal AG-start to start the subroutine 400.
  • the details of the address generation 9, a phase length counter or a subroutine 200 for phase length generation is then started in the next step 506.
  • the phase length counter is embodied, for example, as a presettable downwards counter
  • the details of the subroutine 200 for phase length generation are explained in more detail below with reference to FIG.
  • step 507 generation and output of 180 shift clock pulses SCL from the printer controller 45 are performed.
  • the shift clock SCL is generated to advance, via the serial data output D, all the pixel data for the row of heaters to the shift register.
  • phase_counter : Phase_counter - 1.
  • FIG. 8 shows a flow chart for DMA control.
  • a subroutine 300 is called when a DMA start signal is output from the printer controller 45 to the DMA controller 43 (step 301).
  • a word count W is set to the Value 'zero' set.
  • a DMA-busy signal is set to the value 'one' and transmitted to the printer controller 45.
  • a DMA request signal DMA REQ having a value 'zero' is transmitted to the microprocessor 6. The latter transmits an acknowledgment signal DMA ACK to the DMA controller 43.
  • a non-receipt of the acknowledgment signal DMA ACK branches to a waiting loop with a value 'zero'.
  • a value 'zero' is jumped to a second interrogation step 305, the state of the switching signal SO being determined. If the switching signal SO has the state equal to one, then a branch is made to a third interrogation step 306. Otherwise, the switching signal SO has the state equal to 'zero' and a branch is made to a fourth interrogation step 309.
  • step 306 it is checked whether the word counter has a value W less than forty-five. For this case (W ⁇ 45), a branch is made to a step 307.
  • step 307 the first selection signal Sel_1.1. for the first pixel energy data processing unit 41 of the first printing column half is switched to the value 'one' and the address writing signal AW receives the current value W of the word counter.
  • step 312 the pixel data are taken over into a buffer of the pixel energy data processing units 41, 42 selected in this way.
  • step 313 all selection signals are switched to the value 'zero' and a DMA request signal DMA REQ with a value 'one' is transmitted to the microprocessor 6.
  • step 314 the word count W is incremented with the value 'one'.
  • a subsequent query step 315 it is checked whether the word counter has a value W smaller than ninety. For this case, in which the word counter has a value W ⁇ 90, a branch back to a step 303. Otherwise, a branch is made to a step 316 to output a signal DMA busy having the value 'zero' before the end (step 317) of the subroutine 300 is reached.
  • step 306 if it is determined in the third interrogation step 306 that the word count value W is not less than forty-five, then a branch is made to a step 308, in which the first selection signal Sel_2.1. is changed to the value 'one' for the second pixel energy data processing unit 42 for the pixel energy data of the subsequent second printing column half, and the address write signal AW receives the current value W of the word counter which is reduced by the value 'forty five'. In the subsequent step 312, the pixel data are taken over again in the buffer selected in this way.
  • step 309 it is also checked whether the word counter has the value W ⁇ 45, namely, if it was previously determined in the interrogation step 305, the switching signal SO does not have the state equal to one. If the word counter has the value W ⁇ 45, then in step 310, the second selection signal Sel_1.2. for the first pixel energy data processing unit 41 for the pixel energy data of the first printing column half of a subsequent printing column is switched to the value of one 'and the address writing signal AW receives the current value W of the word counter. In the subsequent step 312, the pixel data are taken over again in the buffer selected in this way.
  • the fourth query step 309 branches to a step 311 in which the second selection signal Sel_2.2 for the second pixel energy data processing unit 42 of the pixel energy data of the subsequent second print column half of a subsequent print column the value 'one' is switched over and the address write signal AW receives the value W of the word counter which is reduced by the value 'forty-five'.
  • the pixel data are taken over again in the buffer selected in this way.
  • Figure 9 shows a flow chart for address generation.
  • the addresses of stored binary pixel data begin with the start address zero, which is the following for the address read signal AR is generated.
  • the output of the address read signal AR to the latches takes place for their addressing.
  • FIG. 10 shows a flow chart for phase length generation.
  • the printer controller 45 has, for example, a down-counter that can be preset to a value PL, which causes an equal time duration for each phase when printing dot's of a column.
  • the backward counter operates on subroutine 200 and is started in step 201.
  • the value PL of the phase length is provided by a register of the printer controller 45.
  • the register value is written by the microprocessor 6 and changed accordingly when parameter changes.
  • the printer controller 45 is preferably part of an FPGA which has an internal clock generator or uses an external clock signal which generates a high frequency signal FPGA_CLK, for example 20 MHz.
  • the invention is applicable to both a single thermal transfer printhead having two shift registers which provide pixel data for one-half of a row of heaters, as well as a plurality of such orthogonal-aligned thermal transfer printheads to the transport direction of the print material. This requires several pixel data conditioning units and the special controller 43, 44, 45 and 48.
  • the arrangement of pixel energy data in the pixel energy storage RAM 7 can advantageously be organized such that a change of picture elements is easily possible.
  • the print data control for pixel data processing during printing with a printhead thus also enables a higher flexibility with regard to the requirements of different national postal authorities to a printing mail processing device.

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EP06001375A 2005-02-15 2006-01-24 Procédé et dispositif de controller l'impression d'une imprimante à transfert thermique Expired - Lifetime EP1696390B1 (fr)

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DE102005007220A DE102005007220B4 (de) 2005-02-15 2005-02-15 Verfahren und Anordnung zum Steuern des Druckens eines Thermotransferdruckgeräts

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EP2370267B1 (fr) 2008-12-25 2014-03-26 Brother Kogyo Kabushiki Kaisha Imprimante sur bande
PL2370264T3 (pl) 2008-12-25 2015-01-30 Brother Ind Ltd Kaseta z taśmą oraz drukarka taśmowa
JP5136503B2 (ja) 2009-03-31 2013-02-06 ブラザー工業株式会社 テープカセット
PL2414165T3 (pl) * 2009-03-31 2014-08-29 Brother Ind Ltd Kaseta z taśmą oraz drukarka taśmowa
JP5282815B2 (ja) 2009-03-31 2013-09-04 ブラザー工業株式会社 テープカセット
CN101850662B (zh) 2009-03-31 2015-02-11 兄弟工业株式会社 带式打印装置
JP4947085B2 (ja) * 2009-03-31 2012-06-06 ブラザー工業株式会社 テープカセット
JP5445582B2 (ja) 2009-03-31 2014-03-19 ブラザー工業株式会社 テープカセット
CN101850674B (zh) 2009-03-31 2015-01-14 兄弟工业株式会社 带盒
US12296580B2 (en) 2009-03-31 2025-05-13 Brother Kogyo Kabushiki Kaisha Tape cassette
EP2261040B1 (fr) * 2009-06-10 2012-02-08 Brother Kogyo Kabushiki Kaisha Imprimante
US20100329767A1 (en) * 2009-06-30 2010-12-30 Brother Kogyo Kabushiki Kaisha Tape cassette
US8641304B2 (en) * 2009-06-30 2014-02-04 Brother Kogyo Kabushiki Kaisha Tape cassette
JP5326950B2 (ja) * 2009-09-09 2013-10-30 ブラザー工業株式会社 テープカセット
JP5212550B2 (ja) 2009-12-16 2013-06-19 ブラザー工業株式会社 テープカセット
EP2520437B1 (fr) 2009-12-28 2015-05-20 Brother Kogyo Kabushiki Kaisha Cassette à bande
JP5093265B2 (ja) * 2010-02-26 2012-12-12 ブラザー工業株式会社 テープカセット
US8384750B2 (en) * 2010-03-31 2013-02-26 Brother Kogyo Kabushiki Kaisha Printing apparatus
EP2371558B1 (fr) 2010-03-31 2015-04-15 Brother Kogyo Kabushiki Kaisha Imprimante thermique
DE202010015353U1 (de) * 2010-11-11 2011-02-10 Francotyp-Postalia Gmbh Ein- und ausschaltbare Versorgungseinheit
US10783103B1 (en) 2017-02-24 2020-09-22 Xilinx, Inc. Split control for direct memory access transfers

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DE3833746A1 (de) 1988-09-30 1990-04-05 Siemens Ag Thermodruckverfahren mit vorheizung
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DE102005007220B4 (de) 2007-08-16
US7965308B2 (en) 2011-06-21
DE102005007220A1 (de) 2006-08-17
EP1696390A3 (fr) 2006-09-06
EP1696390B1 (fr) 2008-09-03
DE502006001462D1 (de) 2008-10-16
US20060181718A1 (en) 2006-08-17

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