EP1714208A2 - Procedes et systemes d'affichage a consommation d'energie optimisee - Google Patents

Procedes et systemes d'affichage a consommation d'energie optimisee

Info

Publication number
EP1714208A2
EP1714208A2 EP05706372A EP05706372A EP1714208A2 EP 1714208 A2 EP1714208 A2 EP 1714208A2 EP 05706372 A EP05706372 A EP 05706372A EP 05706372 A EP05706372 A EP 05706372A EP 1714208 A2 EP1714208 A2 EP 1714208A2
Authority
EP
European Patent Office
Prior art keywords
display
display panel
memory
display system
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05706372A
Other languages
German (de)
English (en)
Inventor
Francky Catthoor
Andy Dewilde
Lieven Hollevoet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of EP1714208A2 publication Critical patent/EP1714208A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Definitions

  • the present invention relates to devices and methods for displaying information. More particularly, the present invention relates to methods for displaying information having limited power consumption and devices or systems thus obtained.
  • Typical examples of such displays are Light Emitting Diode Displays and Organic Light Emitting Diode (OLED) Displays.
  • An important factor in power consumption related to data transfer, corresponds with the number of memory accesses that are performed to put data on the screen.
  • To put an image on the display typically data is first written into a so-called video buffer or frame buffer.
  • the frame buffer is typically used as the data source for a display controller unit, which scans the frame buffer and generates the control signals for the display panel.
  • a display system 100 as shown schematically by way of example in Fig. 1a, is shown with a display unit 102 seen as a separate building block of a multimedia terminal. From the application point of view, the display unit 102 is considered to be a black box.
  • a typical application currently used for generating screen data writes its output from a processing means 104 in the frame buffer 106.
  • the output typically is first at least partly processed in a video memory 108.
  • the frame buffer 106 typically is located in a main memory of the platform or in a memory unit contained within a display unit 102, furthermore comprising a display controller 110, such as e.g. an LCD controller unit.
  • a display controller 110 such as e.g. an LCD controller unit.
  • the frame buffer 106 is integrated in the main platform and may be a part of the main memory. Refreshing the display panel 112, such as e.g.
  • the LCD panel requires transferring the data from the main memory frame buffer 106 through the memory bus 114 to the display controller 110. This is typically done using a dedicated Direct Memory Access (DMA) controller contained within the display controller 110. The complete content of the frame buffer 106 then is transferred to the display controller 110 at a speed that is determined by the refresh rate of the display panel 112, e.g. 60 Hz or 75 Hz. This traffic places a heavy burden on the memory bus, and hence, on the power consumption of the platform. An overview of the bus connection for such a system 100 is shown in Fig. 1b.
  • the advantage of using a processor- integrated display controller 110 is the reduction of the chip count of a system, an important factor in the design of portable devices.
  • Disadvantages are the load on the main memory bus 114 and the power consumption caused by the bus accesses.
  • this part of the system accounts for 28% of the total power.
  • the memory accesses cause a significant power consumption, both in the memory chips themselves or memory units on the processing/display chips as in the busses that have to be driven to transfer the data between the chips.
  • using a frame buffer allows designers to make abstraction of the display unit.
  • the display controller such as e.g. an LCD controller takes care of the hardware specific actions required to put an image on the screen. As long as energy or memory footprint are not an issue, this allows a simpler design procedure.
  • a specific processing means may be de-energised according to timing or according to kind of input data. More specifically, if e.g. simple displaying actions need to be performed, the frequency by which the specific processing means is activated can be significantly reduced, thus leading to a reduced power consumption. Adjusting the refreshment of image data in a system, possibly in relation to the content of the data to be displayed, also allows for reducing power consumption in a display system.
  • JP2000/356977 describes a method for reducing the load on a CPU by transferring only difference data between a previous frame and a present frame to a display driver.
  • a status RAM provides information about the contents between different frames. This info can be obtained at a writing time at which the CPU writes data to the video RAM.
  • the invention relates to a display system for displaying information, the system comprising a processing means and a display unit with a display panel, the display system having an image data processing path for transferring information to said display panel, wherein said image data processing path comprises maximally one writable memory component external to the display panel, said maximally one writable memory component adapted for storing or buffering at least a single image frame.
  • the display system may comprise one writable memory component.
  • the writable memory component may be a single port memory component.
  • the writable memory component may comprise different memory elements that can be contacted all through the same memory port.
  • the system furthermore may comprise a control means adapted to control access of said one writable memory component.
  • the control means may be implemented in hardware or in software.
  • the one writable memory external to the display panel e.g. the frame buffer memory, should preferably not be a dual-port memory component, i.e. for example it is not a dual-port frame. In other words reading information from the one writable memory external to the display panel by the display panel may be not possible simultaneously with writing information to the one writable memory external to the display panel by the processing means.
  • the control means may control the processing means and the display panel such that they never access the information at the same time, and that the production of new pixels from the processing means, i.e. the generation or transmission of the new image to the one writable memory external to the display panel, may be always postponed till the display has read the pixels of the current image from the one writable memory external to the display.
  • This one writable memory external to the display may be a single-buffered memory.
  • the memory may be capable of comprising only one image frame of the information to be displayed.
  • the writable memory component may be a frame buffer.
  • the frame buffer may be integrated in the display unit. Alternatively, the frame buffer may be positioned on a main platform of the display system, where the processing means is located.
  • the writable memory component may be a video RAM. This video RAM may be located on the main platform of the display system. It may be part of a larger memory.
  • the display system may comprise no writable memory component external to said display panel on said image data processing path.
  • the display panel may comprise a plurality of pixels, and the display system may comprise a writable memory component in the display panel, the writable memory component in the display panel comprising a memory cell for each pixel of said display panel.
  • the memory cells corresponding with the pixels of the display panel may be used as writable memory in the image data processing.
  • the display unit may comprise an active matrix display panel.
  • the display unit may comprise a fixed format display panel.
  • the display unit may comprise any display with an array of pixels whereby every pixel has a memory element associated with it, e.g. a capacitor.
  • the display unit may comprise a liquid-crystal-on-silicon based (LCOS) device.
  • the display unit may comprise any of an organic light emitting device or a light emitting diode device.
  • the display unit may comprise a thin film transistor based display panel. Access to the display unit, e.g. to the on-display memory component, may be organised via the memory map within the processing means.
  • the display system may be adapted to store digital or analog values for each pixel of the display panel.
  • the display system may comprise a conversion means for transforming digital outputs received in said processing means, to analog values suited for said display unit.
  • the display unit may be directly connected to said processing means. More particularly, the display panel may be directly connected to said processing means.
  • the direct connection may be made by a first bus.
  • the maximally one writable memory component external to the display panel may be connected to the processing means by a second bus.
  • the number of memory accesses, e.g. writes from the processing means may be minimized so that only the "new updates" are overwriting the "current image info" in the one writable memory component external to the display panel. So not only the display itself may be only "reading” the modified pixels from the buffer. Also the transfer from the processing means to the one writable memory component external to the display panel, e.g.
  • the frame buffer may be optimised by only transferring the modified pixel display data to the one writable memory external to the display panel, e.g. the frame buffer.
  • the first bus and the second bus may have no parts in common.
  • the invention furthermore relates to a display system for displaying information, the system comprising a processing means and a display unit, wherein said display unit is directly connected to said processing means.
  • the direct connection may be made by a first bus connection.
  • the first bus connection may be a dedicated display bus connection.
  • the display unit may comprise a display panel and the display system may comprise maximally one writable memory component external to said display panel and adapted for comprising at least a single image frame, said maximally one writable memory component external to said display panel being connected to said processing means through a second bus, said second bus having no common part with said first bus.
  • the display unit furthermore may be powered by a driver bus.
  • the display unit may comprise a fixed format display panel.
  • the display unit may comprise any of a liquid-crystal-on-silicon based display panel, an organic light emitting device display panel or a light emitting diode display panel.
  • the display panel may be a thin film transistor based display panel.
  • the display panel may comprise a plurality of pixels, wherein said display system may be adapted to store digital or analog values for each pixel of said display panel.
  • the display system furthermore may comprise a conversion means for transforming digital outputs of said computation means to analog values suited for said display unit. Access to said display panel may be organised via a memory map in the processing means.
  • the invention also relates to a method for displaying information, the method comprising receiving in a processing means information to be displayed, converting said information in an image to be displayed, displaying said image to be displayed, wherein converting said information in an image to be displayed comprises converting said information in an image to be displayed using maximally one writable memory component external to the display panel.
  • the method may be applied in any of the display systems, as described above.
  • Converting said information in an image to be displayed may comprise controlling the access to the maximally one writable memory component external to the display panel. Converting said information in an image to be displayed may comprise converting said information in memory information for the memory elements corresponding to pixels of the display panel.
  • the invention furthermore relates to a method for displaying information, the method converting information into framed image sequences, the method comprising computing an image whereby at least one pixel value for a new frame is determined and updating pixel display data only when said pixel display data are changed. Updating pixel display data only when said pixel display data are changed may comprise transferring only the updated pixel display data to pixels of a display panel.
  • the information may be video information.
  • the video information may be block oriented video information, each block comprising a header. Computing an image may comprise indicating in said block which pixel information has been changed.
  • Fig. 1a - prior art is a schematic overview of a conventional display system comprising a frame buffer and a video memory as known from the prior art.
  • Fig. 1 b - prior art shows the typical bus connection for a prior art display system as described in Fig. 1a, wherein the display unit is connected to a processing means using at least part of the memory bus used for connecting the frame buffer with said processing means.
  • Fig. 2 is a schematic representation of a display system having an image data processing path between a processing means and a display panel with maximally one writable memory, according to a first embodiment of the present invention.
  • Fig. 3 illustrates a memory map for allowing addressing of pixels of a display panel, according to embodiments one to four of the present invention.
  • Fig. 4a and Fig. 4b shows a display system, with alternative positions for the frame buffer, being the sole writable memory on the image data processing path, external to said display panel, according to a first embodiment of the present invention.
  • Fig. 4c and Fig. 4d illustrate different ways for connecting the different components of the display system as shown in Fig. 4a or Fig. 4b, either using part of a memory bus to connect the display unit (Fig. 4c), or using a separate display bus (Fig. 4d).
  • Fig. 5a shows a schematic illustration of a display system wherein the frame buffer is omitted and the video RAM is the sole writable memory on the image data processing path, external to said display panel, as an alternative system according to the first embodiment of the present invention.
  • Fig. 5b and Fig. 5c illustrate different ways for connecting the different components of the display system as shown in Fig. 5a, either using part of a memory bus to connect the display unit (Fig. 5b), or using a separate display bus (Fig. 5c).
  • Fig. 6a shows a schematic illustration of a display system wherein no writable memory components are present on the image data processing path, external to said display panel according to a second embodiment of the present invention.
  • Fig. 6b illustrates a way for connecting the different components of the display system as shown in Fig. 6a, wherein the display unit is directly connected to the processing means.
  • Fig. 7a shows a schematic illustration of a display system according to the display system of Fig. 6a, wherein the display unit allows for reading back.
  • Fig. 7b illustrates a way for connecting the different components of the display system as shown in Fig. 7a, wherein the display unit is directly connected to the processing means with a two way communication.
  • Fig. 8a shows a schematic representation of a display system, the display system comprising a display unit comprising only a display panel without display controller as an alternative example according to the second embodiment of the present invention.
  • Fig. 8b illustrates a way for connecting the different components of a display system as shown in Fig. 8a, wherein the display unit is directly connected to the processing means.
  • Fig. 9a shows a schematic representation of a display system according to Fig. 8a, wherein furthermore a separate bus driver is provided for compensating leakage of the memory elements of the display panel.
  • Fig. 8a shows a schematic representation of a display system according to Fig. 8a, wherein furthermore a separate bus driver is provided for compensating leakage of the memory elements of the display panel.
  • FIG. 9b illustrates a way for connecting the different components of a display system as shown in Fig. 9a, wherein the display unit is directly connected to the processing means.
  • Fig. 10 illustrates the different steps of a method for power optimised displaying according to a fifth embodiment of the first aspect of the present invention.
  • Fig. 11 - prior art illustrates a way for connecting different components of a display system as known from the prior art.
  • Fig. 12 illustrates a way for connecting different components of a display system wherein a specific bus is used for connecting the processing means with the display unit, according to a fifth embodiment of the present invention.
  • Fig. 13a and Fig. 13b are two examples of the way for connecting different components of a display system as shown in Fig. 12.
  • Fig. 14 is an illustration of the power gained by optimising compared to the original power consumption.
  • the same reference signs refer to the same or analogous elements.
  • a device comprising means A and B should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
  • the term “coupled”, also used in the claims, should not be interpreted as being restricted to direct connections only.
  • the scope of the expression “a device A coupled to a device B” should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.
  • a display system wherein the number of intermediate memories, between a processing means, such as a microprocessor, and the display panel, is limited.
  • a display system with low power consumption and a method of operating the same is provided.
  • Fig. 2 illustrates, by way of example, a display system 150, the display system 150 comprising a display unit 152 and a processing means 154.
  • the display unit 152 comprises at least a display panel 156.
  • the display unit 152 optionally may comprise a display controller 157, although the invention is not limited thereto.
  • information is generated or received to be displayed on the display panel 156.
  • the processing means 154 may be any suitable processing means such as e.g.
  • the present display system 150 provides maximally only one writable image memory 160 along said image data processing path 158 external to the display panel 156. In other words, either one writable image memory component 160 external to the display panel 156, or no writable image memory component 160 external to the display panel 156 is present.
  • the display panel 156 itself may act and actively be used as a memory.
  • the maximally one writable image memory component 160 may be any writable memory component that is adapted for comprising a single image frame. Typical examples of such writable memory components are random access memory (RAM) memory, such as e.g. dynamic RAM and static RAM, DRAM, SRAM, EDO RAM, EDRAM, etc., the invention not being limited thereto.
  • RAM random access memory
  • the reduction of intermediate memories allows to obtain an improved power consumption, i.e. the power consumption is reduced e.g.
  • a typical way of obtaining a reduction of intermediate memories between the processing means 154 and the display panel 156 is by treating the display panel 156 itself as a memory.
  • a memory element is associated with each pixel of a fixed format display and is used as a memory store. The latter allows for a reduction of intermediate memories, as the requirements for bringing the display output data in specific display format is overcome.
  • the display system 150 thus has a new hardware architecture comprising a display panel 156 which actually may be used as video memory.
  • the display panel 156, used as a video memory is based on integration techniques, wherein a memory is integrated at the pixel level.
  • a pixel-level memory is present for each pixel of the display panel 156.
  • Typical display panels 156 having such a memory element incorporated for each pixel are e.g. display panels 156 with active pixels, also referred to as active matrix display panels, as these comprise at the pixel level an electronic component including a memory element such as a storage capacitor local to each pixel, or display panels wherein for each pixel a memory element is specifically included.
  • Typical examples of such display panels 156 comprising an integrated pixel-level memory are thin film transistor display panels. Specific types of display panels that can be used are e.g. OLED display panels, LED display panels, LCD display panels, etc.
  • the display panel that can be used may e.g. be a reflective display such as e.g.
  • a system based on LCOS valves wherein the memory cell is hidden behind the pixel.
  • the status of pixels in the display panel 156 is then determined by the value that is written in the corresponding memory cell. Switching a pixel on or off occurs by writing a certain value to the corresponding memory location on the display panel.
  • a shadow memory element may be additionally provided, that allows storing information of a frame subsequent to the current frame that is displayed.
  • the display panels used preferably are fixed format display panels, such that the number of memory elements per display panel is known.
  • the processor memory then is equipped with a processors memory map comprising information about the display memory map addresses.
  • the memory map 170 provides for the main memory 172 the necessary information about the display memory addresses in the display memory 174 present in one of the peripherals 176, such as e.g. a display unit, a PDA, a mobile phone, etc.
  • the display panel thus acts as a large Random Access Memory (RAM) to the processor, thereby fully exploiting the fact that a memory cell is present for every pixel on the screen.
  • RAM Random Access Memory
  • This memory may be write only or may also be read/write if the necessary access coders are provided.
  • the display system thus preferably is adapted for processing the information to be displayed on the data processing path such that the information to be displayed is converted in memory information, suitable for the memory elements of the pixels of the display panel.
  • a dedicated display has been provided for the processor rather than providing an output of the processor which can be used with any display.
  • a display panel used as a memory both monochrome as well as colour images can be represented.
  • Introduction of colour can be provided by displaying combinations of values in different memory cells corresponding with different adjacent coloured pixels (e.g. a set of primary colour pixels such as three pixels for red, green, blue) thus regarding the group of coloured pixels, e.g.
  • the set of primary colour pixels such as three pixels for red, green, blue, as a superpixel.
  • Introduction of grey levels and/or colour levels can be provided by displaying combinations of values in different memory cells corresponding with adjacent pixels (e.g. a cell of n pixels) thus regarding the group of pixels, e.g. the cell of n pixels, a superpixel.
  • grey levels and/or colour levels can be displayed.
  • different embodiments will be described wherein the number of intermediate memories is reduced compared to prior art display systems. Referring to Fig.
  • a display system 200 is described, wherein one of the frame buffer or the video RAM on the main platform is not provided, such that there is only a single writable memory external to the display panel 156, between the processing means 154 and the display panel 156. Not providing, i.e. eliminating compared to prior art systems, the video
  • the display system 200, 220 comprises a display unit 152 with a display panel 156.
  • the display system 200, 220 furthermore comprises a processing means 154 on a main platform, e.g. a motherboard, and a frame buffer 202.
  • the display unit 152 furthermore may optionally comprise a display controller 157.
  • the frame buffer 202 may be located either in the display unit 152, as part of the display controller 157, as shown in Fig. 4a or it may be located on the main platform as shown in Fig. 4b.
  • the display controller 157 acts as a separate building block accessible to the processor 154.
  • the frame buffer is not provided and the video RAM 302 of the main platform is the maximally one writable memory on the image data processing path external to the display panel. The latter is shown for display system 300, shown in Fig. 5a. This allows for important power savings as the high throughput bus between the frame buffer and the display panel 156 is not required any more.
  • the one writable memory on the image data processing path may be adapted for comprising at least a single image frame.
  • the one writable memory component on the image data processing path may be a single port memory, meaning that it can only be contacted for reading or writing through a single port. It is to be noted that several memory elements contacted through the same, single port, may be considered as one writable memory component. It is an advantage that at least one intermediate memory is not provided anymore, as this may allow, e.g. if a frame buffer allocated in the main memory is not provided or if a video RAM allocated in the main memory is not provided, a reduction of the required main memory size of a platform. This enables designers to switch off memory banks that are not in use, which reduces the required memory footprint and further optimises the power consumption.
  • Fig. 4c shows a connection between the processing means 154 and the display unit 152 by a display bus 250 connection which uses part of the memory bus 252, i.e. the connection between the processing means 154 and the maximally one writable memory, such as the frame buffer 202, as shown in Fig.
  • the processing means 154 and the display unit 152 there is no direct connection between the processing means 154 and the display unit 152, as the display bus 250 and the memory bus 252 have shared parts.
  • the frame buffer 202 is integrated in the display controller, the load involved in refreshing the display may be removed from the main memory and system bus since the data traffic may be routed from the internal frame buffer to the display panel 156 through a separate bus.
  • the advantage of this way of working is that the main memory bus is free for other subparts of the system and that the power consumption of the bus accesses, required to refresh the display panel 156, is reduced.
  • the dedicated bus is shorter and less complex than the system bus and hence, it will pose a smaller load on the system's power consumption.
  • direct connection between the processing means 154 and the display panel 156 may be provided.
  • a dedicated display bus 254 is provided for directly connecting the processing means 154 and the display panel 156.
  • a separate driver bus for the display panel may furthermore be provided to provide power compensation for the leakage of the memory elements or to power the switches for the pixels of the display panel.
  • the display system described in the first embodiment wherein one writable memory external to the display panel is present on the data processing path between the processing means and the display panel, is suitable both for streaming video, i.e. wherein near-instantaneous delivery of various kinds of media, such as e.g. moving images, camera, mobile streaming media, digital or analog television, etc. as well as video or moving images obtained from a memory where it is locally stored.
  • the system also can be used for for still images or a sequence thereof.
  • the invention relates to a display system 400, 450, 500, 550 wherein no writable memory external to said display panel 156 is present in the image data processing path between the processing means 154 and the display panel 156.
  • the processing means 154 is directly connected to the display unit 152, comprising a display panel 156.
  • the display unit 152 furthermore comprises a display controller 157. Whereas in Fig. 6a, only information can be written to the display unit 152, i.e.
  • a display unit wherein information can both be written to as read from the display unit 152 or more particularly to and from the memory cells corresponding with the pixels of the display panel 156.
  • Fig. 6b and Fig. 7b show the respective connection between the processing means 154 and the display unit 152 for both the display systems shown in Fig. 6a and Fig. 7a.
  • the display busses shown provide the direct connection between the processing means 154 and the display unit 152, which may be considered as a dedicated display bus.
  • This bus can be a memory bus, as the present is not loaded or overloaded by a connection between the processing means 154 and a writable memory.
  • Fig. 7a a display unit is shown wherein information can both be written to as read from the display unit 152 or more particularly to and from the memory cells corresponding with the pixels of the display panel 156.
  • Fig. 6b and Fig. 7b show the respective connection between the processing means 154 and the display unit 152 for both the display systems shown in Fig. 6
  • a one way communication bus is provided, whereas in Fig. 7b, a two way communication bus is provided. In the latter case, both information can be written to the display unit 152 and information can be read from the display unit by the processing means 154.
  • an additional driver bus may be provided to solve for e.g. leakage of the memory cells or switches of the display panel 156.
  • a display system 500, 550 is shown comprising a processing means 154 and a display unit 152 comprising a display panel 156,. In these embodiments, no display controller is provided.
  • the display panel 156 may be provided with an additional driver bus 552, as shown in Fig. 9a.
  • a direct connection between the processing means 154 and the display panel 156 is provided, using a bus. This may be considered as a dedicated display bus, or as a memory bus as it provides connection between the processing means 154 and the display memory. Furthermore, as discussed above and also shown in Fig. 9b, an additional driver bus 552 may be provided to solve for leakage of the memory elements or switches provided for the pixels of the display panel.
  • the only video related memory that is required is the memory that exists on the display panel itself, for example an array of memory elements, each memory element being located at a pixel of a fixed format display.
  • the display panel according to the present embodiment thus is treated as an item of memory, for example it can be plugged directly onto a memory bus of an embedded processor or of a standalone computing and/or communications device such as a PC, laptop, PDA, mobile phone, smart phone.
  • the display may be plugged directly onto a motherboard of a PC.
  • the display panel thus may be plugged directly onto the memory bus.
  • the display systems described in the second embodiment are especially useful for media with a low new data rate, such as still images or a sequence thereof, or video wherein the new data rate is low such as e.g. in the use of a worksheet or text application, in an application showing a fixed image combined with a relatively slow changing image, etc.
  • the video signal is sent as a series of memory frames and can be displayed as if the display panel was a memory.
  • the video signal therefore does not require additional information which has been used in the past by CRT's, e.g. blanking periods, horizontal and vertical sync signals.
  • a display in accordance with the present invention can display an arbitrary image, e.g. a video optionally in colour. Consequently, less information needs to be provided in order to obtain the correct displaying of images on the display panel.
  • the system described in the previous embodiments is combined with a method for further reducing the power consumption, by only changing those pixels of a fixed format display that need to be updated because the information to be displayed by the pixel is to be changed.
  • the refresh of the display generates a large part of the total memory traffic and bus usage. Refreshing e.g. a 640 x 480 pixel, 60 Hz display that uses 18 bits to represent one pixel, generates a 316 Mbits per second load in the memory units and bus between the frame buffer and the LCD panel.
  • the consequences in power consumption are considerable: 6% of the total system power is needed to drive the LCD panel bus, the frame buffer accounts for 19% of the total power.
  • the present invention relates to a display system 150 according to the first embodiment, having one writable memory component external to the display panel 156, whereby the display system 150 furthermore is adapted for controlling the access to the writable memory component, which may be e.g. a frame buffer.
  • the one writable memory component, external to the display panel 156 typically is a single port memory component, in contrast to dual-port memory components often used in the prior art to provide a certain flexibility in design of the display system 150.
  • the single port memory component thus typically is not able to both read information from the processing means 154 and provide information to the display panel simultaneously, i.e. at the same time. In other words, reading and writing cannot be performed in parallel as there is only one memory port. Reading from and writing to the single port memory thus needs to be perfomed alternatingly.
  • the display system 150 comprises a control means adapted to control the access to the memory component.
  • This control means may be implemented both in hardware or in software.
  • the control means may time the read and write demands to the frame buffer such that reading and writing is not performed in parallel or in other words, the control means may control the processing means 154 and the display panel 156 such that they never access the information at the same time, and that the production of new pixels from the processing means 154, i.e. the generation or transmission of the new image to the one writable memory external to the display panel 156, may be always postponed till the display panel 156 has read the pixels of the current image from the one writable memory external to the display.
  • This one writable memory external to the display may be a single-buffered memory.
  • the memory may be capable of comprising only one image frame of the information to be displayed.
  • This single-buffered memory is especially usefull in combination with a memory component comprised in the display panel 156, built up from the different memory cells of the display panel 156 which are corresponding to the different pixels of the display panel 156.
  • the present invention relates to a method for driving a power optimised display.
  • the method comprises different steps, as shown in Fig. 10.
  • the method 570 comprises, receiving information to be displayed in a processing means 154.
  • the information to be received may be either still images or it may be video like information.
  • the information furthermore may be received from a storage location where it is stored, or the information may be received as streaming data.
  • the information is received in a processing means 154 which may be e.g. a microprocessor or a CPU, although the processing means 154 is not limited thereto.
  • a second step 574 the received information is converted in an image to be displayed.
  • This converting step 574 comprises the processing of the information to be displayed, e.g. in image frames.
  • the present method 570 thereby is characterised in that this converting of the information to be displayed is performed using only 1 writable memory component external to the display panel. The latter allows to significantly reduce the number of memory accesses, thus allowing to reduce the power consumption of the system.
  • the present step 574 especially can be performed in systems as described in the previous embodiment of the first aspect of this invention.
  • This converting step 574 thus comprises converting the information to be displayed in memory information suitable for the memory component built up from the memory cells of the pixels of the display panel 156. After the information to be displayed is converted in the appropriate memory information, the appropriate memory information is written to the memory cells of the display panel, thus allowing to create an image on the display panel. The latter is performed in step 576. The information thereby may be immediately displayed by the pixel as soon as the memory cell is written.
  • the invention relates to a display system 600 with lower power consumption, whereby the reduced power consumption is obtained by shifting the display panel of the display system to a separate bus on the processor.
  • the processor is directly connected to the display unit, without using the memory bus or part thereof.
  • a display connection 602 is provided between the processing means 154 and the display panel 156 which uses part of the memory connection 604 between the processing means 154 and the video memory 606 external to the display panel, which may be e.g. a video RAM on the main platform or e.g. a frame buffer.
  • the information traffic between the processing means 154 and the display panel 156 thus provides an additional load on the memory connection 604, typically a memory bus.
  • the display connection 602 between the processing means 154 which may e.g. be a CPU, and a display panel 156, are different from the memory connection 604 between the processing means 154 and the video memory 606 external to the display panel.
  • the display connection 602 between the processing means 154 and the display panel 156, and the memory connection 604 between the processing means 154 and the video memory 606 have no common part. The latter is obtained by providing a separate bus for different peripherals, e.g.
  • one peripheral is a display panel 156
  • the second peripheral is a video memory 606 such as e.g. a frame buffer.
  • a separate bus for connecting the display panel 156 may be called a dedicated display bus, as it provides a direct connection between the processing means and the display panel.
  • the processing means 154 can access different peripherals using different busses, thus decreasing the load on the memory bus, which results in an improved low power consumption.
  • the specific display system architecture and the method of connecting different components to the processing means using different busses may be applied to the different embodiments described in the first aspect of the invention. Some examples are shown in Fig. 13a and Fig.
  • the invention relates to a method for reducing the number of memory accesses, whereby advantage is taken of the content of the data that is displayed on the screen. It seldom occurs that, between two frames, every pixel of the new frame differs from the pixel at the same position in the previous frame. If, for a general display system, the system can only update those pixels that have changed when comparing the new frame to the current frame, it can avoid many unnecessary memory accesses. A broad range of applications can take advantage of such selective screen updating.
  • the information about which pixels need to be updated can e.g. be provided in a header of the frame that is sent to the video memory wherein the content dependent updating will be performed, i.e. for example the frame buffer or the on-display memory.
  • Video decoding applications can be optimised to only update those parts of the screen that have changed.
  • Applications requiring user input, such as calendars, spreadsheets, and word processors can take advantage of the fact that user input is most of the time limited to a small part of the screen area.
  • the present invention provides a modification to the software that generates the data for a video memory of the system, which may be e.g. a frame buffer, but which also may be the display panel itself. Instead of writing the entire video memory, the software only updates the pixels that have changed.
  • optimisation is performed on the level of the display panel, i.e. whereby the memory cells corresponding to the different pixels of the display panel are updated only if the value of the memory cell needs to be changed.
  • This may both be done in systems comprising another video memory, external to the display panel, or in systems wherein the video memory associated with the memory cells of the different pixels of the display panel is the only video memory present.
  • a video memory external to the display panel such as e.g. a frame buffer, and a video memory at the level of the display panel
  • the optimisation may be performed both at the level of the external video memory and at the pixel level video memory.
  • Content dependent updating is especially useful if only a fraction of the screen is to be updated between different subsequent frames.
  • Content dependent updating may be usefull for both for still images and for streaming video. If e.g. an MPEG4-coded video stream is used, only the content that has been changed when compared to the previous image, which may e.g. be found in the decoded macroblocks of a P-frame, can be sent to the screen.
  • the number of memory accesses e.g. the number of write operations from the processing means to one of the writable memories, typically may be minimized such that only the new updates are overwriting the current image info in the writable memory component.
  • the new updates thereby are the display data for those pixels that need to display differently between the current frame and the next frame of information to be displayed.
  • This optimisation may not only be performed in the writable memory component of the display panel, but also in the writable memory component external to the display panel. If e.g. a frame buffer is present, only the modified pixel display data, i.e. the display data corresponding with pixels that need to display different information between the current frame to be displayed and the next frame to be displayed, may be transferred to the frame buffer.
  • the different methods and systems for reducing the power consumption of a display system are non-providing one or more intermediate memories, updating the display pixel level video memory, i.e.
  • Optimisation of the power consumption based on reduction of the number of intermediate memories in the display system of the Personal Digital Assistant may be done by a hardware related architectural change, combined with software related changes.
  • a hardware related architectural change may e.g. be using a display provided with a per-pixel memory such as e.g. an active matrix driven display or a display with specifically introduced memory elements for each display.
  • Using the display panel as a large RAM memory, based on the memory elements for each of the pixels of the display panel is supported by the fact that the PDA typical has a fixed format display panel.
  • Another example of a system wherein power optimisation may play an important role is in systems having a small form factor, such as e.g. a watch, whereon a display application is to be run.
  • Such applications may be e.g. a visual information providing application such as e.g. a global positioning system application, a textual news providing application, a route mapping application, etc.
  • a visual information providing application such as e.g. a global positioning system application, a textual news providing application, a route mapping application, etc.
  • a battery having limited battery lifetime typically only have a very simple user interface.
  • An example thereof are GPS watches having only a very simple user interface on a black- and-white LCD display. These systems would largely benefit from display systems having a reduced power consumption. Again different methods for reducing power consumption could be applied to these systems, whereby only one method may be applied or different power consumption optimisation methods may be combined.
  • the different methods that may be applied are content dependent updating of the video memory, not providing one or more intermediate video memory components and/or providing a separate bus for connecting the display panel directly with the processing means.
  • the usability of such a device would be lifted an order of magnitude if the user could get a graphical feedback of the application run on the system, e.g. the GPS application.
  • USB Universal Serial Bus
  • a display unit can be attached to a host system by means of a Universal Serial Bus (USB) connection. Connecting the display triggers the software driver module on the host system that maps the display memory into the memory map of the processing means.
  • the signal transfer rate using an USB connection depends on the type of USB connection. Typically 1.5Mbits/sec (USB1.0) or 12Mbits/sec (USB1.1) can be transferred with the USB 1 standard, while USB 2.0 allows an additional transfer speed being 480Mbits/sec. Transfer furthermore is determined by the protocol used to divide the bus time, e.g.
  • USB display application that optimally can use the power consumption optimisations as discussed above is an e-book interface.
  • An e- book application typically updates the entire screen at once and then waits for user input, e.g. to load the new content. With memory cells located underneath every pixel, the display panel behaves as a static memory. The content consequently has only to be written once and remains static in between screen updates. The infrequent screen update requirement minimises power consumption by reducing the data transfers from host to screen.
  • an iPod system providing e.g. calender, game, address book applications, an advanced mobile telephone, a portable device combining e.g. streaming video with streaming audio, etc.
  • a two-step optimisation method for building a multimedia terminal that eliminates redundant memory accesses when interfacing to the display unit is applied.
  • the frame buffer access is optimised. Only parts of the screen that are modified between frames are written to the frame buffer. This optimisation reduces the number of memory accesses between processor and frame buffer. Hence, the power consumption of the system is reduced.
  • a new hardware architecture that eliminates the frame buffer is presented. This second step enables a further reduction of the power consumption.
  • the experimental results are obtained for proposed set-ups provided on a test platform of which the power consumption can be measured. Both dedicated test software and an existing compressed video decoder application are used to evaluate the impact of the optimisations. The experimental results were obtained using a readily available prototyping platform. The impact of the optimisations on real hardware thus is measured. The obtained test results furthermore indicate that similar results can be obtained for other display systems. The latter can be concluded by extrapolating the test results.
  • the hardware and software used in the measurement set-up is further described in more detail.
  • the hardware set-up consists of a test platform which is an XSCALE PXA250-based prototyping platform with 64 MB of SDRAM and a Tvia CyberPro 5205G-50 video processor.
  • the video buffer of the Tvia is mapped in the memory space of the processor. This allows to emulate e.g. an OLED display if the Tvia video processor is considered to be a display unit.
  • the operating system of the set-up is Linux.
  • the Tvia video processor generates a PAL video output signal. This video output signal is used to display the output of the test set-up on a standard TV screen.
  • the current drained by the entire platform was monitored at the power supply. The power required by the actual display unit, i.e.
  • the TV screen is not taken into account.
  • Three different software applications are tested. The first two are dedicated test applications.
  • the third application is an MPEG-4 video decoder that has been developed in our research group. This decoder allowed us to verify the predicted gain in a real-life application and is described in detail further on.
  • the test applications are written to be able to measure the impact of every step of the proposed optimisation. In a first test case, the influence of optimising the frame buffer access is measured.
  • the second test case allowed us to verify the direct video memory access optimisation.
  • the influence of the content dependent optimisations were studied with a set-up as schematically illustrated in Fig. 13a.
  • An application running on the processor of the test platform generates screen data.
  • This data is written into a frame buffer that is allocated in main memory of the system, indicated by arrow A in Fig. 13a.
  • the application copies the frame buffer content to the Tvia video controller, indicated by arrow B and C in Fig. 13a .
  • Eight frames per second are generated and written to the frame buffer (640 x 480 pixels, 16 bits per pixel).
  • the frame rate has been selected in order not to overload any hardware system limits, such as bus capacity or processor load.
  • the transfers from the frame buffer to the Tvia also occur eight times per second.
  • the impact of the memory transfers on the power usage is evaluated in five different cases, ranging from updating the entire display to doing no update at all.
  • the possible energy savings by integrating an OLED display with per-pixel memory are evaluated on the same hardware setup.
  • the frame buffer is eliminated, i.e. not provided in the display system, and the test application writes its data immediately to the Tvia video processor.
  • the impact of the display related memory accesses on the power usage is evaluated in five different cases, ranging from a full screen update to doing no update at all.
  • the block scheme of the test software shows that the only display related transfer is the one from the CPU to the Tvia video processor, as shown e.g. in Fig. 13b. The results are obtained, using the above described test cases with the above described hardware and software.
  • the idle power consumption of the platform is 5.3 W. It is important to understand that, as low power design techniques get more and more accepted, the CPU and its peripherals will start consuming a smaller amount of the total power. The memory related power consumption is not expected to drop that fast. This means that the impact of the memory operations on the power consumption will even become larger in future systems. In order to represent the measurement results, all further figures are expressed as a percentage of the maximal difference in power consumption, 770 mW.
  • the possible gain in power consumption ranges between 0% (when all pixels are updated) and 71 % (when no pixels are updated) compared to the original power consumption of the display related memory accesses.
  • 36% power is saved. This can e.g. be seen in table 1 , showing the power gained due to optimisation of the display-related memory accesses.
  • the second test case allows for power savings between 45% (the entire screen is updated) and 100%(in case of a static image).
  • a platform based on this architecture uses 72% less power for the display related memory accesses.
  • the results are indicated in Fig. 14, showing the relative amount of power consumption saved, for both content dependent updating in a prior art system (white bars) and combined content dependent updating in a system without frame buffer (dashed bars).
  • Fig. 14 showing the relative amount of power consumption saved, for both content dependent updating in a prior art system (white bars) and combined content dependent updating in a system without frame buffer (dashed bars).
  • the effect of that is that the absolute measured gain by introducing the new display will be even larger in existing systems.
  • the high throughput on the LCD panel bus due to the high refresh rate will cause a higher power drain than the energy consumption that occurs in our test set-up.
  • the absolute value of the power saving in a device also depends on the frame size, the frame rate and the system architecture (e.g. the type of RAM, the length of the system busses, ). Assuming that on average 50% of the pixels need to be refreshed between two frames, the obtained power savings are 277 mW (36%) for the content dependent optimisation (first test case) and 554 mW (72%) for the version with the per-pixel memory display (the second test case).
  • the proposed test-bed contains video at different bit rates and with varying degrees of motion: from mother and daughter, a head and shoulders type sequence to calendar and mobile, a highly complex sequence with multiple, heterogeneous motion. All sequences are compressed using an MPEG-4 Simple Profile coder which uses a hybrid video block-based algorithm exploiting temporal and spatial redundancy in subsequent frames.
  • intra blocks contain only independent texture information
  • inter blocks use motion compensated prediction
  • skipped blocks a special kind of inter blocks, in which none of the pixels change compared to the previous frame.
  • Table 2 represents the amount of blocks requiring a screen update, varying with the complexity of the video sequence to be displayed.
  • Table 2 lists the relative amount of intra, inter and skipped 8x8 blocks in the MPEG-4 Simple Profile video sequences. The amount of skipped blocks varies from virtually zero for highly complex to almost 80 % for low motion video. For an average sequence, around 75 % of the image is updated. This leads to respectively 18 % and 59 % power saving for the two optimisations.
  • the invention is particularly useful for battery powered devices with a display as main user interface, such as e.g. a handheld multimedia terminal which is portable, although the invention is not limited thereto. It is an advantage of the above described embodiments of the present invention that display systems and methods for using display systems are provided that allow for power saving by decreasing the required number of memory accesses to put a frame on the screen. It is also an advantage of several of the above described embodiments of the present invention that both hardware design an software design is optimised in order to obtain a reduced power consumption. It is furthermore an advantage of the embodiments of the present invention that, for display systems incorporated in a battery powered device, the battery autonomy can be increased. It is also an advantage of the present invention that energy savings up to 72% of the power can be obtained, compared to traditional display system setups.

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Abstract

L'invention concerne un système d'affichage et un procédé d'affichage qui permettent d'afficher des informations. Ce système comprend un moyen de traitement et une unité d'affichage comprenant un panneau d'affichage. Sur la voie de traitement des données d'image permettant de transférer des informations au panneau d'affichage, le nombre de composants de mémoire accessibles en écriture extérieurs au panneau d'affichage est limité au maximum à un. Ce composant de mémoire accessible en écriture est conçu de façon qu'il comprennent au moins une seule trame d'image. Ce système et ce procédé permettent de réduire la consommation d'énergie en se basant sur la réduction du nombre d'accès mémoire. L'invention concerne également un procédé et un système dans lesquels une mise à jour des informations de pixel est effectuée en fonction du contenu. L'invention concerne en outre un système dans lequel un panneau d'affichage est connecté au moyen de traitement à l'aide d'un bus d'affichage spécialisé séparé.
EP05706372A 2004-02-13 2005-02-14 Procedes et systemes d'affichage a consommation d'energie optimisee Withdrawn EP1714208A2 (fr)

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