EP1784701A1 - Systeme de miroir de courant - Google Patents

Systeme de miroir de courant

Info

Publication number
EP1784701A1
EP1784701A1 EP05790411A EP05790411A EP1784701A1 EP 1784701 A1 EP1784701 A1 EP 1784701A1 EP 05790411 A EP05790411 A EP 05790411A EP 05790411 A EP05790411 A EP 05790411A EP 1784701 A1 EP1784701 A1 EP 1784701A1
Authority
EP
European Patent Office
Prior art keywords
current mirror
transistor
transistors
cascode
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05790411A
Other languages
German (de)
English (en)
Inventor
Jakob Jongsma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram AG
Original Assignee
Austriamicrosystems AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems AG filed Critical Austriamicrosystems AG
Publication of EP1784701A1 publication Critical patent/EP1784701A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to a current mirror arrangement with cascode stage according to the preamble of patent claim 1.
  • Current mirror circuits can be used in a variety of switching techniques or integration processes, such as in bipolar circuit technology or in metal-insulator-semiconductor (MIS) circuitry.
  • MIS metal-insulator-semiconductor
  • Figure 1 shows a generic, known current mirror with cascode stage.
  • the actual current mirror comprises two transistors 2, 3 which are each connected to one terminal of their controlled paths against a reference potential terminal 1.
  • the transistors 2, 3 of the current mirror in the present case are each of the n-conductivity type, ie N-channel transistors.
  • the control terminals of the transistors 2, 3 are also referred to as gate and are directly verbun ⁇ the.
  • the input-side transistor 2 of the current mirror has a controlled path, which is connected with a first terminal to the gate terminal of the current mirror transistor 2 and with a further terminal to the reference potential terminal 1.
  • the connected to the gate terminal of the transistor 2 terminal of the controlled path of the transistor 2 is connected via the controlled path of a first cascode Transistor 9 and connected via a current source 4 to a supply potential connection 5.
  • the current source 4 represents one of the current mirror arrangement with cascode zu ⁇ leading input current.
  • the output-side transistor 3 of the current mirror of FIG. 1 also has a controlled path which is connected on the one hand to the reference potential terminal 1 and on the other hand via a second cascode transistor 10 to one terminal of a controlled path of a further transistor 6.
  • the further transistor 6 is connected to another terminal of its controlled path to the supply potential terminal 5 of the circuit and has a p-type conductivity.
  • the further transistor 6 is with respect to the StromLitetran- transistors 2, 3, but also with respect to the cascode transistors 9, 10 of the opposite conductivity type.
  • the control terminal of the transistor 6 is connected to that terminal of its controlled path, which is also connected to the cascode transistor 10.
  • the cascode stage of the current mirror arrangement of FIG. 1 comprises the two cascode transistors 9, 10, of which the first cascode transistor 9 is connected in the input-side current path between current source 4 and transistor 2.
  • the second transistor 10 of the cascode stage is connected in the output-side current path of the arrangement between the further transistor 6 connected as a diode and the output-side current mirror transistor 3.
  • the transistors 9, 10 themselves form a current mirror with each other, the first cascode transistor 9 forming the input-side transis tor of the cascode current mirror 9, 10.
  • the circuit according to FIG. 1 can be used to generate two complementary bias signals. For this purpose, output terminals 7, 8 are formed.
  • a first output terminal 7 for providing a blowing signal NBIAS is formed at the common gate terminal of the current mirror transistors 2, 3 and thus at the connection node of the current mirror transistor 2 with the cascode transistor 9.
  • Another output terminal 8 is formed with the control terminal of the further transistor 6 and with the connection node between further transistor 6 and second cascode transistor 10.
  • the output terminal 8 serves as an output for picking up a bias signal PBIAS for p-MOS components.
  • the bias signal NBIAS which can be tapped off at the first output terminal, is used to drive n-type MOS components.
  • the two bias signals PBIAS, NBIAS can, for example, be used to set operating points of other components not shown in FIG.
  • the source-drain voltages of the transistors 2, 9 are to be subtracted from the supplied supply voltage. to determine the remaining voltage range for the input signal.
  • This remaining drive range or input voltage range is also referred to as headroom.
  • the object of the present invention is to provide a current mirror arrangement which provides a larger modulation range at its input with the same supply voltage and can have a construction with a cascode stage.
  • the object is achieved by a current mirror arrangement, which is developed in such a way that the first and the second cascode transistor each comprise a plurality of partial transistors connected in series with one another with respect to their controlled paths.
  • the first cascode transistor which forms a common input current path together with the first current mirror transistor, is divided into a plurality of partial transistors.
  • the subtransistors each have controlled paths which together form a series circuit.
  • the second cascode transistor is divided into a plurality of subtransistors.
  • the common control connection of the current mirror transistors it is possible to connect the common control connection of the current mirror transistors to one of the intermediate nodes formed by the division into partial transistors in the first cascode transistor. Accordingly, the common control connection of the current mirror transistors no longer necessarily has to be connected between the first cascode transistor and the first current mirror transistor, but may be connected between partial transistors.
  • the control voltage is reduced by a specific number of partial voltages which drop across the controlled sections of the subtransistors.
  • the input voltage range, English: Headroom, of the current mirror is increased at the same supply voltage.
  • the supply voltage for the same control range can be reduced.
  • cascode transistor is not understood in the narrow sense, but rather the proposed principle can also be applied to other current mirror arrangements having a plurality of stacked transistors, for example so-called Wilson current mirrors.
  • the first Kasko ⁇ de-transistor with respect to the first current mirror transistor forms a cascode stage.
  • the second cascode transistor forms a cascode stage with respect to the second current mirror transistor.
  • the common control terminal of the first and the second current mirror transistor is connected to a connection node.
  • the connection node is formed between two partial transistors of the first cascode transistor.
  • the first cascode transistor when dividing the first cascode transistor into more than two subtransistors, it is intended to provide the connection node between only one subtransistor ei ⁇ neminte all other subtransistors of the first cascode transistor on the other hand to this one subtransistor. Accordingly, only a partial transistor of the first cascode transistor is connected with respect to its controlled path between the connection node and an input of the current mirror or a current source connected thereto. This one subtransistor is preferably operated in saturation, while the remaining subtransistors may operate in their linear range. According to a further, preferred embodiment, an output transistor is connected to the side of the second cascode transistor remote from the second current mirror transistor. At the output transistor, an output terminal is formed, which serves to deliver a first current.
  • a further output terminal for providing a second current is formed at that connection node with which the common control terminal of the two current mirror transistors is connected.
  • the subtransistors of the first cascode transistor preferably each have a control terminal, all the control terminals of the subtransistors being connected to one another. Likewise, the control terminals of the subtransistors of the second cascode transistor are all connected together.
  • the control terminals of the subtransistors of the first cascode transistor and the control terminals of the subtransistors of the second cascode transistor are preferably also connected to one another.
  • the output transistor, the second cascode transistor and the second current mirror transistor are arranged in a common output current path in a series connection, wherein the common current path is connected between a supply potential terminal and a reference potential terminal.
  • the first cascode transistor and the first current mirror transistor are arranged in a common input current path.
  • the output transistor is preferably connected as a diode.
  • the conductivity type of the output transistor on the one hand and the conductivity type of the two cascode transistors on the other hand are preferably complementary to one another.
  • the cascode transistors preferably have the same conductivity type as the current mirror transistors.
  • the first cascode transistor and the first current mirror transistor are preferably arranged together with a current source in a common input current path.
  • the current source represents the current that is to be supplied to the current mirror.
  • the current source, the first cascode transistor and the first current mirror transistor are preferably connected in a series connection between a supply and a reference potential connection.
  • the cascode transistors are preferably each connected between a current mirror transistor on the one hand and the output transistor or the current source on the other hand.
  • a feedback current mirror is formed by the second cascode transistor and the first cascode transistor. In this case, the second cascode transistor is connected as a diode.
  • the second current mirror transistor forms the input-side current mirror transistor with respect to the main current mirror and is therefore connected as a diode instead of the first current mirror transistor.
  • a Wilson current mirror is formed.
  • the current mirror arrangement is preferably constructed in integrated circuit design.
  • the current mirror arrangement is preferably constructed in the so-called complementary metal oxide semiconductor, CMOS circuit technology. Further details and advantageous developments of the proposed principle are the subject of the dependent claims.
  • FIG. 1 shows a current mirror arrangement with cascode stage
  • FIG. 2 shows a first exemplary embodiment of a current mirror arrangement according to the proposed principle with a cascode stage
  • FIG. 3 shows a current mirror arrangement according to Wilson
  • FIG 4 shows a second embodiment of a current mirror arrangement according to the proposed principle in a Wilson current mirror.
  • FIG. 1 shows a current mirror arrangement with cascode stage.
  • the circuit of FIG. 1 has already been explained in the introduction to the description and will therefore not be described again at this point.
  • FIG. 2 shows a current mirror arrangement on a first embodiment according to the proposed principle.
  • a first current mirror transistor 2 is provided which forms a current mirror with a second current mirror transistor 3.
  • the controlled paths of the two current mirror transistors 2, 3 are each connected to a reference potential terminal 1 with one of their terminals.
  • the control terminals of Strom ⁇ mirror transistors are interconnected.
  • the further connection of the controlled sections of the current mirror transistors 2, 3 is connected to a respective cascode transistor 11, 12.
  • the first cascode transistor 11 and the second cascode transistor 12 each have a plurality of partial transistors 13, 14, 15 connected in series with each other in terms of their controlled routes. 16, 17, 18 on.
  • the partial transistors 13, 14, 15 of the first cascode transistor 11 are, like the two current mirror transistors 2, 3, formed as MOS transistors and have a common channel length, the alsumm ⁇ example, that of a conventional cascode transistor 9 of Figure 1 corresponds.
  • the control terminals of the subtransistors 13, 14, 15 of the first cascode transistor 11 are connected to each other and to a terminal of the controlled path of the cascode transistor 11, which is not connected to the current mirror transistor 2. This connection is also connected to a current source 4, which provides an input current for the current mirror.
  • the second cascode transistor 12 likewise comprises a plurality of partial transistors 16, 17, 18 connected in series with one another with respect to their controlled paths, whose 5 control terminals are likewise connected to each other and to the control terminals of the partial transistors 13, 14, 15 of the first cascode transistor 11 ,
  • the sum L of the channel lengths Lmin of the individual subtransistors in the second cascode transistor 12 also corresponds, for example, to the channel length of the second cascode transistor 10 of FIG.
  • the second cascode transistor 12 is switched between the second current mirror transistor 3 and an output transistor 6 ge.
  • the output transistor 6 is of a p-channel type
  • the output transistor 6 is connected as a diode.
  • a PBIAS signal can be tapped off at the gate terminal of the output transistor 6 which is connected to a connection of its controlled path.
  • connection node VGL which is formed between two subtransistors 14, 15 of the first cascode transistor 11.
  • the connection node VG1 is also connected to the common control terminal of the current mirror.
  • connection node VGl is separated from the current source 4 by only a partial transistor 15.
  • the remaining subtransistors 13, 14 are connected between the connection node VG1 and the first current mirror transistor 2.
  • the two cascode transistors 11, 12 By dividing the two cascode transistors 11, 12 into a number of series-connected subtransistors and connecting the gate terminal of the NMOS current mirror 2, 3 to the source terminal of the uppermost subtransistor 15 of the first cascode transistor is advantageously the Voltage across cascode transistor 11 and current mirror transistor 2 is reduced. This reduction takes place by the sum of the drain-source voltages of the subtransistors 13, 14 below the uppermost subtransistor 15 of the first cascode transistor 11. In turn, a larger input voltage range for the current source 4 is available. This means that the so-called headroom is enlarged. In this case, the sum of the channel lengths of the subtransistors 13 to 15 corresponds to the total channel length which a single cascode transistor would have.
  • the channel lengths of the individual subtransistors are advantageously the same. For symmetry reasons, the same division also takes place in the case of the second cascode transistor.
  • the current mirror arrangement according to FIG. 2 additionally provides two complementary-type bias signals PBIAS, NBIAS, which means that components of the complementary conductivity type can be driven with the two bias signals, for example for setting the operating point.
  • the present circuit allows due to the structure shown and the structure with cascode stage a particularly good match of the two bias signals to each other, so that a high Schal ⁇ symmetry and a good matching of driven, sym metric or complementary components is ensured.
  • the partial transistor 15 While it is preferable for the partial transistor 15 to be operated in saturation between the connection node VG1 and the current source 4, the remaining partial transistors need not be saturated, but can be operated in their linear range.
  • transistors of the complementary conductivity type can also be used in modifications of the circuit shown.
  • FIG. 3 shows a Wilson current mirror to which the proposed principle can also be applied.
  • two current mirror transistor pairs are stacked one above the other 5, however, one of the two current mirrors is designed as a feedback current mirror in the Wilson current mirror. Accordingly, in the circuit of FIG. 3, a forward current mirror with the transistors 19, 20 and a reverse current mirror with the current mirror transistors 21, 22 are provided.
  • the first transistor 19 and the first current mirror transistor 21 together with the current source 4 form a series circuit.
  • the first transistor 19 is connected as a diode.
  • the second transistor 20 also forms a series circuit with the second current mirror transistor 22.
  • 15 second current mirror transistor 22 is connected as a diode.
  • the second transistor 20 and the first current mirror transistor 21 are not connected as diodes.
  • the transistors 19, 20, 21, 22 of Figure 3 replace the transistors 2, 3, 11, 12 of Figure 2, otherwise the circuit is unchanged and
  • Transistors 19, 20 in turn in partial transistors, so er ⁇ give the advantages already described for a Wil ⁇ son current mirror.
  • FIG. 4 Such a further developed circuit is shown in FIG.
  • the circuit of FIG. 4 corresponds in structure and function largely to that of FIG. 3 and will not be described again in this respect.
  • the transistors 19, 20 of Figure 3 are in Figure 4 in sub-transistors 23, 24, 25; 26
  • the subtransistors are in turn connected in pairs with respect to their controlled routes in series.
  • the control terminals of all subtransistors 23 to 28 are connected together in a common control Finally connected, which is connected to the circuit node formed between the partial transistor 25 and the power source 4. Accordingly, the transistors 19, 20, which comprise the subtransistors 23 to 28, form the forward current mirror of the circuit arrangement of FIG.
  • connection node 29 which is connected according to the proposed principle between two partial transistors of the transistor 20.
  • the connecting node between the subtransistors 27, 28 has been chosen analogously to the circuit of FIG. 2 as connection point in order to obtain the largest possible voltage range as a headroom.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

La présente invention concerne un système de miroir de courant dans lequel deux transistors à miroir de courant (2, 3) forment un miroir de courant. Deux transistors cascodes (11, 12) sont connectés aux deux transistors à miroir de courant (2, 3), formant ainsi un étage de cascode. Les transistors cascodes (11, 12) comprennent respectivement plusieurs transistors partiels (13, 14, 15; 16, 17, 18) qui sont connectés les uns aux autres en série par rapport à leurs voies commandées. Il est ainsi possible de raccorder les noeuds de liaison des transistors à miroir de courant à un noeud de liaison entre deux transistors partiels (14, 15), ce qui engendre un élargissement de la gamme de tensions d'entrée d'une source de courant (4) fournissant un courant d'entrée pour le miroir de courant.
EP05790411A 2004-09-01 2005-08-31 Systeme de miroir de courant Ceased EP1784701A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004042354A DE102004042354B4 (de) 2004-09-01 2004-09-01 Stromspiegelanordnung
PCT/EP2005/009398 WO2006024525A1 (fr) 2004-09-01 2005-08-31 Systeme de miroir de courant

Publications (1)

Publication Number Publication Date
EP1784701A1 true EP1784701A1 (fr) 2007-05-16

Family

ID=35462615

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05790411A Ceased EP1784701A1 (fr) 2004-09-01 2005-08-31 Systeme de miroir de courant

Country Status (4)

Country Link
US (1) US20070290740A1 (fr)
EP (1) EP1784701A1 (fr)
DE (1) DE102004042354B4 (fr)
WO (1) WO2006024525A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004021232A1 (de) * 2004-04-30 2005-11-17 Austriamicrosystems Ag Stromspiegelanordnung
JP4761458B2 (ja) * 2006-03-27 2011-08-31 セイコーインスツル株式会社 カスコード回路および半導体装置
US7724077B2 (en) * 2008-07-28 2010-05-25 Freescale Semiconductor, Inc. Stacked cascode current source
EP2784934B1 (fr) 2013-03-25 2020-09-23 Dialog Semiconductor B.V. Circuit de polarisation électronique destiné à transconductance constante
CN114911302A (zh) * 2021-02-09 2022-08-16 虹晶科技股份有限公司 电流镜电路
US11966247B1 (en) * 2023-01-27 2024-04-23 Psemi Corporation Wide-swing intrinsic MOSFET cascode current mirror
US12476598B2 (en) 2023-01-27 2025-11-18 Psemi Corporation Intrinsic MOS cascode differential input pair

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952884A (en) * 1998-02-18 1999-09-14 Fujitsu Limited Current mirror circuit and semiconductor integrated circuit having the current mirror circuit

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Publication number Priority date Publication date Assignee Title
US4550284A (en) * 1984-05-16 1985-10-29 At&T Bell Laboratories MOS Cascode current mirror
US5635869A (en) * 1995-09-29 1997-06-03 International Business Machines Corporation Current reference circuit
GB9809438D0 (en) * 1998-05-01 1998-07-01 Sgs Thomson Microelectronics Current mirrors
US6528981B1 (en) * 1999-07-23 2003-03-04 Fujitsu Limited Low-voltage current mirror circuit
JP2001156558A (ja) * 1999-11-24 2001-06-08 Mitsubishi Electric Corp カスコード・カレントミラー回路
US6680605B2 (en) * 2002-05-06 2004-01-20 Exar Corporation Single-seed wide-swing current mirror
ITTO20020816A1 (it) * 2002-09-19 2004-03-20 Atmel Corp Specchio di corrente a bassa tensione a dinamica rapida con
TWI287185B (en) * 2002-09-19 2007-09-21 Atmel Corp Fast dynamic low-voltage current mirror with compensated error

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952884A (en) * 1998-02-18 1999-09-14 Fujitsu Limited Current mirror circuit and semiconductor integrated circuit having the current mirror circuit

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
NOREN K.V. ET AL: "The Circuits and Filters Handbook, Second Edition. Chapter 56: Analog Circuit Cells", 31 December 2003, WAI-KAI CHEN (EDITOR), CRC PRESS, BOCA RATON, US *
See also references of WO2006024525A1 *
YAN S.; SANCHEZ-SINENCIO E.: "Low voltage Analog Circuit Design Techniques: A Tutorial", IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, vol. E00-A, no. 2, 2 February 2000 (2000-02-02), pages 1 - 17 *

Also Published As

Publication number Publication date
US20070290740A1 (en) 2007-12-20
WO2006024525A1 (fr) 2006-03-09
DE102004042354B4 (de) 2008-06-19
DE102004042354A1 (de) 2006-03-09

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