EP1869711A2 - Production de transistors vdmos a etablissement de contact de grille optimise - Google Patents

Production de transistors vdmos a etablissement de contact de grille optimise

Info

Publication number
EP1869711A2
EP1869711A2 EP06725692A EP06725692A EP1869711A2 EP 1869711 A2 EP1869711 A2 EP 1869711A2 EP 06725692 A EP06725692 A EP 06725692A EP 06725692 A EP06725692 A EP 06725692A EP 1869711 A2 EP1869711 A2 EP 1869711A2
Authority
EP
European Patent Office
Prior art keywords
layer
dielectric layer
contact hole
gate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06725692A
Other languages
German (de)
English (en)
Inventor
Jochen Doehnel
Siegfried Hering
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Publication of EP1869711A2 publication Critical patent/EP1869711A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures

Definitions

  • VDMOS transistors use various technologies for the fabrication of VDMOS transistors.
  • a single VDMOS cell as a base element of the VDMOS transistors is described in sufficient detail in the literature and is assumed to be known.
  • An essential part of the manufacturing process is the contacting of a composite of VDMOS cells, in particular the method of contacting the gate electrode.
  • VDMOS cells are contacted at three locations. On the one hand on the back of the disk or chip (large area), on the other hand on the disk or chip surface at narrow contact points. At the disk or chip surface, the gate and source / body contact must be realized. The two types of contact the
  • the source / body contact is made by a single etch into the single crystal silicon.
  • the use of only one mask layer is problematic for the two contact hole types.
  • the problem is that during the plasma etch process, both via types, i. the gate and the source / body contact are etched simultaneously.
  • the depth of the etching of the source / body contact into the silicon is about the same order of magnitude as the thickness of the polysilicon layer under the gate contact (about 0.3 ⁇ m to 0.5 ⁇ m), which is the electrical terminal of the gate.
  • the polysilicon layer thickness in the region of the gate contact hole area tends to zero.
  • the source region it is also necessary for the source region to reduce the intermediate insulator layer in the contact hole in its lateral extent to a certain extent for adequate contacting.
  • the source contact hole widens in the direction of the gate. This process is sufficiently described.
  • the disadvantage of the method is that at the same time with completely or partially removed polysilicon in the gate contact hole, the field oxide is etched in the gate contact hole. The etching attacks the field oxide in the Depth and undercuts the polysilicon. This results in a deformed gate contact from which late effects for the reliability of the transistor can result.
  • a deformed gate contact (detail 27b) is shown in stylized form.
  • the invention has for its object to design a method for producing a VDMOS transistor so that the gate contact of the individual cells and thus of the transistor is improved, i. is achieved with the constructively targeted whole contact surface and with high reproducibility, whereby data integrity and reliability of the device can be improved.
  • a dielectric layer is applied which, on the one hand, can be etched and thus removed together with the etching back of the second dielectric layer in a suitable etching process in the region of the gate contact, but which on the other hand serves as an effective etching stop layer during the plasma etching.
  • a high degree of integrity of the polysilicon is achieved, while reliable etching back of the second dielectric layer, which serves as an interlayer insulator, can take place.
  • etching properties of the first dielectric layer for the isotropic etching process are set such that for a desired removal of material of the second dielectric layer during the isotropic etching process, the first dielectric layer in the gate contact hole is completely removed.
  • the etching of a recess and removal of the first dielectric layer is carried out using the same etching mask layer. This results in a highly efficient process sequence without sacrificing the benefits outlined above.
  • the first and second dielectric layers comprise silicon oxide.
  • the first dielectric layer may be considered to be a part of the interlayer insulator that allows more efficient process design but does not alter the overall performance of the interlayer insulator, thus maintaining a high degree of compatibility with conventional techniques.
  • forming the gate contact hole and the body / source contact hole comprises:
  • Controlling the common etch process using endpoint detection that detects the exposure of the well area ensures a reliable covering of the polysilicon layer by the first dielectric layer in the gate contact hole, even if the first and the second dielectric layer behave very similar during the etching process.
  • the object is achieved, wherein, in particular, an efficient process sequence is achieved due to the use of the same mask layer for the patterning of the contact holes, the formation of the depression in the well region and the back etching of the interlayer insulator with removal of the first dielectric layer in the gate contact hole (claim 6) ).
  • the claimed invention has the advantages that the additional first dielectric layer, referred to in some embodiments as Oxide layer is provided (Si oxide without significant other components, which is hereinafter referred to as undoped, for example, made of TEOS Si ⁇ 2), which is applied to the unstructured polysilicon, during silicon etching of the source / body contact protects the polysilicon layer. It is then removed during the etching back of the intermediate insulator, after which an undisturbed homogeneous contact surface of the polysilicon is available in the gate contact holes.
  • Oxide layer Si oxide without significant other components, which is hereinafter referred to as undoped, for example, made of TEOS Si ⁇ 2
  • Figure 1 to Figure 4 show a schematic sectional view of the stages of a
  • Figure 1 shows the edge structure of a VDMOS transistor and a VDMOS cell in an early stage of the technological process.
  • the base material consists in one embodiment of a highly doped silicon wafer 1 with an epitaxial layer 2 of the same doping type.
  • a thick oxide layer 3 is grown, which is photolithographically patterned and etched.
  • the patterned oxide layer 3 still has the task of breaking down the drain voltage to the chip surface and forming a buffer layer between epitaxial layer 2 and gate contact layer.
  • a first dielectric layer 6 for example in the form of an "undoped" oxide layer, e.g. deposited on the basis of TEOS. It is designed with regard to its layer thickness and etching rate such that it is completely removed from the gate contact hole in the later process when the source contact hole is etched back in the direction of the gate.
  • the layers 5 and 6 are structured and thus the areas for the trough 8 are defined, as shown in FIG.
  • the so-called well area 8 introduced.
  • the doping type is opposite to that of the epitaxial layer.
  • the following tempering is used i.a. for generating the channel region under the polysilicon gate.
  • the highly doped source 9 is realized by implantation.
  • the so-called inter-insulator layer of e.g. Borphosphorsilikatglas or other suitable material as a second dielectric layer 10 deposited.
  • Gate contact hole is larger than in the source / body contact hole, since there lacks the first dielectric layer 6.
  • the first dielectric layer which may be provided as an undoped oxide layer 6.
  • the first dielectric layer which may be provided as an undoped oxide layer 6.
  • the layer 6 is maintained in the gate contact region. Following the patterning process, a high-dose implantation with dopants of the same charge type as the well provides for a low-resistance body contact 12.
  • the inter-insulator layer 10 in the source / body contact hole has to be wet-chemically reset or etched back by another isotropic etching process.
  • the layer 6 in the gate contact hole is simultaneously completely removed, as shown in FIG.
  • the described process in the gate contact region provides an undisturbed planar polysilicon surface.
  • Inter-insulator layer e.g., BPSG

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Shift Register Type Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé permettant de produire des transistors VDMOS, selon lequel une configuration en couches et un déroulement de procédé permettent de parvenir à un établissement de contact de grille amélioré, avec production simultanée de contacts de source et de grille, au moyen d'un seul masque perforé pour contacts (photomasque).
EP06725692A 2005-04-13 2006-04-10 Production de transistors vdmos a etablissement de contact de grille optimise Withdrawn EP1869711A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005008191A DE102005008191B4 (de) 2005-04-13 2005-04-13 Verfahren zur Herstellung von VDMOS-Transistoren
PCT/EP2006/061497 WO2006108827A2 (fr) 2005-04-13 2006-04-10 Production de transistors vdmos a etablissement de contact de grille optimise

Publications (1)

Publication Number Publication Date
EP1869711A2 true EP1869711A2 (fr) 2007-12-26

Family

ID=36670688

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06725692A Withdrawn EP1869711A2 (fr) 2005-04-13 2006-04-10 Production de transistors vdmos a etablissement de contact de grille optimise

Country Status (4)

Country Link
US (1) US8268688B2 (fr)
EP (1) EP1869711A2 (fr)
DE (1) DE102005008191B4 (fr)
WO (1) WO2006108827A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005008191B4 (de) 2005-04-13 2010-12-09 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von VDMOS-Transistoren
CN103151268B (zh) 2013-03-21 2016-02-03 矽力杰半导体技术(杭州)有限公司 一种垂直双扩散场效应管及其制造工艺
DE102015102130B4 (de) 2015-02-13 2022-07-14 Infineon Technologies Ag Halbleiterbauelemente und ein Verfahren zum Bilden eines Halbleiterbauelements
CN109300847B (zh) * 2017-07-25 2021-03-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
DE102017120943B4 (de) * 2017-09-11 2019-05-09 Infineon Technologies Austria Ag Verfahren zur Herstellung eines MOSFETs

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5795793A (en) 1994-09-01 1998-08-18 International Rectifier Corporation Process for manufacture of MOS gated device with reduced mask count
DE19733350C1 (de) * 1997-08-01 1999-03-04 Siemens Ag Verfahren zur Herstellung eines MOSFET's
JP3298472B2 (ja) * 1997-09-26 2002-07-02 関西日本電気株式会社 絶縁ゲート型半導体装置の製造方法
ITVA20010045A1 (it) * 2001-12-14 2003-06-16 St Microelectronics Srl Flusso di processo per la realizzazione di un vdmos a canale scalato e basso gradiente di body per prestazioni ad elevata densita' di corren
DE102005008191B4 (de) 2005-04-13 2010-12-09 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von VDMOS-Transistoren

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006108827A2 *

Also Published As

Publication number Publication date
US8268688B2 (en) 2012-09-18
US20100035366A1 (en) 2010-02-11
DE102005008191B4 (de) 2010-12-09
WO2006108827A3 (fr) 2007-02-01
DE102005008191A1 (de) 2006-10-26
WO2006108827A2 (fr) 2006-10-19

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