EP1891535A2 - Procede de communication entre au moins deux abonnes d'un systeme de communication - Google Patents

Procede de communication entre au moins deux abonnes d'un systeme de communication

Info

Publication number
EP1891535A2
EP1891535A2 EP06763233A EP06763233A EP1891535A2 EP 1891535 A2 EP1891535 A2 EP 1891535A2 EP 06763233 A EP06763233 A EP 06763233A EP 06763233 A EP06763233 A EP 06763233A EP 1891535 A2 EP1891535 A2 EP 1891535A2
Authority
EP
European Patent Office
Prior art keywords
data
address
lines
bus
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06763233A
Other languages
German (de)
English (en)
Inventor
Andreas Kneer
Axel Aue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1891535A2 publication Critical patent/EP1891535A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Definitions

  • the present invention relates to a method for communication between at least two users of a communication system via a plurality of data lines of a data bus, some of which are used as address lines of an address bus, wherein data and addresses are multiplexed.
  • the invention also relates to a bus system for communication between at least two users of a communication system, wherein the bus system comprises a plurality of data lines of a data bus, some of which can be used as address lines of an address bus, wherein the transmission of data via the data lines and addresses via the address lines in the multiplex ,
  • the present invention also relates to a memory module associated with a microprocessor which is connected to the microprocessor via a plurality of data lines of a data bus, some of which can be used as address lines of an address bus, data and addresses being multiplexed.
  • a memory module associated with a microprocessor which is connected to the microprocessor via a plurality of data lines of a data bus, some of which can be used as address lines of an address bus, data and addresses being multiplexed.
  • a memory module associated with a microprocessor which is connected to the microprocessor via a plurality of data lines of a data bus, some of which can be used as address lines of an address bus, data and addresses being multiplexed.
  • the processor applies a 24-bit address of a desired memory cell to the bus system and activates a Chip Select (CS) signal and an Address Latch Enable (ALE) signal. Shortly thereafter, the processor disables the ALE signal and the memory device remembers the ALE signal transmitted address and retrieves the data from the corresponding memory cell. In a data transfer in the burst, data is fetched from the corresponding memory cell and from subsequent memory cells. Then the processor switches via an Output Enable (OE) signal
  • Output driver of the memory module reads the applied data.
  • Communication method of the aforementioned type proposed that redundant data are transmitted simultaneously with the transmission of the address via the address lines via at least one of the data lines not used as an address line.
  • Transmission of the addresses are necessary (for example, 24 lines), some bus lines are unused during the addressing phase. These unused bus lines are used according to the invention during the addressing phase for transmitting the redundant data, preferably in the form of data bits.
  • the redundant information can be used to secure the transmission path between the participants of the communication system. In this way it is possible to provide with minimal effort, especially without additional bus lines too need to secure the transmission path between microprocessor and memory. As a result, transmission errors can be detected and appropriate measures taken. These measures may be, for example, to mark the transmitted data as faulty and to issue a corresponding notice to the user. A repetition of the data transmission is conceivable.
  • checksums are transmitted as redundant data.
  • a cross sum is formed over the data to be transmitted and, depending on whether the cross sum represents an even or an odd number, a "1" or a "0" is transmitted as a check bit.
  • the bus system comprises means for transmitting redundant data simultaneously with the transmission of the address via the address lines, wherein the means for transmitting the redundant data at least one of do not use data lines not used as address lines.
  • FIG. 1 shows a bus system according to the invention between a
  • Microprocessor and a memory module for implementing the method according to the invention according to a preferred embodiment
  • FIG. 1 shows an interconnection of certain signals in
  • Figure 3 is a timing diagram of a plurality of signals in the
  • Figure 4 is a timing diagram of several signals in the
  • the bus system 1 is arranged between a memory module 2 and a processor 3 (central processing unit (CPU)) of a microprocessor module 4.
  • the memory module 2 includes, for example, a flash memory.
  • the bus system 1 comprises 32 bus lines BLO - BL31, which are connected to the Transmission of data from the memory module 2 to the microprocessor 3 are all used as data lines DO - D31 a data bus.
  • some of the bus lines BLO - BL31 are used as address lines AO - A23 of an address bus.
  • the 32-bit data and the 24-bit addresses are multiplexed on the same bus lines BL0 - BL31.
  • the bus system 1 has control lines, of which in FIG. 1
  • a multiplexed memory access according to a known method proceeds as follows:
  • the memory module 2 remembers the address and fetches the data from the or the corresponding memory cells.
  • OE LOW
  • the processor 3 sets the 24-bit address (AO - A23) and activates the ALE signal and the CS signal.
  • the memory module 2 Based on the fact that the ALE signal is LOW (activated), the memory module 2 according to the invention recognizes that, on the one hand, an address AO - A23 is present and the other output driver (driver) of the memory module 2 may be activated for the redundant data.
  • the other output driver (driver) of the memory module 2 may be activated for the redundant data.
  • Memory module 2 then places the redundant data on the bus lines BL24 - BL31 or on the corresponding unused data lines D24 - D31 during the addressing phase.
  • ALE HIGH
  • the microprocessor 3 takes over the redundant data (check bits)
  • the memory module 2 adopts the address and switches over to the data output.
  • the corresponding time sequence of the signals is shown in FIG.
  • the generation of the redundant data, in particular the checksum (the so-called check bits) in the memory module 2 and the evaluation in the microprocessor 3 can after itself known methods are performed. For asynchronous data transfer between the memory module
  • redundant data can then comprise more than 1 bit and thus also require more than one data line for the transmission of redundant data.
  • the address of a first memory cell is transmitted to the memory module 2 by the processor 3. Starting from this first memory cell, data of this memory cell and several subsequent memory cells are sent to the microprocessor
  • the present invention can be used, for example, by determining check bits for the data to be transmitted in the individual data transmission phases and then checking the check bits in the following
  • Addressing phase are transmitted to the microprocessor 3 via the unused data lines.
  • 8 unused data lines CO-C7 are available during the addressing phase, a check bit for the data transmitted during a data transmission phase can be transmitted via each of these 8 data lines CO - C7.
  • check bits for up to eight data packets of eight consecutive data transmission phases can be transmitted in a single address phase.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé de communication entre au moins deux abonnés (2, 3) d'un système de communication par l'intermédiaire de plusieurs lignes de données (D0 - D31) d'un bus de données, dont certaines sont employées en tant que lignes d'adresses (A0 - A23) d'un bus d'adresses, les données et adresses étant transmises de façon multiplexée. L'invention vise à permettre une sécurisation simple et économique de la voie de transmission entre les abonnés (2, 3). A cet effet, des données redondantes sont transmises par l'intermédiaire d'au moins une ligne de données (D24 - D31) non utilisée en tant que ligne d'adresses lors de la transmission de l'adresse par l'intermédiaire de la ligne d'adresses (A0 - A23). Les données redondantes se présentent de préférence sous la forme de sommes de contrôle (bits de contrôle). Le procédé selon l'invention est de préférence employé pour la communication entre un microprocesseur (3) et un composant mémoire externe (2).
EP06763233A 2005-06-01 2006-05-23 Procede de communication entre au moins deux abonnes d'un systeme de communication Withdrawn EP1891535A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005024988A DE102005024988A1 (de) 2005-06-01 2005-06-01 Verfahren zur Kommunikation zwischen mindestens zwei Teilnehmern eines Kommunikationssystems
PCT/EP2006/062540 WO2006128810A2 (fr) 2005-06-01 2006-05-23 Procede de communication entre au moins deux abonnes d'un systeme de communication

Publications (1)

Publication Number Publication Date
EP1891535A2 true EP1891535A2 (fr) 2008-02-27

Family

ID=37057311

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06763233A Withdrawn EP1891535A2 (fr) 2005-06-01 2006-05-23 Procede de communication entre au moins deux abonnes d'un systeme de communication

Country Status (5)

Country Link
EP (1) EP1891535A2 (fr)
KR (1) KR20080013973A (fr)
CN (1) CN101189593A (fr)
DE (1) DE102005024988A1 (fr)
WO (1) WO2006128810A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8656082B2 (en) * 2008-08-05 2014-02-18 Micron Technology, Inc. Flexible and expandable memory architectures
DE102008049662B4 (de) * 2008-09-30 2012-07-12 Infineon Technologies Ag Verfahren und Vorrichtung zum Prüfen einer asynchronen Übertragung von Steuersignalen
DE102008064761B3 (de) * 2008-09-30 2013-06-13 Infineon Technologies Ag Verfahren und Vorrichtung zum Prüfen einer asynchronenÜbertragung von Steuersignalen
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
US5944806A (en) * 1997-09-26 1999-08-31 Hewlett-Packard Company Microprocessor with versatile addressing
TWI252406B (en) * 2001-11-06 2006-04-01 Mediatek Inc Memory access interface and access method for a microcontroller system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2006128810A2 *

Also Published As

Publication number Publication date
WO2006128810A2 (fr) 2006-12-07
DE102005024988A1 (de) 2006-12-07
WO2006128810A3 (fr) 2007-03-08
CN101189593A (zh) 2008-05-28
KR20080013973A (ko) 2008-02-13

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