EP1966800A2 - Techniques de detection de substitution pour memoires remanentes - Google Patents

Techniques de detection de substitution pour memoires remanentes

Info

Publication number
EP1966800A2
EP1966800A2 EP06848820A EP06848820A EP1966800A2 EP 1966800 A2 EP1966800 A2 EP 1966800A2 EP 06848820 A EP06848820 A EP 06848820A EP 06848820 A EP06848820 A EP 06848820A EP 1966800 A2 EP1966800 A2 EP 1966800A2
Authority
EP
European Patent Office
Prior art keywords
memory cells
bit line
sensing
states
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06848820A
Other languages
German (de)
English (en)
Inventor
Nima Mokhlesi
Jeffrey W. Lutze
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/320,917 external-priority patent/US7616481B2/en
Priority claimed from US11/321,996 external-priority patent/US7349264B2/en
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of EP1966800A2 publication Critical patent/EP1966800A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/565—Multilevel memory comprising elements in triple well structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Definitions

  • the peripheral circuitry supplies the reference voltages to the bit line comparators sequentially.
  • the reference values can all be available concurrently to a multiplexing circuit that supplies the different value, or the line supplying the reference values to the comparator can itself receive the various reference values in a time multiplexed manner.
  • Figure 6 provides Table 1 of example operating voltages of the NAND memory cell array of Figures 2-5;
  • select gate lines are electrically shorted together using one contact for each select gate, as in the STI embodiment the poly-1 layer is etched into isolated strips during the STI definition.
  • poly 1 strips are also etched, leaving the polyl gates residing above select gate channels as isolated conductors.
  • poly-2 layer will form a conducting line, connecting the individual poly-1 select gates to each other in order to form the select gate lines, which extend in a parallel direction to word lines.
  • Figure 8 illustrates threshold voltage distributions for the memory cell array 1 when each floating gate storage element stores two bits of data, namely four data states, in each memory cell (M).
  • the curve 33 represents a distribution of the threshold levels V T of the cells within the array 1 that are in the erased state (E data state), being negative threshold voltage levels.
  • Threshold voltage distributions 34 and 35 of memory cells storing A and B user data, respectively, are shown to be between V V A and V V B and between V V B and Vyc- A curve 36 shows the distribution of cells that have been programmed to the C data state, being the highest threshold voltage level set more than 2V and less than 4.5V of the read pass voltage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

La présente invention concerne un programme de détection de cellules de mémoire. Certaines cellules de mémoire sont déchargées à la terre par leurs canaux, puis la ligne de bits des cellules peut se charger après établissement d'un niveau de tension sur la source traditionnelle et d'un autre niveau de tension sur la grille de commande. La ligne de bits de la cellule de mémoire peut alors se charger alors jusqu'à ce que son niveau de tension soit suffisamment élevé pour interrompre la conduction de la mémoire. L'augmentation de la tension de la ligne de bits se produit à un rythme et à un niveau dépendant de l'état de données de la cellule, cette dernière se coupant lorsque la ligne de bits atteint un niveau suffisamment élevé pour que soit atteint un seuil de cellule de mémoire affectée par l'effet de substrat, seuil où le courant se coupe pratiquement. Dans un mode de réalisation particulier, des sous-opérations multiples de détection se déroulent, chacune avec un tension de commande de grille différente, mais avec détection d'états multiples à chaque opération avec charge par leur source de cellules précédemment déchargées.
EP06848820A 2005-12-28 2006-12-21 Techniques de detection de substitution pour memoires remanentes Withdrawn EP1966800A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/320,917 US7616481B2 (en) 2005-12-28 2005-12-28 Memories with alternate sensing techniques
US11/321,996 US7349264B2 (en) 2005-12-28 2005-12-28 Alternate sensing techniques for non-volatile memories
PCT/US2006/062513 WO2007076451A2 (fr) 2005-12-28 2006-12-21 Techniques de detection de substitution pour memoires remanentes

Publications (1)

Publication Number Publication Date
EP1966800A2 true EP1966800A2 (fr) 2008-09-10

Family

ID=38197637

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06848820A Withdrawn EP1966800A2 (fr) 2005-12-28 2006-12-21 Techniques de detection de substitution pour memoires remanentes

Country Status (5)

Country Link
EP (1) EP1966800A2 (fr)
JP (1) JP4568365B2 (fr)
KR (1) KR101357068B1 (fr)
TW (1) TWI323464B (fr)
WO (1) WO2007076451A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7349264B2 (en) 2005-12-28 2008-03-25 Sandisk Corporation Alternate sensing techniques for non-volatile memories
US7616481B2 (en) 2005-12-28 2009-11-10 Sandisk Corporation Memories with alternate sensing techniques
KR100923810B1 (ko) * 2007-02-22 2009-10-27 주식회사 하이닉스반도체 메모리 소자와 그 동작 방법
US8416624B2 (en) 2010-05-21 2013-04-09 SanDisk Technologies, Inc. Erase and programming techniques to reduce the widening of state distributions in non-volatile memories
WO2014142332A1 (fr) 2013-03-14 2014-09-18 Semiconductor Energy Laboratory Co., Ltd. Procédé d'attaque de dispositif à semi-conducteurs et dispositif à semi-conducteurs
US11049557B2 (en) * 2019-07-19 2021-06-29 Macronix International Co., Ltd. Leakage current compensation in crossbar array
KR102775482B1 (ko) * 2021-01-19 2025-02-28 양쯔 메모리 테크놀로지스 씨오., 엘티디. 반도체 메모리 디바이스

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602789A (en) * 1991-03-12 1997-02-11 Kabushiki Kaisha Toshiba Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller
JPH08249893A (ja) * 1995-03-07 1996-09-27 Toshiba Corp 半導体記憶装置
KR0169267B1 (ko) * 1993-09-21 1999-02-01 사토 후미오 불휘발성 반도체 기억장치
JP3476952B2 (ja) * 1994-03-15 2003-12-10 株式会社東芝 不揮発性半導体記憶装置
JP2697665B2 (ja) * 1995-03-31 1998-01-14 日本電気株式会社 半導体記憶装置及び半導体記憶装置からのデータ読み出し方法
US5687114A (en) * 1995-10-06 1997-11-11 Agate Semiconductor, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
JP4246831B2 (ja) * 1999-02-08 2009-04-02 株式会社東芝 半導体集積回路装置のデータ判別方法
US6259627B1 (en) * 2000-01-27 2001-07-10 Multi Level Memory Technology Read and write operations using constant row line voltage and variable column line load
US7630237B2 (en) * 2003-02-06 2009-12-08 Sandisk Corporation System and method for programming cells in non-volatile integrated memory devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007076451A2 *

Also Published As

Publication number Publication date
WO2007076451A2 (fr) 2007-07-05
WO2007076451A3 (fr) 2007-09-20
TW200741718A (en) 2007-11-01
JP4568365B2 (ja) 2010-10-27
KR20080096644A (ko) 2008-10-31
JP2009522706A (ja) 2009-06-11
KR101357068B1 (ko) 2014-02-03
TWI323464B (en) 2010-04-11

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