EP1991924A2 - Dispositif et procédé d'émission d'images différentes à au moins deux écrans - Google Patents

Dispositif et procédé d'émission d'images différentes à au moins deux écrans

Info

Publication number
EP1991924A2
EP1991924A2 EP07703803A EP07703803A EP1991924A2 EP 1991924 A2 EP1991924 A2 EP 1991924A2 EP 07703803 A EP07703803 A EP 07703803A EP 07703803 A EP07703803 A EP 07703803A EP 1991924 A2 EP1991924 A2 EP 1991924A2
Authority
EP
European Patent Office
Prior art keywords
image
image data
different images
processing unit
displays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP07703803A
Other languages
German (de)
English (en)
Inventor
Axel Kirschbaum
Markus Lindner
Simone Tonte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1991924A2 publication Critical patent/EP1991924A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Definitions

  • the invention is based on a device and a method according to the preamble of the independent claims.
  • a video control circuit for driving two displays is already known.
  • Image data are read from an image memory, wherein the image data are output via two circuit units alternately to a display controller for the first display and to a display controller for the second display.
  • further first-in, first-out storage units are provided, in which the transmitted image data can be buffered before being forwarded to the display controllers in each case.
  • the device according to the invention for outputting different images on at least two displays with the features of the independent claim has the advantage that at least two different images are generated from a video signal already suitable for direct display generation via a suitable processing unit, each of the different images a dedicated display unit is displayed.
  • a Display on several displays with only one display controller it is thus possible, a Display on several displays with only one display controller.
  • the number of mostly quite expensive display controller can be reduced.
  • the image line of the several different images may be output from the control unit in such a way that the multiple, different images in a suitably large display could also be displayed together simultaneously and adjacent.
  • the different images are therefore transmitted line by line in a form of the control unit to the processing unit, as if this would be a common, large
  • Act picture This simplifies both the interface and the data transmission from the control unit to the processing unit.
  • the at least two different images in the image memory adjacent.
  • the images can be easily read, in particular line by line.
  • the processing unit each with a memory for storing the image data of the different images for the at least two displays.
  • this memory makes it possible in each case to provide image data for the respective period for output, in which another image is transmitted to the processing unit for another display.
  • This makes it possible to transmit image data of the different images, in particular line by line, one after the other to the processing unit without interrupting a quasi-continuous image data output from the processing unit to the display unit.
  • a continuous, flicker-free image representation can be ensured on the multiple displays.
  • Storage can be realized in a particularly favorable manner in such a way that up to one image line is stored in each case.
  • a suitable control of the image data transmission for a continuous image data output to the displays is possible, on the other hand, the required storage space can be minimized.
  • an FPGA can be inexpensively designed, on the other hand it allows the image data to be processed almost parallel to be output to the various displays, and it can also be easily adapted by a manufacturer of the device to the requirements of the image data transmitted by the control unit as well as to the requirements of Ads that are connected to the processing unit.
  • the processing unit with an interface for specifying a frequency for the output of the image data to at least one of the display units.
  • the device according to the invention for outputting different images on at least two displays can also be adapted to another display which is connected to the device according to the invention.
  • the processing unit is preferably selected in each case in such a way that for outputting one image line of the different images approximately that time is available in each case in which one image line of all the different images is transmitted to the processing unit. This makes it possible to reduce a memory requirement in the processing unit in each case to an intermediate storage of a picture line. In addition, there is no interruption of the data flow from the processing unit to the different displays.
  • FIG. 1 shows a device according to the invention for outputting different images on at least two displays in a motor vehicle
  • FIG. 2 shows an exemplary embodiment of a device according to the invention for outputting different images on two displays in a schematic structure
  • FIG. 3 shows an example of image data consisting of pixel information of different images
  • FIG. 4 shows an exemplary embodiment of clock and synchronization signals between the control unit and the processing unit on the one hand and between the processing unit and, for example, two displays connected to it on the other hand,
  • FIGS. 5a, 5b and 5c show an exemplary embodiment for transmitting and reading image data in two memory devices of the processing unit.
  • the device according to the invention can be used for any applications in which different image data are also output on correspondingly different displays.
  • the use in a motor vehicle is advantageous since in a vehicle generally only a limited installation space, a limited electrical power and / or a limited computing capacity are available. Therefore, the present invention is explained below using the example of a use of the device according to the invention for outputting different images on two displays in a motor vehicle.
  • the pictures may differ in their picture content. This does not preclude that the images may have the same content depending on a desired output.
  • Picture content would be possible in principle.
  • the images here can be the same size, but can differ in a further embodiment, but also in their image format.
  • FIG. 1 schematically shows an instrument area 2 in front of a driver
  • a combination instrument 4 for displaying driving data of the motor vehicle 1 is arranged.
  • values such as the current vehicle speed can be displayed.
  • the combination instrument 4 has for display, in particular, a liquid crystal display, in which an image of the pointer display 5 is shown.
  • the combination instrument 4 is connected to a device for outputting images 6.
  • the head-up display 8 for example, a night-vision display of a street scene in front of the motor vehicle 1 can be displayed.
  • the center console display 9 for example, navigation instructions can be output.
  • the images outputted from the respective displays are generated in the device 6 for outputting the images in the manner according to the invention.
  • the operation of the device for image output is shown in detail in FIG.
  • an embodiment is shown in which two displays, for example, the combination instrument 4 and the projection unit 7, to the device for
  • FIG. 2 the device according to the invention for outputting different images 6 is shown schematically, the device 6 itself being delimited by a dashed line from the remaining units connected to it. So are a first
  • the arithmetic unit 20 determines those image information to be output on the displays 11 and 12.
  • the arithmetic unit 20 is connected, for example, to a camera 21, to a navigation device 22, to a data medium drive 23 and, preferably via a data bus 24, to sensors 25, 26 in the vehicle.
  • a video image is taken and transmitted to the arithmetic unit 20.
  • the sensors 25, 26 in particular driving data and / or
  • the Environment data of the vehicle supplied to the arithmetic unit 20 may be, for example, the engine speed, the current vehicle speed, the tank level, the cooling water temperature or the outside temperature.
  • the navigation device 22 transmits information about driving information to be output to the computing unit 20. From the disk drive 23 can in particular
  • Image information for output via the displays 11, 12 are read out.
  • Image information and corresponding commands for image output are transmitted from the arithmetic unit 20 to the device 6 for outputting the different images and in this case to the control unit 30 via a suitable interface 29.
  • the In this case transmitted information either represent only commands for image output or can also be image data, which can not be directly used without further processing for controlling one of the displays 11, 12, for example, a TV signal or image data in a compressed data format.
  • the control unit 30 has a graphics processor 31. The latter processes the raw image data supplied to it and writes image data to be output to a frame buffer 32.
  • the image memory 32 is constructed such that a first image 41 to be displayed in the first display 11 and a second image 42 to be displayed in the second display 12 are written in the image memory 32 together.
  • the image data of the two images 41, 42 are not mixed in the image memory 32 is written, but are each stored separately in the memory adjacent.
  • the image data are read from the image memory by a display controller 33 in the control unit 30.
  • the reading of the images 41, 42 is preferably carried out line by line.
  • the image data 41, 42 are preferably stored in the image memory 32 in such a way that they can also be correspondingly interpreted as a large image.
  • the display controller 33 converts the image data transmitted to it into such electronic signals that can be directly converted into an image by a display unit, e.g. VGA or RGB display signals.
  • the display controller 33 has a second data output 35 which, for example, has color lines, each of which is a color bit of the colors
  • Red, green and blue are assigned. Each pixel is assigned a red, green and blue value. It is thus possible, for example, to perform an 8-bit coding of the color values in each case, so that the color information for one pixel is transmitted over 24 individual lines which form the second data output 35.
  • the display controller 33 further comprises a first data output 34, which preferably also has three lines. Synchronization signals are transmitted via the first data output 34, in particular a vertical synchronization signal to the image beginning Synchronization, a horizontal synchronization signal for
  • the reading out of the image data and the outputting of the driving information from the display controller 33 is controlled by a working clock set by a timer 36 in the control unit 30. Via a clock line 37, this clock is also transmitted to the processing unit 50 and thus also controls the processing of the transmitted pixel information and synchronization signals.
  • the interface formed from the first and the second data output 34, 35 and the clock line could now be connected directly to a display, which would be sufficiently large, for example, to represent the images 41, 42 in their display area next to each other.
  • the output signal would be suitable for having the two images 41, 42 appear side by side on a correspondingly large display, provided that the output drive signals are coded in such a way that they could be read by the display accordingly. Further conversion of the data output by the display controller would not be necessary. In practice, data would thus be output by the display controller 33 for the immediate generation of a display representation corresponding to a juxtaposition of the two images 41, 42.
  • the image data converted into drive signals are not output directly to a display, but forwarded to a processing unit 50.
  • the synchronization signals output by the first data output 34 are forwarded to a computing unit 51 of the processing unit 50.
  • a working clock of the processing unit 50 is obtained from the clock of the transmitted image signals.
  • Clock unit 52 respectively generates the processing clock for image output to the first display 11 and the second display 12.
  • the frequency of the clock signals from the clock 36 is halved by the clock unit 52 and possibly still in phase 29obne.
  • each different Frequencies are given, which are stored in a memory 53 of the processing unit 50.
  • the memory 53 is connected to an interface 54.
  • the output parameters for the displays 11, 12 are stored. If the output parameters are to be changed because another display instead of one of the displays 11 or 12 is to be connected to the processing unit 50, then these changed parameters can be written into the memory 53 via the interface 54.
  • the synchronization signals transmitted by the first data output 34, and preferably the unchanged clock signal of the clock generator 36, are fed to the arithmetic unit 51 of the processing unit 50.
  • the pixel information output via the second data output 35 is fed to a switching unit 55, which is actuated by the arithmetic unit 51.
  • the pixel data output by the display controller 33 via the second data output 35 is written into a first memory 61 or a second memory 62.
  • the memories 61, 62 are embodied for example as a dual-ported RAM or as a first-in-first-out memory.
  • the first memory 61 is associated with the first display 11 and the second memory 62 with the second display 12.
  • the memories 61, 62 are preferably designed such that they do not comprise more than one image line, but at least half a picture line in each case of an image which is displayed in the display 11, 12 associated with the respective memory 61, 62.
  • the basic mode of operation of the image data output now takes place such that an image line consisting of a line of the first image 41 and the second image 42 is output pixel by pixel from the display controller 33. If the horizontal synchronization signal for the associated line has been received in the arithmetic unit 51 and the enable signal is also activated, the arithmetic unit 51 sets the switch 55 in such a way that the pixel data output via the second data output 35 are written into the first memory 61 , The arithmetic unit 51 now counts the pixels on the basis of the output from the clock 36 clock signals. In the memory 53, the number of pixels per line is stored in the first display 11.
  • the arithmetic unit 51 can determine from the number of clock signals received after activation of the enable signal, the transmission of pixel data to the first memory 61 is stopped and the switch 55 is switched such that the next transmitted pixel is already in the second memory 62 is written. Accordingly, the first part of the line, namely the part associated with the first image 41, is thus written into the first memory 61 and the second part of the line, namely the part associated with the second image 42, is written into the second memory 62. After the arithmetic unit 51 has determined that all pixels of the line of the second image 42 have been transmitted, writing to the second memory 62 is interrupted. After the arrival of the next horizontal synchronization signal output from the display controller 33, writing of the next image line to the memories 61, 62 is performed.
  • the control data transferred to the memories 61 have already been read out, so that the corresponding pixel information has been forwarded to the displays 11, 12 and has accordingly produced an indication of the pixels of the respective image line.
  • the reading out of the pixel information from the memories 61, 62 takes place in the case of identically sized displays, preferably at half the frequency with which the image information is transmitted from the control unit 30 to the processing unit 50.
  • the image information of a line in parallel processing are read from the memories 61, 62 respectively.
  • the readout process is explained with reference to FIGS. 5a, 5b and 5c.
  • FIG. 5a illustrates a state in which, as indicated by an arrow 70, approximately 80% of a first image line of the first image 41 has been written into the first memory 61. Compared with reading out the image data and outputting to the displays, writing is done at twice the speed. Therefore, only 40% of the information of the first image line of the first image 41 has been read out and displayed in the display 11 at this time. This is illustrated by the second arrow 71 in FIG. 5a.
  • FIG. 5b illustrates the situation at a time at which not only the first image line of the first image 41 but also half of the first image line of the second image 42 has been transmitted, the image information of the second image being transferred to the second memory 62 were enrolled.
  • the state of writing the image information is shown by the arrow 73.
  • 75% of the image information of the first image line has already been output, indicated by the arrow 73.
  • With the writing of the image information in the second memory 62 has also been started to read image information from the second memory 62 and bring in the second display 12 for display.
  • 25% of the image information of the first image line of the second image has already been read, indicated by the arrow 74.
  • FIG. 5c shows the situation at a later time, in which the first image line of the first and the second image has been completely transmitted and the beginning of the second image line of the first image has already been transferred to 20% and written into the first memory 61 ,
  • the status of the writing information is highlighted by the arrow 75.
  • the previously transmitted image information of the first line of the first image 41 can now be overwritten, since the first image line has already been completely output.
  • the first image line of the second image 42 has been completely written in the second memory 62.
  • the first image line of the second image 42 has already been read out to 60%, indicated by the arrow 77.
  • the image information of the first image 41 and the second image 42 are offset by half a line from one another to the first and the second display 11, respectively 12, but it is possible to continuously display the image data 41, 42 of the different images in the displays 11, 12.
  • FIG. 3 shows an exemplary embodiment of an image data signal which is output by the display controller 33 via the second data output 35.
  • color information is output to pixels of the first image 41, indicated by the bracket 81, with individual pixels 84 each containing pixel information of a respective line of the first image. This is followed, indicated by the bracket 82, pixel information of the second image 42 of the same line.
  • pseudo data so-called blanks 83, can be transmitted.
  • FIG. 4 shows an exemplary embodiment of clock signals and synchronization signals over time.
  • a clock signal, an enable signal and a horizontal synchronization signal are shown.
  • the signals generated by the control unit 30 are shown at the output of the display controller 33.
  • the signals generated by the processing unit 50 are shown at the output of the processing unit 50 to the second display 12.
  • the first representation 91 shows the clock signal 94, with which the image data are transmitted from the control unit 30 to the processing unit 50.
  • the clock signals with which image data are output from the processing unit 50 to the first display 11 and the second display 12, ie the clock signals 95, 96 in the representations 92 and 93, are generated by the clock unit 94 from the clock signal 94. It's halfway through
  • the response of the horizontal synchronization signal 97 during the time period 98 initiates in the representation 91 the subsequent transmission of the image data from the control unit 30 to the processing unit 50.
  • the subsequent time phase 99 in which the enable signal is set, the image data of one line of both the first image 41, and the second image 42 are transmitted.
  • the separation between the image data of the first image 41 and the second image 42 are indicated by a dashed line 100.
  • the pause phase is followed by a pause phase 101, in which no image data are transmitted and in which the enable signal is not set.
  • the arithmetic unit 51 generates an associated horizontal synchronization signal 103 to output the image data in the first display 11, which is output to the first display 11.
  • a corresponding enable signal which is likewise generated by the arithmetic unit 51 of the processing unit 50, is output to the first display 11.
  • the drive data for the pixels of the image line are also transmitted to the first display 11.
  • the image data is acquired during the period 106 in which the corresponding enable signal the second display 12 is output from the arithmetic unit 51, transmitted to the second display 12.
  • the transmission of the image data by the output of the enable signal 108 to the first display 11 is again initiated by a horizontal synchronization signal 107. To proceed with subsequent picture lines, the procedure continues accordingly.
  • FIG. 4 shows the transmission of a first image line. With the dashed lines 109 and 110, the corresponding enable signals are shown, which would precede the signals 104 and 106 in a continuous transmission, that is, in existing previous lines, respectively. After the transfer of all
  • Image lines of an image, not shown in the figure 4 vertical synchronization signal is respectively output to the displays 11, 12 and with the next image line, the next image is output, for example, starting with the first line.
  • the data transmission from the control unit 30 to the processing unit 50 takes place in one embodiment via an LVDS interface, in which voltage difference signals are transmitted. As a result, the electromagnetic radiation is minimized.
  • the processing unit 50 and the control unit 30 may in one embodiment be arranged on a common board in such a way that both the control unit
  • the processing unit 50 is each designed as a separate integrated circuit.
  • at least one of the displays 11, 12 is connected to the processing unit 50 via an LVDS interface.
  • the processing unit 50 is preferably designed as an FPGA (Field Programmable Gate Array).
  • the units realized in the processing unit 50 in FIG. 2 are thus not realized in discrete hardware, but are simulated by hardware of the FPGA of the FPGA.
  • the circuit shown in Figure 2 can also be realized by an ASIC. When implemented using an FPGA, however, the existing structure can easily be adapted to other display applications.
  • FIG. 2 shows by way of example the output of two different images on two displays.
  • a third display can be connected to the processing unit 50. Accordingly, other displays can be added, with the execution of the processing unit is adjusted accordingly.
  • the displays 11, 12 it is also possible for the displays 11, 12 to have, for example, different numbers of lines. If, for example, the display 12 extends only in a region 120, then only the image data corresponding to the region 121 of the second image 42 must be read out. Until the last line of the second image 42 is reached, the image data output is unchanged in accordance with the above example. Blanks are transmitted to the display until the next image is pending. The data transmission thus takes place in unchanged speed.
  • Image data to the respective displays also differ.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Studio Circuits (AREA)

Abstract

L'invention concerne un dispositif d'émission d'images différentes à au moins deux écrans, comportant une unité de commande destinée à lire des données d'images des images différentes à partir d'une mémoire d'images, à produire un signal de synchronisation horizontal et à émettre les données d'images et le signal de synchronisation horizontal; et une unité de traitement destinée à recevoir les données d'images et le signal de synchronisation horizontal, à produire d'autres signaux de synchronisation pour un écran respectif en fonction du signal de synchronisation fourni par l'unité de commande et d'un signal de cadence, et à répartir les données d'images transmises par l'unité de commande de telle manière que les données d'images des images différentes sont émises à un écran respectif.
EP07703803A 2006-02-27 2007-01-11 Dispositif et procédé d'émission d'images différentes à au moins deux écrans Ceased EP1991924A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006009010.1A DE102006009010B4 (de) 2006-02-27 2006-02-27 Vorrichtung und Verfahren zur Ausgabe von unterschiedlichen Bildern auf wenigstens zwei Anzeigen
PCT/EP2007/050260 WO2007098974A2 (fr) 2006-02-27 2007-01-11 Dispositif et procédé d'émission d'images différentes à au moins deux écrans

Publications (1)

Publication Number Publication Date
EP1991924A2 true EP1991924A2 (fr) 2008-11-19

Family

ID=38319880

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07703803A Ceased EP1991924A2 (fr) 2006-02-27 2007-01-11 Dispositif et procédé d'émission d'images différentes à au moins deux écrans

Country Status (5)

Country Link
US (1) US8477080B2 (fr)
EP (1) EP1991924A2 (fr)
CN (1) CN101390040B (fr)
DE (1) DE102006009010B4 (fr)
WO (1) WO2007098974A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044220A (zh) * 2009-10-09 2011-05-04 深圳市长运通集成电路设计有限公司 一种液晶显示装置的驱动方法
KR20120018539A (ko) * 2010-08-23 2012-03-05 삼성전자주식회사 복수 개의 표시 패널을 가지는 표시부 제어 방법 및 이를 기반으로 운용되는 휴대 단말기
US8467994B2 (en) * 2010-09-28 2013-06-18 General Electric Company Monitoring system and display for use in a monitoring system
US8704732B2 (en) 2010-09-29 2014-04-22 Qualcomm Incorporated Image synchronization for multiple displays
US9088750B2 (en) * 2012-07-25 2015-07-21 Omnivision Technologies, Inc. Apparatus and method for generating picture-in-picture (PIP) image
CN103092100B (zh) * 2013-01-10 2015-03-11 湘潭大学 一种同步采集数据和多画面显示的控制与显示装置
US9761028B2 (en) * 2013-02-13 2017-09-12 Konica Minolta Laboratory U.S.A., Inc. Generation of graphical effects
JP6881950B2 (ja) * 2016-11-10 2021-06-02 キヤノン株式会社 画像処理装置、画像処理装置の制御方法、及びプログラム
CN113838438B (zh) * 2021-09-01 2022-08-26 深圳市思坦科技有限公司 一种拼屏的数据处理方法、系统、电子装置及存储介质

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6215459B1 (en) 1993-10-01 2001-04-10 Cirrus Logic, Inc. Dual display video controller
WO1998025200A1 (fr) 1996-12-03 1998-06-11 Spea Software Gmbh Commande de deux unites de controle avec transmission des donnees d'affichage via un tampon fifo
CN1091899C (zh) * 1997-03-20 2002-10-02 明碁电脑股份有限公司 显示器模式校正方法及装置
US6188381B1 (en) * 1997-09-08 2001-02-13 Sarnoff Corporation Modular parallel-pipelined vision system for real-time video processing
US7221381B2 (en) * 2001-05-09 2007-05-22 Clairvoyante, Inc Methods and systems for sub-pixel rendering with gamma adjustment
US7451410B2 (en) * 2002-05-17 2008-11-11 Pixel Velocity Inc. Stackable motherboard and related sensor systems
JP2004233743A (ja) * 2003-01-31 2004-08-19 Renesas Technology Corp 表示駆動制御装置および表示装置を備えた電子機器
TWI280498B (en) * 2003-10-28 2007-05-01 Via Tech Inc Combined output driver
KR101001966B1 (ko) * 2004-01-07 2010-12-20 삼성전자주식회사 표시장치 및 이의 제조방법
US20060095617A1 (en) * 2004-10-30 2006-05-04 Tsung-Yung Hung Processing architecture for directly playing audio/video signal

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007098974A2 *

Also Published As

Publication number Publication date
CN101390040B (zh) 2012-05-30
DE102006009010A1 (de) 2007-08-30
WO2007098974A2 (fr) 2007-09-07
DE102006009010B4 (de) 2024-06-20
US8477080B2 (en) 2013-07-02
WO2007098974A3 (fr) 2008-04-17
US20100194666A1 (en) 2010-08-05
CN101390040A (zh) 2009-03-18

Similar Documents

Publication Publication Date Title
EP1991924A2 (fr) Dispositif et procédé d'émission d'images différentes à au moins deux écrans
DE10212911B4 (de) Elektroendoskopsystem mit Elektroendoskopen mit verschiedenen Pixelanzahlen
DE68928773T2 (de) Verfahren zum senkrechten Filtern bei rasterabgetasteten Anzeigevorrichtungen
DE69637276T2 (de) Bildanzeigegerät
DE3878504T2 (de) Vorrichtung zur verarbeitung eines videosignals.
DE69225777T2 (de) Videoanzeigeeinstellung und Menüsystem auf Schirm
DE69518778T2 (de) Multimedia graphische Systeme mit andauernd hoher Taktrate
DE69421040T2 (de) Signalverarbeitungsvorrichtung für eine Flüssigkristallanzeigevorrichtung
DE69625774T2 (de) Vorrichtung zur Anzeige von mehreren komprimierten Bildern
DE102011007518A1 (de) Anzeigevorrichtung für Kraftfahrzeuge
EP1368801B1 (fr) Procede et dispositif d'amelioration de la resolution en niveaux de gris d'un dispositif d'affichage d'images a modulation d'impulsions en largeur
EP0777393A2 (fr) Procédé et appareil pour la superposition d'images vidéos stéréoscopiques
DE19962730C2 (de) Videosignalverarbeitungssystem bzw. Videosignalverarbeitungsverfahren
EP0603226B1 (fr) Procede et dispositif de commande d'affichages matriciels
DE102004020541B4 (de) Anordnung und Verfahren zur Ansteuerung mehrerer Grafikdisplays
DE69207447T2 (de) Anzeigegerät
EP1922871B1 (fr) Transmission d'informations dans le signal video d'un systeme de camera
DE102020129908B4 (de) Indirektes Sichtsystem und Verfahren zum Anpassen einer Bildwiederholungsrate
DE10159469B4 (de) Verfahren zur Anzeige und Anzeigevorrichtung
DE69011935T2 (de) Bildwiedergabevorrichtung.
EP1908286A1 (fr) Procede de transmission analogique d'un signal video
DE69901660T2 (de) Verfahren und Vorrichtung zur Übertragung von Bildinformationen
EP1680929A1 (fr) Commande de stereoprojection
EP4087751A1 (fr) Procédé et dispositif pour fournir un affichage de remplacement pour une unité d'affichage
WO1999049660A1 (fr) Procede permettant de sortir des donnees-image reçues

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK RS

17P Request for examination filed

Effective date: 20081017

RBV Designated contracting states (corrected)

Designated state(s): DE ES FR GB IT

17Q First examination report despatched

Effective date: 20090218

RBV Designated contracting states (corrected)

Designated state(s): DE ES FR GB IT

DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: DE

Ref legal event code: R003

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20140505