EP1993127A3 - Verfahren zur Herstellung eines SOI-Substrats und Verfahren zur Herstellung einer Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung eines SOI-Substrats und Verfahren zur Herstellung einer Halbleitervorrichtung Download PDF

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Publication number
EP1993127A3
EP1993127A3 EP08005687A EP08005687A EP1993127A3 EP 1993127 A3 EP1993127 A3 EP 1993127A3 EP 08005687 A EP08005687 A EP 08005687A EP 08005687 A EP08005687 A EP 08005687A EP 1993127 A3 EP1993127 A3 EP 1993127A3
Authority
EP
European Patent Office
Prior art keywords
substrate
semiconductor layer
manufacturing
base substrate
thin semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP08005687A
Other languages
English (en)
French (fr)
Other versions
EP1993127B1 (de
EP1993127A2 (de
Inventor
Hidakazu Miyairi
Akihisa Shimomura
Tatsuya Mizoi
Eiji Higa
Yoji Nagano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of EP1993127A2 publication Critical patent/EP1993127A2/de
Publication of EP1993127A3 publication Critical patent/EP1993127A3/de
Application granted granted Critical
Publication of EP1993127B1 publication Critical patent/EP1993127B1/de
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01961—Chemical or physical modification, e.g. by sintering or anodisation

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP08005687.2A 2007-05-18 2008-03-26 Verfahren zur Herstellung eines SOI-Substrats Not-in-force EP1993127B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007132380 2007-05-18

Publications (3)

Publication Number Publication Date
EP1993127A2 EP1993127A2 (de) 2008-11-19
EP1993127A3 true EP1993127A3 (de) 2010-06-23
EP1993127B1 EP1993127B1 (de) 2013-04-24

Family

ID=39689453

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08005687.2A Not-in-force EP1993127B1 (de) 2007-05-18 2008-03-26 Verfahren zur Herstellung eines SOI-Substrats

Country Status (6)

Country Link
US (2) US7820524B2 (de)
EP (1) EP1993127B1 (de)
JP (2) JP2009004739A (de)
KR (1) KR101434934B1 (de)
CN (1) CN101308782B (de)
TW (1) TWI478280B (de)

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JP2009004739A (ja) 2009-01-08
EP1993127B1 (de) 2013-04-24
US20080286952A1 (en) 2008-11-20
JP2014017513A (ja) 2014-01-30
KR101434934B1 (ko) 2014-08-27
US7820524B2 (en) 2010-10-26
KR20080101658A (ko) 2008-11-21
JP5849077B2 (ja) 2016-01-27
CN101308782A (zh) 2008-11-19
US8895407B2 (en) 2014-11-25
EP1993127A2 (de) 2008-11-19
TWI478280B (zh) 2015-03-21
CN101308782B (zh) 2012-10-17
TW200849465A (en) 2008-12-16

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