EP2016621A1 - Dispositif à semi-conducteur présentant une configuration de semi-conducteur sur isolant et un super-réseau et procédés associés - Google Patents

Dispositif à semi-conducteur présentant une configuration de semi-conducteur sur isolant et un super-réseau et procédés associés

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Publication number
EP2016621A1
EP2016621A1 EP07761837A EP07761837A EP2016621A1 EP 2016621 A1 EP2016621 A1 EP 2016621A1 EP 07761837 A EP07761837 A EP 07761837A EP 07761837 A EP07761837 A EP 07761837A EP 2016621 A1 EP2016621 A1 EP 2016621A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
layer
superlattice
energy band
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07761837A
Other languages
German (de)
English (en)
Inventor
Scott A. Kreps
Kalipatnam Vivek Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atomera Inc
Original Assignee
Mears Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/381,850 external-priority patent/US20060243964A1/en
Priority claimed from US11/381,835 external-priority patent/US7586116B2/en
Application filed by Mears Technologies Inc filed Critical Mears Technologies Inc
Publication of EP2016621A1 publication Critical patent/EP2016621A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

  • the present invention relates to the field of semiconductors, and, more particularly, to semiconductors having enhanced properties based upon energy band engineering and associated methods.
  • U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensiie strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
  • U.S. Patent No. 4,937,204 to lshibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxtaliy grown. The direction of main current flow is perpendicular to the layers of the superiattice.
  • U.S. Patent No. 5,357,119 to Wang et ai. discloses a Si-Ge short period superiattice with higher mobility achieved by reducing alioy scattering in the superiattice.
  • U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutional ⁇ present in the silicon lattice at a percentage that places the channel layer under tensile stress.
  • U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO ⁇ /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
  • An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor- atomic superiattice (SAS) of silicon and oxygen.
  • the Si/O superiattice is disclosed as useful in a silicon quantum and light-emitting devices.
  • a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
  • the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
  • the insulating iayer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.
  • APBG Aperiodic Photonic Band-Gap
  • material parameters for example, the location of band minima, effective mass, etc, can be tailored to yield new aperiodic materials with desirable band-structure characteristics.
  • Other parameters such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.
  • a semiconductor device such as a silicon-on- insuiator (SOI) device, having relatively high charge carrier mobility and related methods.
  • SOI silicon-on- insuiator
  • a semiconductor device which may include a substrate, an insulating layer adjacent the substrate, and a superiattice adjacent a face of the insulating layer opposite the substrate.
  • the superiattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon.
  • the energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  • the semiconductor device may further include a semiconductor layer between the insulating layer and the superlattice.
  • source and drain regions may be on the semiconductor layer, and the superlattice may extend between the source and drain regions.
  • a gate may aiso overly the superlattice, and a contact layer may be on at least one of the source and drain regions.
  • the substrate may comprise silicon
  • the insulating layer may comprise silicon oxide.
  • the superiattice may have a common energy band structure therein, and it may also have a higher charge carrier mobility than would otherwise be present without the energy band-modifying layer.
  • Each base semiconductor portion may comprise at least one of silicon and germanium, and each energy band-modifying layer may comprise oxygen. Further, each energy band-modifying layer may be a single monolayer thick, and each base semiconductor portion may be less than eight monolayers thick.
  • the superlattice may further have a substantially direct energy bandgap, and it may also include a base semiconductor cap layer on an uppermost group of layers.
  • all of the base semiconductor portions may be a same number of monolayers thick.
  • at least some of the base semiconductor portions may be a different number of monolayers thick.
  • each energy band- modifying layer may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example.
  • Another aspect of the invention is dirfected to a method for making a semiconductor device which may include forming an insulating layer adjacent a substrate, and providing a superlattice adjacent a face of the insulating layer opposite the substrate.
  • the superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon.
  • the energy band-modifying layer may include at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  • the method may further include providing a semiconductor layer between the insulating layer and the superlattice.
  • the source and drain regions may be formed on the semiconductor layer, and the superlattice may extend between the source and drain regions.
  • a gate may also be formed overlying the superlattice, and a contact layer may be formed on at least one of the source and drain regions.
  • the substrate may comprise silicon, and the insulating layer may comprise silicon oxide.
  • the substrate may also comprise germanium, for example.
  • FIG. 1 is schematic cross-sectional view of a semiconductor device in accordance with the present invention.
  • FIG. 2 is a greatly enlarged schematic cross-sectionai view of the superlattice as shown in FIG. 1.
  • FIG. 3 is a perspective schematic atomic diagram of a portion of the superiattice shown in FlG. 1.
  • FIG. 4 is a greatly enlarged schematic cross-sectionai view of another embodiment of a superlattice that may be used in the device of FIG. 1.
  • FIG. 5A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-3.
  • FIG. 5B is a graph of the calculated band structure from the Z point for both buik silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-3.
  • FIGS. 6A-6C are a series of schematic cross-sectional diagrams illustrating a method for making the semiconductor device of FIG. 1. Detailed Description of the Preferred Embodiments [0025]The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
  • the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices.
  • f is the Fermi-Dirac distribution
  • Ep is the Fermi energy
  • T is the temperature
  • E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
  • the indices i and j refer to cartesian coordinates x, y and z
  • the integrals are taken over the Briiiouin zone (B.Z.)
  • the summations are taken over bands with energies above and crizow the Fermi energy for electrons and holes respectively.
  • Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
  • the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the materia!, such as typically for a preferred direction of charge carrier transport.
  • the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
  • the conductivity effective mass for eiectrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
  • One such example would be a superiattice 25 material for a channel region in a semiconductor device.
  • a silicon-on-insu!ator (SOI) MOSFET 20 including the superiattice 25 in accordance with the invention is now first described with reference to FIG. 1.
  • SOI silicon-on-insu!ator
  • the iilustrated SOi MOSFET 20 includes a silicon substrate 21, an insulating layer (i.e., silicon oxide) 37 on the substrate, and a semiconductor (i.e., silicon) layer 39 on a face of the insulating layer opposite the substrate.
  • a semiconductor layer 39 on a face of the insulating layer opposite the substrate.
  • Lightly doped source/drain extension regions 22, 23 and more heavily doped source/drain regions 26 » 27 are formed in the semiconductor layer 39, as shown, and a channel region extending between the lightly doped source/drain extension regions is provided by the superlattice 25.
  • Source/drain suicide layers 30, 31 and source/drain contacts 32, 33 overlie the source/drain regions, as wiil be appreciated by those skilled in the art.
  • a gate 35 illustratively includes a gate insulating layer 36 ⁇ e.g., silicon oxide) adjacent the channel provided by the superSattice 25, and a gate electrode layer 38 (e.g., silicon) on the gate insulating layer. Sidewall spacers 40, 41 are also provided in the illustrated SOI MOSFET 20, as well as a suicide layer 34 on the gate electrode layer 36.
  • the insulating layer 37 and the gate insulating layer 36 are shown with stippling in the drawings.
  • the superlattice 25 is shown with dashes in regions where dopant from the source/drain implantations is present. It should be noted that other source/drain and gate configurations may be also used.
  • the insulating layer 37 of the above-described SOI device advantageously provides reduced capacitance adjacent the source and drain regions 26, 27, thereby reducing switching time and providing faster device operation, for example.
  • the insulating layer 37 may be used for the insulating layer 37, such as glass or sapphire, for example.
  • the substrate 21 and semiconductor layer 39 may comprise other semiconductor materials, such as germanium, for example.
  • the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular iayer deposition.
  • the superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 2.
  • Each group of layers 45a-45n of the superiattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band- modifying layer 50 thereon.
  • the energy band-modifying layers 50 are indicated by stippling in FIG. 2 for clarity of illustration.
  • the energy-band modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. In other embodiments, more than one such monolayer may be possible.
  • non- semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as semiconductor, may not necessariiy exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
  • energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction.
  • the band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure.
  • the semiconductor device described above enjoys a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
  • the superiattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example, as described in further detail below.
  • the source/drain regions 22, 23 and gate 35 of the MOSFET 20 may be considered as regions for causing the transport of charge carriers through the superiattice in a parallel direction relative to the layers of the stacked groups 45a ⁇ 45n. Other such regions are also contemplated by the present invention.
  • the superiattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n.
  • the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
  • the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
  • Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group IH-V semiconductors, and Group N-Vl semiconductors.
  • Group IV semiconductors also includes Group !V-IV semiconductors, as will be appreciated by those skilled in the art.
  • the base semiconductor may comprise at least one of silicon and germanium, for example.
  • Each energy band-modifying layer 50 may comprise a non- semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example.
  • the non-semiconductor is aiso desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
  • the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art.
  • the base semiconductor may comprise at least one of silicon and germanium, for example.
  • the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not ail of the possible sites are occupied. For example, with particular reference to the atomic diagram of FIG. 3, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied.
  • this one half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a fiat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0045] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used.
  • semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and impiemented, as will be appreciated by those skilled in the art.
  • a superlattice such as the Si/O superlattice
  • the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages.
  • the 4/1 repeating structure shown in FIGS. 2 and 3, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction.
  • the calculated conductivity effective mass for electrons is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46.
  • the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superiattice resulting in a ratio of 0.44.
  • the lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
  • the superlattice 25 may further comprise at least one type of conductivity dopant therein as will also be appreciated by those skilled in the art.
  • ail of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick, In still other embodiments, ail of the base semiconductor portions may be a different number of monolayers thick. [0051] in FIGS. 5A-5C band structures calculated using Density
  • DFT Functional Theory
  • FIG. 5A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice 25 as shown in FIGS. 1-3 (represented by dotted lines).
  • the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
  • the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
  • the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.
  • St can be seen that the conduction band minimum for the 4/1
  • Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
  • Si bulk silicon
  • the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
  • the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
  • FIG. 5B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superiattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the
  • FIG. 5C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superiattice 25' of FIG. 4 (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
  • the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicants to further theorize that the 5/1/3/1 superiattice 25' should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.
  • a method for making the SOI MOSFET 20 begins with providing a first semiconductor (e.g., silicon) substrate 61.
  • the substrate 61 may be an eight-inch wafer 21 of lightly doped P-type or N-type single crystal silicon with ⁇ 100> orientation, although other suitable substrates may also be used.
  • a base undoped silicon layer 152 is epitaxially formed across the upper surface of the substrate 61.
  • the layer 152 may include a plurality of base semiconductor monolayers 46 to define a cap layer for the superiattice 25, which is then formed thereon. St should be noted that the superiattice here is being constructed in the reverse order as described above, since it will be "flipped" when combined with the SOI substrate 21, as discussed further below.
  • the superiattice 25 material is deposited using atomic layer deposition, as will be appreciated by those skilled in the art. It should be noted that in some embodiments the superlattice 25 material may be selectively deposited in those regions where channels are to be formed, rather than across the entire substrate 61, as will also be appreciated by those skilled in the art.
  • the epitaxial silicon layer 39 is formed on the superlattice 25, and this layer is preferably undoped or lightly doped. The thickness of the layer 39 should be appropriate for either a partially or fully depleted device, as the case may be. Planarization may be used as necessary after forming the above layers to achieve the desired thickness and surface characteristics.
  • the substrate 61 is implanted with ions (e.g., hydrogen ions), as illustrated with the downward pointing arrows in FIG. 6A, to form a separation layer 60 in the first substrate.
  • ions e.g., hydrogen ions
  • the separation layer 60 is generaliy parallel to the upper surface of the substrate 61 and is located at a position corresponding to the mean penetration depth of the ion implantation, as will be appreciated by those skilled in the art.
  • the implantation energy is chosen to give the desired overall layer thickness and the appropriate cap layer thickness in the finished device 20.
  • the insulating layer 37 is formed on a second substrate 21 , which may be similar to the substrate 61 discussed above, using conventional semiconductor processing techniques. While shown side by side for reference in FIG. 6A, it should be noted that the two substrates 21, 61 need not be processed simultaneously.
  • the substrate 61 is then flipped and the layer 39 is bonded to the insulating layer 37 as shown in FIG. 6B. Once bonded, a thermal cycle is performed to fracture and cleave the first substrate 61 at the separation layer 60, as will be appreciated by those skilled in the art. The separated substrate 61 may then be discarded, and the substrate 21 becomes the base substrate for the device 20,
  • a thin gate oxide 36 is deposited, and steps of poly deposition, patterning, and etching are performed.
  • Poly deposition refers to low pressure chemical vapor deposition (LPCVD) of silicon onto an oxide (hence it forms a polycrystal ⁇ ne material).
  • the step includes doping with P+ or As- to make it conducting, and the layer may be around 250 nm thick, for example.
  • the pattern step may include performing a spinning photoresist, baking, exposure to light (i.e., a photolithography step), and developing the resist.
  • the pattern is then transferred to another layer (oxide or nitride) which acts as an etch mask during the etch step.
  • the etch step typically is a plasma etch (anisotropic, dry etch) that is material selective (e.g., etches silicon ten times faster than oxide) and transfers the lithography pattern into the materia! of interest.
  • the sidewall spacers 40, 41 may be formed after patterning of the gate stack, as will be appreciated by those skilled in the art.
  • the gate 35 and sidewall spacers 40, 41 may be used as an etch mask to remove the superlattice 25 material and portions of the substrate 21 in the regions where the source and drain are to be formed, as will be appreciated by those skilied in the art. As may be seen in FIG. 1 , this step forms an underlying step portion of the silicon layer 39 beneath the superlattice 25.
  • the superlattice 25 materia! may be etched in a similar fashion to that described above for the gate 35. However, it should be noted that with the non-semiconductor present in the superlattice 25, e.g., oxygen, the superlattice may be more easily etched using an etchant formulated for oxides rather than silicon. Of course, the appropriate etch for a given implementation will vary based upon the structure and materials used for the superlattice 25 and substrate 21, as will be appreciated by those of skill in the art.
  • the lightly doped source and drain ("LDD") extensions 22, 23 are formed using n-type or p-type LDD implantation, annealing, and cleaning.
  • An anneal step may be used after the LDD implantation, but depending on the specific process, it may be omitted.
  • the clean step is a chemical etch to remove metals and organics prior to depositing an oxide layer, it should be noted that when the source and drain regions are said to be formed "on" the semiconductor layer 39 herein, this is meant to include implantations in the semiconductor layer as well as raised source/drain regions which may be formed on top of the semiconductor layer, as will be appreciated by those skilled in the art.
  • the source and drain 26, 27 implants, an SiO. 2 mask is deposited and etched back. N-type or p-type ion implantation is used to form the source and drain regions 26, 27. The structure is then annealed and cleaned. Self-aligned suicide formation may then be performed to form the suicide layers 30, 31, and 34, and the source/drain contacts 32, 33, are formed to provide the final SOI MOSFET device 20 illustrated in FiG. 1.
  • the suicide formation is also known as salicidation.
  • the salicidation process includes metal deposition (e.g. Ti), nitrogen annealing, metal etching, and a second annealing.
  • the foregoing is, of course, but one example of a process and device in which the present invention may be used, and those of skill in the art will understand its application and use in many other processes and devices.
  • the structures of the present invention may be formed on a portion of a wafer or across substantially all of a wafer.
  • the use of an atomic layer deposition tool may also not be needed for forming the superlattice 25 in some embodiments.
  • the monolayers may be formed using a CVD tool with process conditions compatible with control of monolayers, as will be appreciated by those skilled in the art.
  • insulator-on-substrate device that may be produced using the above described techniques is a memory device.
  • Other potential insulator-on- substrate devices include optica! devices.

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Abstract

L'invention concerne un dispositif à semi-conducteur pouvant comporter un substrat semi-conducteur sur isolant (SOI), une couche isolante jouxtant le substrat, et une couche à semi-conducteur jouxtant une face de la couche isolante à l'opposé du substrat. Le dispositif peut également comporter des zones source et de drain sur la couche à semi-conducteur, un super-réseau jouxtant la couche à semi-conducteur et s'étendant entre les zones source et de drain pour définir un canal, et une grille recouvrant le super-réseau. Ledit super-réseau peut comporter plusieurs groupes de couches empilés, chaque groupe de couches comportant empilées plusieurs monocouches à semi-conducteurs de base définissant une partie à semi-conducteur de base et, au-dessus de celle-ci, une couche modifiant la bande d'énergie. Ladite couche modifiant la bande d'énergie peut comporter au moins une monocouche non semi-conductrice confinée dans un réseau cristallin de parties à semi-conducteurs de base contiguës. Le super-réseau peut contenir du germanium.
EP07761837A 2006-05-05 2007-05-03 Dispositif à semi-conducteur présentant une configuration de semi-conducteur sur isolant et un super-réseau et procédés associés Withdrawn EP2016621A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/381,850 US20060243964A1 (en) 2003-06-26 2006-05-05 Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US11/381,835 US7586116B2 (en) 2003-06-26 2006-05-05 Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
PCT/US2007/068159 WO2007131119A1 (fr) 2006-05-05 2007-05-03 Dispositif à semi-conducteur présentant une configuration de semi-conducteur sur isolant et un super-réseau et procédés associés

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EP2016621A1 true EP2016621A1 (fr) 2009-01-21

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EP07761837A Withdrawn EP2016621A1 (fr) 2006-05-05 2007-05-03 Dispositif à semi-conducteur présentant une configuration de semi-conducteur sur isolant et un super-réseau et procédés associés

Country Status (6)

Country Link
EP (1) EP2016621A1 (fr)
JP (1) JP2009536464A (fr)
AU (1) AU2007247955A1 (fr)
CA (1) CA2650489A1 (fr)
TW (1) TW200807708A (fr)
WO (1) WO2007131119A1 (fr)

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Publication number Priority date Publication date Assignee Title
US5241197A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
US7351993B2 (en) * 2000-08-08 2008-04-01 Translucent Photonics, Inc. Rare earth-oxides, rare earth-nitrides, rare earth-phosphides and ternary alloys with silicon
US6410371B1 (en) * 2001-02-26 2002-06-25 Advanced Micro Devices, Inc. Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
JP2002314089A (ja) * 2001-04-16 2002-10-25 Matsushita Electric Ind Co Ltd 半導体装置
WO2005018005A1 (fr) * 2003-06-26 2005-02-24 Rj Mears, Llc Dispositif a semi-conducteur comprenant un transistor mosfet pourvu d'un super-reseau concu sous forme de bande
US6830964B1 (en) * 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7029964B2 (en) * 2003-11-13 2006-04-18 International Business Machines Corporation Method of manufacturing a strained silicon on a SiGe on SOI substrate
US7247546B2 (en) * 2004-08-05 2007-07-24 International Business Machines Corporation Method of forming strained silicon materials with improved thermal conductivity

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007131119A1 *

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Publication number Publication date
TW200807708A (en) 2008-02-01
AU2007247955A1 (en) 2007-11-15
JP2009536464A (ja) 2009-10-08
WO2007131119A1 (fr) 2007-11-15
CA2650489A1 (fr) 2007-11-15

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