EP2051929A1 - Procédé de fabrication de structures mems - Google Patents

Procédé de fabrication de structures mems

Info

Publication number
EP2051929A1
EP2051929A1 EP07729426A EP07729426A EP2051929A1 EP 2051929 A1 EP2051929 A1 EP 2051929A1 EP 07729426 A EP07729426 A EP 07729426A EP 07729426 A EP07729426 A EP 07729426A EP 2051929 A1 EP2051929 A1 EP 2051929A1
Authority
EP
European Patent Office
Prior art keywords
layer
sacrificial
silicon
monocrystalline
structuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07729426A
Other languages
German (de)
English (en)
Inventor
Andreas Scheurle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2051929A1 publication Critical patent/EP2051929A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
    • B81C1/00714—Treatment for improving the physical properties not provided for in groups B81C1/0065 - B81C1/00706
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0102—Surface micromachining
    • B81C2201/0105—Sacrificial layer
    • B81C2201/0109—Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0176—Chemical vapour Deposition
    • B81C2201/0177—Epitaxy, i.e. homo-epitaxy, hetero-epitaxy, GaAs-epitaxy

Definitions

  • the invention relates to a method for the production of MEMS structures (Micro Electro Mechanical Systems) based on silicon, preferably multi-layer depositable MEMS structures.
  • MEMS structures Micro Electro Mechanical Systems
  • silicon preferably multi-layer depositable MEMS structures.
  • such structures essentially comprise a conductive functional layer containing fixed and movable regions. Movable regions are usually fixed during production by a so-called sacrificial layer, which is selectively removed at the end of the production process by methods known from micromechanical or semiconductor technology.
  • Another disadvantage of said methods is the generally quite sensitive compensation of stress gradients by the driving in of the dopants.
  • the success of this compensation depends sensitively on the avoidance of later thermal overloads of the doped layers, which is why, when a desired integration of a plurality of sensor elements into a chip is required, the sensor elements must be displaced laterally in order to thermally decouple them during manufacture. This increases the space requirements and costs of the MEMS structure and the finished component.
  • the object of the invention is to provide a method which allows the production of complex MEMS structures with high efficiency in a small space and avoids the disadvantages of the prior art.
  • the inventive method is based on the deposition of largely monocrystalline functional and sacrificial layers. Obviously, the associated omission of the grain boundaries effectively impedes the diffusion of germanium. This makes it possible to use sacrificial layers of silicon germanium without having to apply an additional barrier to germanium in order to limit its diffusion.
  • the method is used to produce MEMS structures with at least one functional layer made of silicon, which contains structures which are released by removing a sacrificial layer.
  • at least one sacrificial layer and at least one functional layer are deposited such that they grow up monocrystalline, wherein the sacrificial layer consists of a silicon-germanium mixed layer.
  • a plurality of functional layers and sacrificial layers are deposited on top of each other, wherein all functional layers and all sacrificial layers are deposited in such a way that they grow up monocrystalline, and the sacrificial layers each consist of a silicon-germanium mixed layer.
  • the multiple separation is possible because of the relatively high Growth rates claimed the heating of the entire assembly only a relatively short period in which a diffusion of germanium, which is also hampered by lack of grain boundaries, can be neglected.
  • the removal of the sacrificial material by CIF3 gas phase cats takes place.
  • process parameters are advantageously adjusted at least temporarily so that the epitaxial growth takes place at a growth rate of at least 3 ⁇ m / min.
  • the change between silicon layers and silicon-germanium mixed layers facilitates by monitoring the plasma emission and / or species detectable by mass spectroscopy the avoidance of false etching depths and thus the occurrence of faulty structuring.
  • the steps of depositing and structuring a sacrificial layer and depositing and structuring a functional layer can be repeated several times before completion with a capping layer.
  • FIG. 2 shows an SOI wafer with a structured starting layer
  • FIG. 3 shows an SOI wafer with an additional first structured sacrificial layer
  • 4 shows an SOI wafer with a first structured functional layer
  • 5 shows an SOI wafer with a second structured functional layer
  • FIG. 6 shows an SOI wafer with a closed cap layer
  • FIG. 7 shows an SOI wafer with a completely exposed functional structure
  • FIG. and FIG. 8 shows a SOI wafer with a sealed and contacted MEMS structure.
  • FIG. 1 shows an unstructured SOI wafer as starting material for the production of multi-layer depositable
  • Such a wafer consists of a thick silicon layer 1, which also serves as a mechanical carrier, on which a silicon oxide layer is deposited as the insulating layer 2.
  • a silicon oxide layer is deposited as the insulating layer 2.
  • the insulating layer 2 On the insulating layer 2 there is a monocrystalline starting layer 3 made of silicon.
  • SOI wafers it is possible to produce by individual structuring individual electrically isolated regions, which can serve as a starting layer for later epitaxial growth of other layers.
  • FIG. 2 shows an SOI wafer with a structured starting layer 3.
  • the structuring takes place by means of an etching step. Vorlie- In addition, several regions of the starting layer 3 are electrically insulated from one another, since the etched trenches 4 extend to the insulating layer 2. The individual areas of the starting layer 3 thus exposed form the bases of the later MEMS structures.
  • the silicon layer must have a certain conductance value for this purpose.
  • the conductance can be adjusted by doping the silicon.
  • the conductance of the start layer 3 is maintained by in-situ doping during the deposition of further layers. Subsequent doping and thermal overload of individual structural areas can be avoided.
  • the starting layer 3 is structured from monocrystalline silicon
  • sacrificial material is deposited in the form of monocrystalline silicon germanium.
  • the area of the silicon regions remaining after the structuring of the starting layer 3 serves for the growth of an initially closed sacrificial layer 5 as a starting layer in order to allow epitaxial growth.
  • CMP step chemical mechanical polishing
  • the polished sacrificial layer 5 is then patterned by an etching step in order to produce contact holes 6 to individual regions of the starting layer 3, which can serve as a base or conductor track.
  • the plasma emission can be monitored during this process step. Disappear emission lines, the one Indicate the presence of germanium, a structuring of the sacrificial layer 5 can be read and the etching process is stopped.
  • FIG. 4 shows an SOI wafer with a first structured functional layer 7 of monocrystalline silicon. This is first epitaxially deposited on the sacrificial layer 5 and then patterned in a trench process. Since there is no layer that causes an etch stop and too much overcutting could cause unwanted connections between conductive areas, the etch depth should always be monitored in this process step. This can be done, for example, by a mass spectrometer, to which the exhaust gases of the trencher are supplied. If germanium is detected, the etching process is stopped. As a result of this step, there is a structured functional layer 7, the regions of which partially protrude on the sacrificial layer and are partially in electrically conductive connection with regions of the starting layer 3.
  • the steps of the deposition and structuring of a sacrificial layer which can be read in FIGS. 3 and 4 and the deposition and structuring of a functional layer can be repeated several times in order to place a plurality of structures one above the other until a desired functional structure is formed.
  • acceleration sensors can be superimposed on a chip whose detection directions are offset by 90 °, which leads to two-axis acceleration sensors without enlarging the chip surface.
  • cascaded structures can be realized.
  • rotation rate sensors can be produced whose detection structures (acceleration sensors) are arranged on or under a vibrator (oscillator).
  • FIG. 5 shows an SOI wafer having a second structured functional layer 8 of monocrystalline silicon and a second sacrificial layer 9 of monocrystalline silicon. Germanium. It is important that the structuring takes place in such a way that the zones which are filled by the sacrificial material in each case form interconnected areas which can be reached through the last silicon layer.
  • FIG. 6 shows an SOI wafer with a closed cap layer 10.
  • a last sacrificial layer 11 made of monocrystalline silicon germanium, which is broken at points at which contact has to be made later.
  • the application of the last sacrificial layer 11, its structuring and the application of the cap layer 10 take place after the functional structure has been completely formed.
  • accesses 12 are structured in the cap layer 10, via which the entire sacrificial material can be leached out by C1F 3 gas phase salts in one step. This produces the mechanical functionality of the functional structures.
  • FIG. 8 shows a detail of an SOI wafer with a sealed and contacted MEMS structure. By way of example, it has four mechanically deflectable structures 15, 16, 17, 18, two of which are arranged one above the other.
  • the accesses required in the cap layer 10 for dissolving out the sacrificial material were hermetically sealed in the present case by plasma-assisted nonconformal deposition of an oxide 19 at low temperature, for example based on silane or TEOS.
  • the plasma-assisted oxide deposition can be ensured by appropriate adjustment of the plasma parameters in coordination with the geometric boundary conditions of the access in the cap layer 10 that no too deep penetration of the plasma takes place in the structural cavities of the arrangement.
  • the processing of bond pads 20 onto structures 13, which serve to make contact is preferably carried out with the aid of sputtering technology.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)

Abstract

L'invention concerne un procédé de fabrication de structures MEMS comprenant au moins une couche fonctionnelle en silicium contenant des structures, qui sont libérées par l'élimination d'une couche sacrificielle. Au moins une couche sacrificielle et au moins une couche fonctionnelle sont séparées de telle sorte qu'elles se développent de manière monocristalline, et la couche sacrificielle est composée d'une couche composite de silicium et germanium.
EP07729426A 2006-07-12 2007-05-23 Procédé de fabrication de structures mems Withdrawn EP2051929A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006032195A DE102006032195A1 (de) 2006-07-12 2006-07-12 Verfahren zur Herstellung von MEMS-Strukturen
PCT/EP2007/054988 WO2008006641A1 (fr) 2006-07-12 2007-05-23 Procédé de fabrication de structures mems

Publications (1)

Publication Number Publication Date
EP2051929A1 true EP2051929A1 (fr) 2009-04-29

Family

ID=38458788

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07729426A Withdrawn EP2051929A1 (fr) 2006-07-12 2007-05-23 Procédé de fabrication de structures mems

Country Status (5)

Country Link
US (1) US20100297781A1 (fr)
EP (1) EP2051929A1 (fr)
JP (1) JP2009542452A (fr)
DE (1) DE102006032195A1 (fr)
WO (1) WO2008006641A1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2932923B1 (fr) 2008-06-23 2011-03-25 Commissariat Energie Atomique Substrat heterogene comportant une couche sacrificielle et son procede de realisation.
FR2932788A1 (fr) * 2008-06-23 2009-12-25 Commissariat Energie Atomique Procede de fabrication d'un composant electromecanique mems / nems.
DE102009029202B4 (de) 2009-09-04 2017-05-24 Robert Bosch Gmbh Verfahren zum Herstellen eines mikromechanischen Systems
WO2011154363A2 (fr) * 2010-06-07 2011-12-15 Commissariat à l'énergie atomique et aux énergies alternatives Dispositif d'analyse comportant un réseau mems et/ou nems
US8633088B2 (en) 2012-04-30 2014-01-21 Freescale Semiconductor, Inc. Glass frit wafer bond protective structure
DE102013212118B4 (de) * 2013-06-25 2025-06-26 Robert Bosch Gmbh Sensorsystem mit zwei Inertialsensoren
DE102015206996B4 (de) 2015-04-17 2025-05-22 Robert Bosch Gmbh Verfahren zum Herstellen von mikroelektromechanischen Strukturen in einer Schichtenfolge und ein entsprechendes elektronisches Bauelement mit einer mikroelektromechanischen Struktur
CN112666236A (zh) * 2020-04-17 2021-04-16 华中科技大学 一种传感器集成芯片及其制备
IT202000011755A1 (it) * 2020-05-20 2021-11-20 St Microelectronics Srl Procedimento di fabbricazione di un dispositivo micro-elettro-meccanico, in particolare sensore di movimento con comando/rilevazione di tipo capacitivo, e relativo dispositivo mems
DE102021213259A1 (de) 2021-11-25 2023-05-25 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Cavity SOI Substrats und mikromechanischen Strukturen darin
DE102022208514A1 (de) 2022-08-17 2024-02-22 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung von mikroelektromechanischen Strukturen
DE102023102347A1 (de) 2023-01-31 2024-08-01 Carl Zeiss Smt Gmbh Optisches Bauelement
DE102023206603A1 (de) 2023-07-12 2025-01-16 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Verarbeiten eines Halbleiter-Wafers und Montageschablone
US20250033951A1 (en) * 2023-07-28 2025-01-30 Lawrence Semiconductor Research Laboratory, Inc. Anchor structure
DE102023123480A1 (de) 2023-08-31 2025-03-06 Carl Zeiss Smt Gmbh Verlagerungseinrichtung und optisches Bauelement
DE102023211098A1 (de) 2023-11-10 2025-05-15 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Transferieren von Chips eines Wafers und entsprechende Vorrichtung
US20250187901A1 (en) * 2023-12-08 2025-06-12 Lawrence Semiconductor Research Laboratory, Inc. Micro-electro-mechanical systems (mems) having vertical stops and anchor structures
DE102024200570A1 (de) 2024-01-23 2025-07-24 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung von MEMS-Baugruppen
DE102024201175A1 (de) * 2024-02-09 2025-08-14 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines gekoppelten Wafers

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Publication number Priority date Publication date Assignee Title
DE10017976A1 (de) * 2000-04-11 2001-10-18 Bosch Gmbh Robert Mikromechanisches Bauelement und entsprechendes Herstellungsverfahren
DE10065013B4 (de) * 2000-12-23 2009-12-24 Robert Bosch Gmbh Verfahren zum Herstellen eines mikromechanischen Bauelements
US6790699B2 (en) * 2002-07-10 2004-09-14 Robert Bosch Gmbh Method for manufacturing a semiconductor device
US6808953B2 (en) * 2002-12-31 2004-10-26 Robert Bosch Gmbh Gap tuning for surface micromachined structures in an epitaxial reactor
US7075160B2 (en) * 2003-06-04 2006-07-11 Robert Bosch Gmbh Microelectromechanical systems and devices having thin film encapsulated mechanical structures
FR2857952B1 (fr) * 2003-07-25 2005-12-16 St Microelectronics Sa Resonateur electromecanique et procede de fabrication d'un tel resonateur
US7902008B2 (en) * 2005-08-03 2011-03-08 Globalfoundries Inc. Methods for fabricating a stressed MOS device

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Also Published As

Publication number Publication date
JP2009542452A (ja) 2009-12-03
WO2008006641A1 (fr) 2008-01-17
DE102006032195A1 (de) 2008-01-24
US20100297781A1 (en) 2010-11-25

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