EP2198519A1 - Systèmes et procédés de conversion analogique-numérique recalée synchrone - Google Patents

Systèmes et procédés de conversion analogique-numérique recalée synchrone

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Publication number
EP2198519A1
EP2198519A1 EP08756758A EP08756758A EP2198519A1 EP 2198519 A1 EP2198519 A1 EP 2198519A1 EP 08756758 A EP08756758 A EP 08756758A EP 08756758 A EP08756758 A EP 08756758A EP 2198519 A1 EP2198519 A1 EP 2198519A1
Authority
EP
European Patent Office
Prior art keywords
sub
level
comparators
output
clock phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08756758A
Other languages
German (de)
English (en)
Other versions
EP2198519A4 (fr
Inventor
Choshu Ito
Erik Chmelar
William Loh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Corp filed Critical LSI Corp
Publication of EP2198519A1 publication Critical patent/EP2198519A1/fr
Publication of EP2198519A4 publication Critical patent/EP2198519A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Definitions

  • the present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for analog to digital conversion.
  • Analog to digital converters are used in a number of semiconductor devices to convert an analog electrical signal to a digital representation thereof. In the conversion process, a continuous analog signal is converted to a series of discrete or quantized digital values representing the analog signal at defined sample times. Simple analog to digital converters operate over a specified, static range of operation typically defined to encompass an expected analog input signal.
  • Fig. 1 depicts an exemplary prior art flash analog to digital converter 100. Flash analog to digital converter 100 includes a comparator bank 120 including a number of comparators 121, 122, 123, 124, 125 that each receive a respective reference threshold (i.e., ref(n-l), ref(n-2), ref(3), ref(2) and ref(l)).
  • each of comparators 121, 122, 123, 124, 125 receives an analog input 105, and compares analog input 105 to the respective reference threshold.
  • the reference thresholds are chosen such that the combined output of comparator bank 120 is a thermometer code indicated as a digital output 170.
  • digital output 170 includes an uninterrupted series of O's followed by an uninterrupted series of Is with the transition between Os and Is indicating the level of analog input 105 (i.e., a thermometer code without bubbles).
  • digital output 170 is provided to an encoder 180 that provides an encoded output 190 that may be more compact than a thermometer code.
  • the present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for analog to digital conversion.
  • Such analog to digital converter circuits include a first set of sub-level interleaves and a second set of sub-level interleaves.
  • the first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase.
  • the second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.
  • a global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves.
  • an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase
  • an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
  • Other embodiments of the present invention provide methods for analog to digital conversion.
  • the methods include performing a first set of analog to digital conversions using a first set of comparators; performing a second set of analog to digital conversions using a second set of comparators; performing a third set of analog to digital conversions using a third set of comparators; and performing a fourth set of analog to digital conversions using a fourth set of comparators.
  • a result from the first set of analog to digital conversions is selected based at least in part on a first registered result to provide a first selected result.
  • a result from the second set of analog to digital conversions is selected based at least in part on the first selected result to provide a second selected result.
  • a result from the third set of analog to digital conversions is selected based at least in part on the second registered result to provide a third selected result.
  • a results from the fourth set of analog to digital conversions is selected based at least in part on the third selected result to provide a fourth selected result.
  • the fourth selected result is registered to provide the first registered result, and the second selected result is registered to provide the second registered result.
  • performing the first set of analog to digital conversions is synchronized to a first clock phase; performing the second set of analog to digital conversions is synchronized to a second clock phase; performing the third set of analog to digital conversions is synchronized to a third clock phase; and performing the fourth set of analog to digital conversions is synchronized to a fourth clock phase.
  • registering the fourth selected result is synchronized to the first clock phase, and registering the second selected result is synchronized to the third clock phase.
  • Such communication systems include a receiver utilizing at least one retimed analog to digital converter.
  • the retimed analog to digital converter includes a first set of sub-level interleaves and a second set of sub-level interleaves.
  • the first set of sub-level interleaves includes a first sub- level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase.
  • the second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.
  • a global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves.
  • the systems include a transmitter and a medium. In such instances, information is provided from the transmitter to the receiver via the medium.
  • the system is a storage system, and the medium is a storage medium.
  • the system is a wireless communication system, and the medium is a wireless communication medium.
  • FIG. 1 depicts a prior art flash analog to digital converter
  • Fig. 2a is an analog to digital converter using a multiplexer tree implemented in combinatorial logic in accordance with some embodiments of the present invention
  • Fig. 2b is another analog to digital converter using a multiplexer tree implemented in synchronized combinatorial logic in accordance with one or more embodiments of the present invention
  • FIG. 3a depicts a synchronous, retimed analog to digital converter in accordance with various embodiments of the present invention
  • Fig. 3b is a timing diagram depicting an exemplary operation of the synchronous, retimed analog to digital converter of Fig. 3a;
  • FIG. 4 depicts a communication system including a synchronous, retimed analog to digital converter in accordance with some embodiments of the present invention.
  • the present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for analog to digital conversion.
  • a dynamic range analog to digital converter is a special purpose analog to digital converter that may be used for detecting a bit sequence transmitted through a known channel.
  • An example of a dynamic analog to digital converter is described in US Pat. App. No. 12/108,791 entitled “Analog-To-Digital Converter” and filed April 24, 2008 by Chmelar et al. The aforementioned application is incorporated herein by reference for all purposes.
  • Such a dynamic analog to digital converter employs one or more comparators that compare an input against a reference voltage. The output of the dynamic analog to digital converter may then be used to select an input range for comparison during a subsequent bit period.
  • an analog to digital converter may be unified with a modified Decision Feedback Equalization (DFE) circuit to yield an advantage in predicting a future range for a dynamic analog to digital converter.
  • DFE Decision Feedback Equalization
  • the aforementioned application is incorporated herein by reference for all purposes.
  • the incorporated DFE may reduce or eliminate inter-symbol interference that occurs in relation to processing a serial bit sequence in a channel.
  • Fig. 2a and Fig. 2b depict two examples of analog to digital converters that are incorporated with a modified DFE.
  • Analog to digital converter 200 uses some level of pipelining implemented using a multiplexer tree and intervening registers.
  • Analog to digital converter 200 utilizes a multiplexer tree similar to that disclosed in US Pat. App. No. 12/134,523 and filed on a date even herewith by Gribok et al. The aforementioned application is assigned to an entity common hereto, and is incorporated herein by reference for all purposes.
  • Analog to digital converter 200 includes a bank of eight comparators 210 that each compare an analog input 220 against respective reference voltages (not shown).
  • each of comparators 210 is clocked by a respective gated clock that is generated by a bank of AND gates 230.
  • Each of AND gates 230 logically ANDs a clock input 224 with a combination of an enable bit 282 and an enable bit 292.
  • one quarter of comparators 210 i.e., comparators a, e are clocked whenever enable bit 282 and enable bit 292 are both asserted low, and a clock input 224 is asserted high.
  • comparators 210 are clocked whenever enable bit 282 and enable bit 292 are both asserted high, and clock input 224 is asserted high.
  • comparators 210 i.e., comparators b, f
  • comparators c, g are clocked whenever enable bit 282 is asserted high, enable bit 292 is asserted low, and clock input 224 is asserted high.
  • comparators 210 i.e., comparators c, g
  • comparators 210 are clocked whenever enable bit 282 is asserted high, enable bit 292 is asserted low, and clock input 224 is asserted high.
  • An output bit 284 is equivalent to the output of one of comparators 210 asserted one bit period prior
  • enable bit 282 is equivalent to the output of one of comparators 210 asserted two bit periods prior
  • output bit 292 is equivalent to the output of one of comparators 210 asserted three bit periods prior, with all three being based on previous bit assertions as selected by a synchronized multiplexer tree comprising a first tier of multiplexers 240, a first tier of flip-flops 250, a second tier of multiplexers 260, and a third tier multiplexer 270.
  • Enable bit 282 is stored in a flip-flop 280
  • output bit 292 is stored in a flip-flop 290.
  • Enable bits 282, 292 are provided to AND gates 230 to enable clocking of a selected subset of comparators 210. Further, enable bit 292 drives the selector input of the multiplexers in first tier multiplexers 240 and second tier multiplexers 260. Enable bit 282 drives the selector input of third tier multiplexer 280.
  • Fig. 2b is another analog to digital converter 201 using a multiplexer tree 211 implemented in synchronized combinatorial logic.
  • Analog to digital converter 201 includes a number of comparators 215 that each compare an analog input 291 against respective reference voltages (not shown) that span the input range of analog to digital comparator 201.
  • a distinct reference voltage is provided to each of comparators 215 with the reference voltages extending across the input range of analog to digital converter 201.
  • the respective reference voltages are programmable such that the input range of analog to digital converter 201 can be adjusted.
  • An output bit 285 of one of comparators 215 is selected using multiplexer tree 211.
  • Output bit 285 is selected based on prior determined outputs such that inter symbol interference is reduced.
  • output bit 285 is provided to a flip-flop 295.
  • a single enable bit 297 provided from flip-flop 295 is used as a selector input for the different tiers of multiplexer tree 211.
  • the outputs of each tier of multiplexer tree 211 are synchronized to clock signal 225 using flip-flops.
  • enable bit 297 from flip-flop 295 receives three successive values of output bit 285 (i.e., the value of output bit 285 from three successive bit periods).
  • the three successive values of output bit 285 are used to moved a respective comparator output from one of comparators 215 through multiplexer tree 211 until the output is provided as output bit 285.
  • T is the period of the clock used to synchronize the analog to digital converter
  • t cq is the time required to stabilize a newly clocked flip-flop output
  • t su is a setup time for an intervening flip-flop.
  • the maximum data rate is limited regardless of the levels of interleaving, pipelining depth, or speculation bits utilized. This is because flip-flops are used to transfer data between clock periods. Such flip-flops can be very slow circuit elements. For example, in some technologies, the combination of t cq and t su may be 180ps. Where a data rate of six giga bits per second is desired, the combination of t cq and t su exceeds the clock period (T) making the above described circuits unable to achieve the desired result.
  • Some embodiments of the present invention provide for retiming an analog to digital converter unified with a modified DFE to achieve higher bandwidth operation than that achievable through use of corresponding un -retimed circuits.
  • some embodiments of the present invention provide the above mentioned retiming by employing two or more levels of interleaving. This may include, for example, a global level of interleaving along with one or more sub-levels of interleaving. Such a sub-level of interleaving may include a number of sub- level interleave. As an example, where one sub-level of interleaving is employed along with one global level of interleaving, data from the comparators is processed in sub-level interleaves. The output of the sub-level interleaves is passed to the global interleave.
  • a synchronous, retimed analog to digital converter 300 is shown in accordance with various embodiments of the present invention.
  • Analog to digital converter 300 is clocked using eight different phases of a master clock.
  • the eight clock phases are labeled cl, c2, c3, c4, c5, c6, c7, c8.
  • the eight phases are evenly distributed phases of the master clock, with each of the eight phases being approximately forty-five degrees advanced from the preceding phase.
  • the master clock and eight clock phases are not individually shown. Rather, clocked circuit elements of analog to digital converter 300 are labeled cl-c8 to indicate which of the eight clock phases is used to clock that particular circuit element.
  • Analog to digital converter 300 includes eight sub-level interleaves 310, 320, 330, 340, 350, 360, 370, 380.
  • the eight sub-level interleaves are implemented as two global interleaves 390, 395.
  • global interleave 390 includes a group of four sub-level interleaves (i.e.. sub-level interleaves 310, 320, 330, 340) and global interleave 395 includes a group of four sub- level interleaves (i.e., sub-level interleaves 350, 360, 370, 380).
  • Analog to digital converter 300 includes a number of comparators that each compare an analog input (not shown) with respective reference voltages 302, 304, 306, 308.
  • Reference voltages 302, 304, 306, 308 are programmed by selecting a particular predefined output from a lookup table 309. The selected outputs from lookup table 309 are provided to four digital to analog converters 301, 303, 305, 307 that in turn drive reference voltages 302, 304, 306, 308, respectively.
  • Sub-level interleave 310 includes a set of four comparators 312 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 312 are registered by respective ones of a set of four flip-flops 314.
  • One of the outputs of flip-flops 314 is selected using a two tier multiplexer 316, and an output of multiplexer 316 is registered by a flip-flop 318.
  • the registered output is labeled Al on the diagram.
  • all of comparators 312 and flip-flops 314 are synchronized to clock phase c5.
  • Flip-flop 318 is synchronized to clock phase c5.
  • Sub-level interleave 320 includes a set of four comparators 322 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 322 are registered by respective ones of a set of four flip-flops 324.
  • One of the outputs of flip-flops 324 is selected using a two tier multiplexer 326, and an output of multiplexer 326 is registered by a flip-flop 328.
  • the registered output is labeled A2 on the diagram.
  • all of comparators 322 are synchronized to clock phase c2
  • all of flip- flops 324 are synchronized to clock phase c6.
  • Flip-flop 328 is synchronized to clock phase c5.
  • Sub-level interleave 330 includes a set of four comparators 332 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 332 are registered by respective ones of a set of four flip-flops 334.
  • One of the outputs of flip-flops 334 is selected using a two tier multiplexer 336, and an output of multiplexer 336 is registered by a flip-flop 338.
  • the registered output is labeled A3 on the diagram.
  • all of comparators 332 are synchronized to clock phase c3
  • all of flip- flops 334 are synchronized to clock phase c7.
  • Flip-flop 338 is synchronized to clock phase c5.
  • Sub-level interleave 340 includes a set of four comparators 342 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 342 are registered by respective ones of a set of four flip-flops 344.
  • One of the outputs of flip-flops 344 is selected using a two tier multiplexer 346, and an output of multiplexer 346 is registered by a flip-flop 348.
  • the registered output is labeled A4 on the diagram.
  • all of comparators 342 are synchronized to clock phase c4, and all of flip- flops 344 are synchronized to clock phase c8.
  • Flip-flop 348 is synchronized to clock phase c5.
  • Sub-level interleave 350 includes a set of four comparators 352 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 352 are registered by respective ones of a set of four flip-flops 354.
  • One of the outputs of flip-flops 354 is selected using a two tier multiplexer 356, and an output of multiplexer 356 is registered by a flip-flop 358.
  • the registered output is labeled A5 on the diagram.
  • all of comparators 352 are synchronized to clock phase c5, and all of flip- flops 354 are synchronized to clock phase cl.
  • Flip-flop 358 is synchronized to clock phase cl.
  • Sub-level interleave 360 includes a set of four comparators 362 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 362 are registered by respective ones of a set of four flip-flops 364.
  • One of the outputs of flip-flops 364 is selected using a two tier multiplexer 386, and an output of multiplexer 366 is registered by a flip-flop 368.
  • the registered output is labeled A6 on the diagram.
  • all of comparators 362 are synchronized to clock phase c6, and all of flip- flops 364 are synchronized to clock phase c2.
  • Flip-flop 368 is synchronized to clock phase cl.
  • Sub-level interleave 370 includes a set of four comparators 372 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 372 are registered by respective ones of a set of four flip-flops 374.
  • One of the outputs of flip-flops 374 is selected using a two tier multiplexer 376, and an output of multiplexer 376 is registered by a flip-flop 378.
  • the registered output is labeled A7 on the diagram.
  • all of comparators 372 are synchronized to clock phase c7
  • all of flip- flops 374 are synchronized to clock phase c3.
  • Flip-flop 378 is synchronized to clock phase cl.
  • Sub-level interleave 380 includes a set of four comparators 382 that each compare the analog input with a respective one of reference voltages 302, 304, 306. 308.
  • the outputs from comparators 382 are registered by respective ones of a set of four flip-flops 384.
  • One of the outputs of flip-flops 384 is selected using a two tier multiplexer 386, and an output of multiplexer 386 is registered by a flip-flop 388.
  • the registered output is labeled A8 on the diagram.
  • all of comparators 382 are synchronized to clock phase c8, and all of flip- flops 384 are synchronized to clock phase c4.
  • Flip-flop 388 is synchronized to clock phase cl.
  • the output of multiplexer 316 is selected based on a combination of A7 and A8.
  • A7 operates to select between the outputs of flip-flops 314 in the first tier of multiplexer 316 and A8 operates to select between the outputs of the first tier of multiplexer 316.
  • the output of multiplexer 326 is selected based on a combination of A8 and the output of multiplexer 316.
  • A8 operates to select between the outputs of flip-flops 324 in the first tier of multiplexer 326 and the output of multiplexer 316 operates to select between the outputs of the first tier of multiplexer 326.
  • the output of multiplexer 336 is selected based on a combination of the output of multiplexer 316 and the output of multiplexer 326.
  • the output of multiplexer 316 operates to select between the outputs of flip-flops 334 in the first tier of multiplexer 336 and the output of multiplexer 326 operates to select between the outputs of the first tier of multiplexer 336.
  • the output of multiplexer 346 is selected based on a combination of the output of multiplexer 326 and the output of multiplexer 336.
  • the output of multiplexer 326 operates to select between the outputs of flip-flops 344 in the first tier of multiplexer 346 and the output of multiplexer 336 operates to select between the outputs of the first tier of multiplexer 346.
  • the output of multiplexer 356 is selected based on a combination of A3 and A4.
  • A3 operates to select between the outputs of flip-flops 354 in the first tier of multiplexer 356 and A4 operates to select between the outputs of the first tier of multiplexer 356.
  • the output of multiplexer 366 is selected based on a combination of A4 and the output of multiplexer 356.
  • A4 operates to select between the outputs of flip-flops 364 in the first tier of multiplexer 366 and the output of multiplexer 356 operates to select between the outputs of the first tier of multiplexer 366.
  • the output of multiplexer 376 is selected based on a combination of the output of multiplexer 356 and the output of multiplexer 366.
  • the output of multiplexer 356 operates to select between the outputs of flip-flops 374 in the first tier of multiplexer 376 and the output of multiplexer 366 operates to select between the outputs of the first tier of multiplexer 376.
  • the output of multiplexer 386 is selected based on a combination of the output of multiplexer 366 and the output of multiplexer 376.
  • the output of multiplexer 366 operates to select between the outputs of flip-flops 384 in the first tier of multiplexer 386 and the output of multiplexer 376 operates to select between the outputs of the first tier of multiplexer 386.
  • Timing diagram 301 depicts an exemplary operation, and it will be understood by one of ordinary skill in the art that other timing diagrams may be developed to depict other exemplary operations of synchronous, retimed analog to digital converter 300.
  • flip-flops 354 are clocked making output 356 available
  • flip-flops 358, 368, 378, 388 are all clocked making A5-A8 available on the same clock edge at the global interleave level.
  • flip-flops 364 are each clocked making output 366 available.
  • flip-flops 374 are each clocked making output 376 available.
  • comparators 324 are each clocked at the sub-interleave level, and flip-flops 384 are each clocked making output 386 available.
  • flip-flops 314 are clocked making output 316 available, and flip-flops 318, 328, 338, 348 are all clocked making A1-A4 available on the same clock edge at the global interleave level.
  • flip-flops 324 are each clocked making output 326 available.
  • comparators 372 are each clocked at the sub-interleave level, and flip-flops 334 are each clocked making output 336 available.
  • comparators 384 are each clocked at the sub-interleave level, and flip- flops 344 are each clocked making output 346 available.
  • outputs 316, 326, 336, 356, 366, 376 and A3, A4, A7, A8 are used to select the appropriate comparator output.
  • Synchronous, retimed analog to digital converter 300 performs block processing via two levels of interleaving.
  • sub-level interleaves 310, 320, 330, 340 interleave based on clocks cl-c4; and sub-level interleaves 350, 360, 370, 380 interleave based on clocks c5-c8.
  • the block outputs from sub-level interleaves 310, 320, 330, 340 are globally interleaved based on clock c5, and the block outputs from sub-level interleaves 310, 320, 330, 340 are globally interleaved based on clock cl.
  • sub-level interleaves 310, 320, 330, 340 may be globally interleaved based on clock c8, and the block outputs from sub-level interleaves 310, 320, 330, 340 may be globally interleaved based on clock c4. This approach results in the reduction of one clock period of latency.
  • sub-level interleaving and global interleaving that are possible in accordance with different embodiments of the present invention.
  • the retiming of the data transfer occurs between global interleaves. Said another way, the retiming of the data transfer occurs through synchronization using flip-flops 318, 238, 338, 348 using one clock phase and flip-flops 358, 268, 378, 388 using another clock phase. Therefore, the data transfer between one global interleave (i.e., the outputs from sub-level interleaves 310, 320, 330, 340) and the other global interleave (i.e., the outputs from sub-level interleaves 350, 360, 370, 380) has an amount of time that is equal to 4T (i.e., four periods of the master clock depicted in Fig. 3b).
  • 4T i.e., four periods of the master clock depicted in Fig. 3b
  • a desired amount of sub-level interleaving and global interleaving may be determined based on latency including comparator delays, flip-flops and multiplexers allowable in the circuit. For example, assume the comparator, flip-flop and multiplexer delays are such that the number of sub-level interleaves (j) is four, and the number of global interleaves (i) is two. Further, assume that an associated data transfer channel exhibits an inter symbol interference characteristic requiring a number of taps (tap) equal to two. The aforementioned design constraints leads to the circuit of Fig.
  • comparators i.e., 2 ⁇ ta ⁇
  • a modification to the number of taps, the number of sub-level interleaves, or the number of global interleaves will yield different circuit designs. Further, it should be noted that multi-level sub-level interleaves may be possible in accordance with different embodiments of the present invention.
  • T master clock period
  • tcq flip-flop clock-to-q delay
  • tsu flip-flop setup time
  • tmux multiplexer delay
  • tcomp comparator delay
  • cwire wire capacitance.
  • Input Capacitance 2/ * 2 tap * ccomp +f (cwire).
  • Communication system 400 includes a transmitter 410 that transmits a signal representing a data set to receiver 420 via a transfer medium 430.
  • Transfer medium 430 may be, but is not limited to, a wireless transfer medium, a electrically wired transfer medium, a magnetic storage medium, or an optical transfer medium. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of transfer media that may be used in relation to different embodiments of the present invention.
  • Receiver 420 includes synchronous, retimed analog to digital converter similar to that described above in relation to Fig. 3a.
  • communication system 400 may be a cellular telephone system with transmitter 410 and receiver 420 being cell phones and/or cell towers.
  • communication system 400 may be a magnetic storage medium with transmitter 410 being a write function, transfer medium 430 being a magnetic storage medium, and receiver 420 being a read function. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other systems that may be represented as communication system 400 in accordance with different embodiments of the present invention.

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Abstract

La présente invention porte sur des systèmes et des procédés de conversion analogique-numérique. Un convertisseur analogique-numérique recalé est décrit qui comprend des premier et second ensembles d'entrelacements de niveau secondaire. Le premier ensemble d'entrelacements de niveau secondaire comprend un premier entrelacement de niveau secondaire comprenant un premier ensemble de comparateurs synchronisés sur une première phase d'horloge, et un deuxième entrelacement de niveau secondaire comprenant un deuxième ensemble de comparateurs synchronisés sur une deuxième phase d'horloge. Le second ensemble d'entrelacements de niveau secondaire comprend un troisième entrelacement de niveau secondaire comprenant un troisième ensemble de comparateurs synchronisés sur une troisième phase d'horloge, et un quatrième entrelacement de niveau secondaire comprenant un quatrième ensemble de comparateurs synchronisés sur une quatrième phase d'horloge. Un entrelacement global sélectionne l'un du premier ensemble de comparateurs sur la base d'une sortie provenant du second ensemble d'entrelacements de niveau secondaire.
EP08756758A 2008-06-06 2008-06-06 Systèmes et procédés de conversion analogique-numérique recalée synchrone Withdrawn EP2198519A4 (fr)

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PCT/US2008/066060 WO2009148457A1 (fr) 2008-06-06 2008-06-06 Systèmes et procédés de conversion analogique-numérique recalée synchrone

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EP2198519A1 true EP2198519A1 (fr) 2010-06-23
EP2198519A4 EP2198519A4 (fr) 2012-10-31

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US7956790B2 (en) 2011-06-07
KR20110033101A (ko) 2011-03-30
EP2198519A4 (fr) 2012-10-31
US20100194616A1 (en) 2010-08-05
WO2009148457A1 (fr) 2009-12-10
TWI448085B (zh) 2014-08-01
JP2011523293A (ja) 2011-08-04
CN101821951B (zh) 2014-07-23
JP5244233B2 (ja) 2013-07-24
CN101821951A (zh) 2010-09-01
TW200952347A (en) 2009-12-16

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