EP2242101A2 - Circuit de réception pour connecteurs avec une impédance complexe variable - Google Patents

Circuit de réception pour connecteurs avec une impédance complexe variable Download PDF

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Publication number
EP2242101A2
EP2242101A2 EP10160034A EP10160034A EP2242101A2 EP 2242101 A2 EP2242101 A2 EP 2242101A2 EP 10160034 A EP10160034 A EP 10160034A EP 10160034 A EP10160034 A EP 10160034A EP 2242101 A2 EP2242101 A2 EP 2242101A2
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Prior art keywords
receive
semiconductor die
circuit
inter
complex impedance
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EP10160034A
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German (de)
English (en)
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EP2242101B1 (fr
EP2242101A3 (fr
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Robert J. Drost
Robert D. Hopkins
Alex Chow
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Oracle America Inc
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Oracle America Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
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    • H10W42/00—Arrangements for protection of devices
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    • H10W42/00—Arrangements for protection of devices
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    • H—ELECTRICITY
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    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/401—Resistive arrangements
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
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    • H10W90/00—Package configurations
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H10W44/212—Coaxial feed-throughs in substrates
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/216—Waveguides, e.g. strip lines
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    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/226—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for HF amplifiers
    • H10W44/234—Arrangements for impedance matching
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/074—Connecting or disconnecting of anisotropic conductive adhesives
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

Definitions

  • the present invention relates to circuits that mitigate signal distortion caused by a variable complex impedance between a connector on a semiconductor die and one or more microspring or anisotropic-film inter-component connectors.
  • PxC based on capacitive inter-chip contacts provides dense inter-chip connections, with a pitch between neighboring pads on the order of 10-100 ⁇ m.
  • PxC typically requires a similar order of mechanical alignment. It can be difficult to maintain this alignment in the presence of vibrations and thermal stress using a low-cost chip package.
  • the capacitance of the inter-chip contacts can be small, which makes it challenging to couple high-capacity power supplies using PxC.
  • Microsprings can be fabricated on a wide variety of surfaces, including: printed circuit boards (PCB s), organic or ceramic IC packages or on the surface of IC s themselves. They can be fabricated with an areal density of inter-chip connections that exceeds the density of input/output ( I / O ) signals on high performance IC s, and can provide electrical contacts without the use of solder. Moreover, microsprings can be designed to have more compliance than is possible by using PxC alone, which increases the tolerance to mechanical movement and misalignment. However, microsprings are typically required to make and maintain conductive contacts with connectors on IC s.
  • the microsprings In order to achieve such conductive contacts, the microsprings typically have sharp tips that can scrape through any oxide or passivation layers above the connectors on the IC s during a scrub-in process, which increases the fabrication costs of the microsprings. Furthermore, conductive contacts are often achieved by increasing the force between the microsprings and the connectors on an IC in a chip package, which also increases cost. In addition, the sharp tips and large forces can produce foreign particles (such as debris) that can reduce the conductivity of contacts over time, thereby reducing reliability and limiting the number of mating cycles.
  • Anisotropic conductive films can be fabricated by introducing conductive elements into an insulating elastic film so that the conductive elements generally line up normal to the surface of the film. Then, by placing the anisotropic film against a chip pad and compressing it, the conductive elements can make conductive contact, while the non-conductive film maintains isolation among neighboring chip pads. Unlike the microsprings, conduction through the anisotropic film typically involves conduction between the chip pad and its proximal conductive elements in the anisotropic film, and among the various conductive elements that are adjacent to each other within the anisotropic film. Similar to microsprings, anisotropic films often suffer from reliability issues due to the potential for the conductive elements to fail to make adequate contact with each other and with the chip pad. While reliability can be increased by increasing the compressive force, the chip package typically has to provide and maintain this higher force. In general, higher forces within a chip package decrease the chip-package reliability in other ways and increase the packaging cost.
  • One embodiment of the present invention provides a semiconductor die that includes a receive connector that is proximate to or on a surface of the semiconductor die.
  • This receive connector mechanically and electrically couples to one or more first inter-component connectors, thereby defining a receive variable complex impedance between the receive connector and the one or more first inter-component connectors.
  • the receive variable complex impedance corresponds to a first resistor in parallel with a first capacitor.
  • the semiconductor die includes a receive circuit, which is electrically coupled to the receive connector, that receives an electrical signal. This receive circuit mitigates signal distortion associated with the receive variable complex impedance.
  • the receive circuit can be adaptively configured to mitigate the signal distortion of the received electrical signal. Consequently, a configuration of the receive circuit may be selected, directly or indirectly, based at least in part on the receive variable complex impedance.
  • the receive circuit may be configured by adjusting a time constant of an RC circuit in the receive circuit to approximately equal a product of a resistance of the first resistor and a capacitance of the first capacitor.
  • the semiconductor die may include a control-logic circuit that characterizes the receive variable complex impedance and that selects the configuration of the receive circuit.
  • a resistance of the first resistor may be between 0.001-100 G ⁇ .
  • the semiconductor die may include an internal impedance electrically coupled in series between the receive connector and the receive circuit, where an impedance of the internal impedance dominates the receive variable complex impedance over a range of frequencies associated with the received electrical signal.
  • the internal impedance may include an inductor and/or a second capacitor.
  • a capacitance of the second capacitor may be significantly smaller than a capacitance of the first capacitor.
  • the capacitance of the second capacitor may be defined by a dielectric layer in the semiconductor die.
  • the received electrical signal includes a signal modulated on a carrier having a fundamental frequency greater than zero.
  • the received electrical signal may include data and/or power signals.
  • the receive circuit may include a rectifier circuit to recover a DC-power signal from the received electrical signal.
  • the semiconductor die may include one or more electrostatic-discharge-protection connectors proximate and adjacent to the receive connector. Additionally, the semiconductor die may include an electrostatic-discharge-protection component electrically coupled to the receive connector in parallel with the receive circuit and/or a fringe-field shield proximate and adjacent to the second capacitor.
  • the semiconductor die includes a transmit connector proximate to or on the surface of the semiconductor die.
  • This transmit connector mechanically and electrically couples to one or more second inter-component connectors, thereby defining a transmit variable complex impedance between the transmit connector and the one or more second inter-component connectors.
  • the transmit variable complex impedance corresponds to a second resistor in parallel with a second capacitor.
  • the semiconductor die may include a transmit circuit, which is electrically coupled to the transmit connector, that transmits another electrical signal.
  • the one or more first inter-component connectors include a microspring or an anisotropic film.
  • Another embodiment provides a system that includes the semiconductor die, another semiconductor die, and an inter-connect component that mechanically and electrically couples the semiconductor die and the other semiconductor die.
  • This inter-connect component includes the one or more first and/or the one or more second inter-component connectors.
  • Another embodiment provides a method for communicating an electrical signal, which may be performed by the semiconductor die (or one or more circuits on the semiconductor die).
  • the semiconductor die receives the electrical signal from the receive connector that is mechanically and electrically coupled to one or more inter-component connectors.
  • the semiconductor die characterizes the receive variable complex impedance based at least in part on the received electrical signal.
  • the semiconductor die configures the receive circuit to mitigate signal distortion associated with the receive variable complex impedance based at least in part on the characterization of the receive variable complex impedance.
  • FIG. 1A is a block diagram illustrating an existing inter-chip connection technique with a microspring.
  • FIG. 1B is a block diagram illustrating an existing inter-chip connection technique with an anisotropic film.
  • FIG. 2A is a block diagram illustrating an inter-chip connection technique in accordance with an embodiment of the present invention.
  • FIG. 2B is a block diagram illustrating an inter-chip connection technique in accordance with an embodiment of the present invention.
  • FIG. 3A is a block diagram illustrating an inter-chip connection technique in accordance with an embodiment of the present invention.
  • FIG. 3B is a block diagram illustrating an inter-chip connection technique in accordance with an embodiment of the present invention.
  • FIG. 4 is a block diagram illustrating an inter-chip connection technique in accordance with an embodiment of the present invention.
  • FIG. 5 illustrates an equivalent circuit of a variable complex impedance associated with an inter-chip connection in accordance with an embodiment of the present invention.
  • FIG. 6A is a block diagram illustrating a transmit circuit in accordance with an embodiment of the present invention.
  • FIG. 6B is a timing diagram illustrating electrical signals in accordance with an embodiment of the present invention.
  • FIG. 7 is a block diagram illustrating a receive circuit in accordance with an embodiment of the present invention.
  • FIG. 8 is a block diagram illustrating a receive circuit in accordance with an embodiment of the present invention.
  • FIG. 9A is a timing diagram illustrating a power signal in accordance with an embodiment of the present invention.
  • FIG. 9B is a block diagram illustrating a power circuit in accordance with an embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a system with chips coupled using microsprings in accordance with an embodiment of the present invention.
  • FIG. 11 is a block diagram illustrating a system with chips coupled using microsprings in accordance with an embodiment of the present invention.
  • FIG. 12 is a block diagram illustrating a system with chips coupled using microsprings in accordance with an embodiment of the present invention.
  • FIG. 13 is a flow chart illustrating a process for communicating an electrical signal in accordance with an embodiment of the present invention.
  • Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance which can be conductive, capacitive or both
  • This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip.
  • the circuit may mitigate signal distortion associated with the variable complex impedance.
  • the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies.
  • the circuit may be adapted to correct for the signal distortion.
  • this communication technique may reduce or eliminate the need for and the sensitivity to an oxide or passivation layer over the metal connector, which may increase the signal energy transferred through the inter-chip connection between the microspring or anisotropic-film contact and the metal connector.
  • the communication technique may allow: reduced microspring tip sharpness or anisotropic-film conductivity; reduced contact force; eliminate a scrub-in process; increased reliability of the inter-chip connection and the system; reduced sensitivity to misalignment between the microspring or anisotropic-film contact and the metal connector; smaller electrostatic discharge ( ESD ) protection components (which take up valuable chip area; reduce the maximum operating frequency and consume power); and/or reduced fabrication and assembly costs for the microspring or anisotropic film and package for the system.
  • ESD electrostatic discharge
  • FIG. 1A presents a block diagram illustrating an existing inter-chip connection technique 100, in which a microspring 114-1 is used in conjunction with PxC .
  • microspring 114-1 reduces the capacitance between distant signal connectors or pads, such as metal pad 112-1, that communicate using PxC .
  • the surface of IC or chip 110-1 may be coated with passivation layer 116-1 (such as a glass layer) to prevent microspring 114-1 from conductively contacting metal pad 112-1.
  • passivation layer 116-1, microspring 114-1 and metal pad 112-1 may have a rather small capacitance.
  • tip of microspring 114-1 has an area ( A ) of approximately 15x15 ⁇ m 2
  • passivation layer 116-1 has a thickness ( d ) of about 1 ⁇ m and a dieletric constant ( ⁇ r ) of 7.5
  • ⁇ o is the permittivity of free space (8.85 pF/m).
  • Cpad is 15 fF.
  • FIG. 1B presents a block diagram illustrating an existing inter-chip connection technique 150, in which an anisotropic-film contact occurs with anisotropic film 160 rather than one or more microsprings.
  • Example anisotropic films include the PariPoser® Material (from Paricon Technologies, Inc., of Fall River, Massachusetts), as well as a number of patented films, including: United States Patent 5,624,268 , entitled “Electrical Conductors Using Anisotropic Conductive Films," and United States Patent 4,778,950 , entitled “Anisotropic Elastomeric Interconnecting System.”
  • FIG 1B illustrates a cross-section of a PariPoser-type of anisotropic conductive elastomer film.
  • anisotropic film 160 small conductive balls are suspended in a silicone rubber such that the balls generally line up into columns (such as column 162) and provide conduction normal, but not tangential, to the surfaces of anisotropic film 160.
  • metal pad 112-1 may have a passivation layer, such as protection layer 116-1, to prevent arbitrary complex conductive contact.
  • existing inter-chip connection technique 150 may suffer comparable limitations, including limited power or signal energy transfer through the contact.
  • microsprings and microsprings contacts are used as an illustration of the embodiments in this disclosure. However, it should be understood that these embodiments may also be applied to anisotropic films and anisotropic-film contacts.
  • FIG. 2A presents a block diagram illustrating an inter-chip connection technique 200 for receive circuit 210
  • FIG. 2B presents a block diagram illustrating an inter-chip connection technique 250 for transmit circuit 260
  • one or more microsprings such as microspring 114-1
  • microspring 114-1 couples to metal pad 112-1 where metal pad 112-1 is exposed to air by a cut in passivation layer 116-2 of chips 110.
  • chip 110-2 includes ESD component 212-1 (such as a diode to ground) and chip 110-3 may include optional ESD component 212-2 (because transmit circuit 260 may be less sensitive to ESD ).
  • the thickness ( d ) of an oxide on the air-exposed metal pad 112-1 is 2 to 3 nm (which, for example, is the self-limited oxide growth on pure aluminum in air), then the average current of the coupled capacitor is increased and the equivalent impedance is decreased by 500-333 times, respectively.
  • Poweravg is 54 mW and R is 13 ⁇ . Consequently, we can supply 1 W of power using only about 40 microsprings ( e . g ., 20 to source the supply current, and 20 to sink the supply current). Because tens of thousands of microsprings can be patterned on a chip, hundreds of Watts of power can be supplied.
  • a large parasitic capacitance associated with ESD components 212 may be acceptable (typically, 2-8 pF for bonded pads).
  • this ESD -component capacitance may unacceptably attenuate high-frequency information or may introduce inter-symbol interference.
  • FIG. 3A presents a block diagram illustrating an inter-chip connection technique 300 for receive circuit 210.
  • conductively or capacitively coupled metal pad 112-1 is capacitively isolated from receive circuit 210 by capacitor 312-1.
  • chip 110-4 includes an internal impedance electrically coupled in series between metal pad 112-1 and receive circuit 210, such as an inductor and/or a capacitor. Note that a capacitance of capacitor 312-1 may correspond to a thickness and a dielectric constant of a layer deposited on chip 110-4.
  • ESD component 310-1 used to protect the capacitively coupled receive circuit 210 may be significantly reduced. Consequently, ESD component 310-1 may add a much smaller parasitic load, typically as low as 2 fF, because metal pad 112-1 can be protected from an ESD aggressor by nearby air-exposed ESD protector pads (as described further below with reference to FIG. 4 ).
  • Inter-chip connection technique 300 also may offer a significant advantage over existing inter-chip connection technique 100 ( FIG. 1A ).
  • metal pad 112-1 is typically only capacitively coupled to microspring 114-1 by less than half of the parasitic capacitance of metal pad 112-1. This limited capacitance further reduces the electrical signal.
  • capacitor 312-1 between metal pad 112-1 and the input to receive circuit 210 can be designed to have a very high ratio of coupling relative to the parasitic capacitance.
  • the corresponding chip with the transmit circuit may not need to include a capacitor, such as capacitor 312-1. However, in some embodiments, the corresponding chip with the transmit circuit includes such a capacitor.
  • FIG. 3B presents a block diagram illustrating an inter-chip connection technique 350 for transmit circuit 260 with optional capacitor 312-2.
  • chip 110-5 includes optional ESD component 310-2.
  • receive circuits in chips 110 are used as an illustration. In some embodiments, the components and techniques described are used separately or additionally with transmit circuits in chips 110.
  • FIG. 4 presents a block diagram illustrating an inter-chip connection technique 400 in which interdigitated fingers of metal form a shield capacitor 410 that adds very little parasitic capacitance to the input node of receive circuit 210 in chip 110-6. Hence the received signal can be quite large. Note that the non-conductive shield capacitor 410 connects metal pad 112-1 to receive circuit 210. Moreover, fringe-field shield 412 also reduces parastic capacitance. The residual parasitic capacitance can be readily driven by the impedance of the contact with microspring 114-1. While FIG. 4 shows interdigitation in one layer of metal, more layers of metal may be used to increase the ratio further.
  • FIG. 4 also shows ESD air-exposed metal pads 414 on either side of the signal metal pad 112-1.
  • These metal pads, and associated ESD components 416 permit a mini- ESD component 418 (such as a diode or capacitor to ground, which has much smaller parasitic load than ESD components 310) to protect the capacitively shielded receiver input from kV-level ESD events.
  • ESD air-exposed metal pads 414 may be shared among multiple capacitively or conductively coupled microspring metal pads or connections to lower the effective area cost.
  • FIG. 5 illustrates an equivalent circuit 500 of a variable complex impedance associated with an inter-chip connection, such as a microspring coupled to a connector or a metal pad on a chip.
  • This equivalent circuit has a resistor ( Rcontact ) 510 in parallel with a capacitor ( Ccontact ) 512.
  • Rcontact 510 typically has a value between 0.01 ⁇ to infinite impedance, depending on whether and to what degree the microspring tip breaks through the oxide on the metal pad.
  • Ccontact 512 typically has a value on the order of 1-10 pF, depending on the area of overlap between the microspring tip and the metal pad, and the thickness of the oxide and air gap between the microspring tip and the metal pad.
  • the contact impedance (Zcontact) should be as small as possible.
  • reducing Rcontact 510 ensures that Zcontact is small at all frequencies regardless of Ccontact 512.
  • Rcontact 510 is large or infinite, at high frequencies Ccontact 512 can still result in a small contact impedance. Therefore, in some embodiments, a small contact impedance can be achieved by AC -modulating power and/or data signals regardless of the mix of resistive and capacitive contact.
  • FIG. 6A presents a block diagram illustrating a transmit circuit 600
  • FIG. 6B presents a timing diagram 650 illustrating associated electrical signals.
  • unencoded signal Datain 610 is modulated by clock signal ( Clk ) 612 to produce a DC-balanced (50% high and 50% low) signal Txdata 614.
  • This modulation technique is sometimes referred to as 1 b2b, which means that one bit of data has been spread across two bits of encoded data. Therefore, this modulation technique has a 50% coding overhead with respect to bandwidth.
  • Other modulation techniques such as 4b6b or 8b 10 b or 64b65b, have lower coding overhead but typically require more complex encoding and decoding circuits, as well as higher added latency.
  • transmit channels are periodically refreshed using spare channels so that Datain 610 does not have to be encoded to be DC balanced.
  • receive-circuit biasing that is tolerant to inputs with maximum-run-lengths constraints is used rather than DC -balanced signals, such as Txdata 614.
  • FIGs. 7 and 8 present block diagrams illustrating receive circuits 700 and 800 which work with Txdata 614.
  • the inter-chip connection is shielded by Cshield 718 from ESD component and its parasitic capacitance, which is denoted Cesd 720.
  • Cshield 718 may be designed to have a capacitance that is always much less than Ccontact 512, such as 0.1 pF.
  • the capacitance of parasitic capacitor Cshpar 722 may be around half that of Cshield 718 or 0.05 pF.
  • Txdata 614 is passed undistorted to Rxin 714, albeit with attenuation from the capacitor divider between Cshield 718 and the sum of Cesd 720 and the input capacitance of amplifier 726. Note that this attenuation may be small because Cesd 720 may be only a few femtoFarads, and the input capacitance of amplifier 726 may be small compared to Cshield 718.
  • receive circuit 800 In receive circuit 800, more net signal energy will be coupled to receive input node ( Rxnoshield ) 810 than to Rxin 714 because there is no Cshield 718 ( FIG. 7 ).
  • the signal coupled to Rxnoshield 810 may be distorted because it may experience different attenuations and phase shifts at different frequencies. However, this distortion may be reduced or eliminated if the time constant given by the product of Rcontact 510 and Ccontact 512 is matched to the internal time constant of receive circuit 800, i . e ., the product of Rbias 724 and the sum of Cesd 720 and the input capacitance of amplifier 726.
  • the internal time constant of receive circuit 800 may be adjusted by selecting or adjusting either or both of Rbias 724 and the sum of Cesd 720 and the input capacitance of amplifier 726. This adjustment may be based at least in part on instructions or signals from control logic 812 (or a control-logic circuit). Furthermore, control logic 812 may adjust the internal time constant of receive circuit 800 after directly or indirectly characterizing the variable impedance ( e . g ., Rcontact 510, Ccontact 512 and/or their product) associated with the inter-chip connection.
  • control logic 812 may adjust the internal time constant of receive circuit 800 after directly or indirectly characterizing the variable impedance (e . g ., Rcontact 510, Ccontact 512 and/or their product) associated with the inter-chip connection.
  • Control logic 812 may sample Rxnoshield 810 twice after each transition, and using the slope of the signal may determine whether to increase or decrease the controllable values of Rbias 724, Cesd 720 and/or the input capacitance of amplifier 726.
  • receive circuit 700 ( FIG. 7 ) was described with a fixed configuration (because Cshield 718 in FIG. 7 may have a capacitance that is always much less than Ccontact 512), in some embodiments receive circuit 700 ( FIG. 7 ) includes optional control logic 728 (or a control-logic circuit) which directly or indirectly characterizes the inter-chip connection, and accordingly selects or adjusts the internal time constant of receive circuit 700 ( FIG. 7 ).
  • optional control logic 728 or a control-logic circuit
  • FIGs. 7 and 8 are each illustrated with one signal path, in other embodiments differential signal paths for at least the data signals are used to reduce susceptibility to noise sources.
  • Vthreshold 730 in FIGs. 7 and 8 is replaced with a second signal path.
  • FIG. 9A presents a timing diagram 900 illustrating a power signal TXpower 910
  • FIG. 9B presents a block diagram illustrating an associated power circuit 950.
  • TXpower 910 may be transmitted as an AC signal. This signal may be directly available from a power supply, or may be generated using DC-to-AC inverter circuits.
  • the signal swing of TXpower 910 may be two diode drops greater than chip core 960 requires in order to compensate for the two diode drops in each arm of power circuit 950. For instance, if chip core 960 requires 1.8 V and each diode drop is 0.15 V (for example for a Schottky diode), then TXpower 910 may be 2.1 V.
  • FIG. 9A presents a timing diagram 900 illustrating a power signal TXpower 910
  • FIG. 9B presents a block diagram illustrating an associated power circuit 950.
  • Vddcore net power signal
  • power circuit 950 in FIG. 9B is illustrated as a bridge rectifier, in other embodiments power circuit 950 separately or additionally rectifies TXpower 910 using a switch capacitor rectifier. This approach also permits the rectifier to step the amplitude up or down as required. Moreover, following power circuit 950, there may be a DC-to-DC converter circuit. In order to maximize the power transfer, in some embodiments, neither the transmit chip nor the receive chip in a power-signal channel include a shield capacitor.
  • FIG. 10 presents a block diagram illustrating a system 1000 with chips 1010-1 and 1012-1 coupled using microsprings 1014-1.
  • Microsprings 1014-1 may be integrated onto chip 1012-1 and contact pads 1016-1 in a glasscut opening may be integrated on chip 1010-1.
  • FIG. 11 presents a block diagram illustrating a system 1100 with chips 1010-2 and 1010-3 coupled using microsprings 1014-1 and 1014-2.
  • the coupling is mediated by an interposer chip 1110 with microsprings 1014-1 and 1014-2 on both faces.
  • Metal pads 1016 on chips 1010-2 and 1010-3 communicate through interposer chip 1110. Note that a given connection between chips 1010-2 and 1010-3 includes two conductive or capacitive contacts in series. By decomposing the corresponding transfer function into two series transfer functions, the analysis described previously still applies.
  • interposer chip 1110 provides all of microsprings 1014-1 and 1014-2 for the contacts to chips 1010-2 and 1010-3. Note the connections from the microsprings 1014-1 on one face of interposer chip 1110 to microsprings 1014-2 on the other face are not shown. These connections may connect the microsprings in the same order from left to right on both faces, may include some reorderings of microspring pairings, or may connect one microspring to multiple other microsprings if desired. In other embodiments, interposer chip 1110 provides the metal-pad portion of the contacts rather than the microspring for at least some set of the connections. Additionally, interposer chip 1110 could extend to the left and right and contact additional chips. Furthermore, the connections between microsprings or metal pads internal to interposer chip 1110 could permit a given chip to communicate with any or all of the chips on both sides of interposer chip 1110.
  • FIG. 12 presents a block diagram illustrating a system 1200 with chips 1010-2 and 1010-3 coupled using microsprings 1014-1 and 1014-2 on one side of a common substrate 1210 (such as a ceramic or organic substrate material).
  • a common substrate 1210 such as a ceramic or organic substrate material.
  • FIG. 11 This is a variation on system 1100 ( FIG. 11 ) in which all of the chips are on one side of interposer chip 1110 ( FIG. 11 ), which has been renamed substrate 1210.
  • substrate 1210 is coupled to an optional circuit board 1212 by a ball-grid array (BGA) or a pin-grid array (PGA).
  • BGA ball-grid array
  • PGA pin-grid array
  • either the transmit circuit or the receive circuit is on the microspring side or the metal pad side of a connection.
  • the transmit circuit may also couple non-conductively to the inter-chip connection using an on-chip shield capacitor. Although the energy transmitted would be reduced versus a conductive connection to the channel, this approach may reduce the size of one or more ESD components, which are coupled to the transmit circuit, and hence may reduce power consumption.
  • microsprings in the preceding embodiments no longer require a sharpened tip to scrub-in, these microsprings can have a variety of different shapes, such as: rectangles, circles and/or fingers. These shapes may: make it easier to fabricate the microsprings, increase reliability, and/or increase the contact capacitance. While the non-conductive shield was illustrated using a shield capacitor, in other embodiments one or more inductors, such as coupled spiral metal inductors (which function effectively a transformer), may be used.
  • microspring geometries there may be two or more microspring geometries on a given chip.
  • data-signal microsprings may be short with blunt ends, while power-signal microsprings may be longer with sharper tips.
  • the power-signal microsprings may be more likely to scrub-in and form resistive connections, thereby maximizing power transfer, and possibly allowing a simpler DC-power transmission.
  • yield and long-term reliability may be enhanced even if some number of the power-signal microsprings lose conductive connection.
  • Data-signal microsprings may be designed to have a lower insertion force, thereby simplifying the package design, because these connections may use circuits that are tolerant of conductive and/or capacitive contacts (such as receive circuits 700 and 800 in FIGs. 7 and 8 ).
  • electronic alignment techniques are used to correct for planar mechanical misalignments in systems, such as the systems shown in FIGs. 10-12 .
  • electronic alignment may be used with conductive-capacitive contacts if a given microsprings contacts an array of transmit or receive micropads or microbars.
  • the thickness of the oxide and the air gap between a given microspring and metal pad may be greater than the thickness of the oxide layer alone.
  • a conductive liquid, paste or film may be added to the contact area to fill in any gaps. This would also have the beneficial effect of increasing the area of overlap to the extent that the liquid, paste or film extends beyond the edges of the given microspring.
  • the preceding embodiments may include fewer components or additional components.
  • the expose metal of the chip metal pads may have one or more additional layers added to them so that their top surface extend beyond the elevation of the chip passivation layer.
  • two or more components may be combined into a single component and/or a position of one or more components may be changed.
  • the functionality is implemented more in hardware and less in software, or less in hardware and more in software, as is known in the art.
  • circuits may be implemented using PMOS and/or NMOS , and signals may include digital signals that have approximately discrete values and/or analog signals that have continuous values.
  • FIG. 13 presents a flow chart illustrating a process 1300 for communicating an electrical signal.
  • the semiconductor die receives the electrical signal from the receive connector that is mechanically and electrically coupled to one or more inter-component connectors (1310).
  • the semiconductor die characterizes the receive variable complex impedance based at least in part on the received electrical signal (1312).
  • the semiconductor die configures the receive circuit to mitigate signal distortion associated with the receive variable complex impedance based at least in part on the characterization of the receive variable complex impedance (1314).
  • process 1300 there may be additional or fewer operations. Moreover, the order of the operations may be changed and/or two or more operations may be combined into a single operation.

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CN101866907A (zh) 2010-10-20
US8098079B2 (en) 2012-01-17
EP2242101A3 (fr) 2011-11-09
CN101866907B (zh) 2014-07-16
US20100264954A1 (en) 2010-10-21
TWI521668B (zh) 2016-02-11
TW201130101A (en) 2011-09-01

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