EP2555235B1 - Procédé de fabrication de CI comportant plusieurs transistors bipolaires et CI comportant plusieurs transistors bipolaires - Google Patents

Procédé de fabrication de CI comportant plusieurs transistors bipolaires et CI comportant plusieurs transistors bipolaires Download PDF

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Publication number
EP2555235B1
EP2555235B1 EP11176278.7A EP11176278A EP2555235B1 EP 2555235 B1 EP2555235 B1 EP 2555235B1 EP 11176278 A EP11176278 A EP 11176278A EP 2555235 B1 EP2555235 B1 EP 2555235B1
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Prior art keywords
layer
emitter
emitter cap
cap layer
forming
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German (de)
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EP2555235A1 (fr
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Hans Mertens
Johannes Josephus Theodorus Marinus Donkers
Evelyne Gridelet
Tony Vanhoucke
Petrus Hubertus Cornelis Magnee
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NXP BV
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NXP BV
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Priority to US13/560,517 priority patent/US8901669B2/en
Priority to CN201210270055.5A priority patent/CN102915964B/zh
Publication of EP2555235A1 publication Critical patent/EP2555235A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H10D84/642—Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs

Definitions

  • the present invention relates to manufacturing an integrated circuit comprising a plurality of bipolar transistors including first type and second type bipolar transistors, the method comprising providing a substrate comprising a plurality of first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of said bipolar transistors and forming a base layer stack over said substrate.
  • the present invention further relates to an IC manufactured in this manner.
  • CMOS complementary metal oxide semiconductor
  • CMOS transistors limit the usefulness of CMOS transistors in RF applications unless costly measures are implemented in the CMOS process to improve these characteristics. Such costly measures typically prohibit the use of RF-CMOS technologies for manufacturing small volume devices such as analog mixed signal (AMS) devices. For these reasons, efforts have been made to produce bipolar transistors using a CMOS process flow, thereby providing mixed technology ICs in which bipolar transistors can be used for handling RF signals.
  • An example of such an IC is provided in WO2010/066630 A1 .
  • CMOS process flow An example of a low-complexity IC including a heterojunction bipolar transistor formed in a CMOS process flow can for instance be found in WO 2003/100845 A1 .
  • FIG. 1 An example of such a bipolar transistor is shown in FIG. 1 , and comprises a silicon substrate 10 including an active region 11 in which the collector of the bipolar transistor is formed, e.g. by provision of a buried layer in the substrate 10 or by implantation of an impurity into the substrate 10.
  • the active region 11 is defined in between isolation regions 12, e.g. shallow trench isolation (STI) regions.
  • the bipolar transistor further comprises a layer stack including an epitaxially grown base layer, which grows as a monocrystalline region 14 over the silicon substrate 10 and as a polycrystalline region 14' over the isolation regions 12.
  • a nitride layer may be present on the isolation regions 12 to promote epitaxial growth of the base layer portion 14'.
  • a polysilicon base contact layer 16 is present on the base layer, which is covered by an electrically insulating layer 18.
  • An emitter window 28 is defined over the active region 11, in which an emitter material 24 is formed, e.g. As-doped polysilicon, which is electrically insulated from the base contact layer 16 by sidewall spacers 22 in the emitter window 28 and by the electrically insulating layer 18 for the emitter material 24 deposited outside the emitter window 28, e.g. the emitter contact.
  • the emitter material 24 is electrically insulated from the intrinsic base region 14 by further electrically insulation portions 20. The outdiffusion 26 of the emitter 24 is surrounded by these portions 20.
  • a complication in such mixed CMOS and bipolar transistor devices occurs when the device requires bipolar transistors for different purposes, such as high frequency as well as high voltage application domains.
  • the optimized design parameters of a bipolar transistor for high frequency applications tend to differ from the optimized design parameters of a bipolar transistor for high voltage applications, as the increase in current gain that is desirable for high frequency applications, as it enables high cut-off frequencies and improved noise performance, is typically accompanied by a reduction in breakdown voltage, i.e. the open-base breakdown voltage BV CEO , due to the increased collector current density, which is highly undesirable in high voltage applications.
  • BV CEO open-base breakdown voltage
  • the present invention seeks to provide a method for manufacturing an IC comprising bipolar transistors optimized for high frequency and high voltage applications respectively, as recited in claim 1.
  • the present invention seeks to provide an IC comprising bipolar transistors optimized for high frequency and high voltage applications respectively, as recited in claim 11.
  • a method of manufacturing an integrated circuit comprising a plurality of bipolar transistors including a first type bipolar transistor and a second type bipolar transistor, the method comprising providing a substrate comprising a plurality of first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of said bipolar transistors; forming a base layer stack over said substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different to the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of said bipolar transistors.
  • the present invention is based on the insight that by tuning the effective thickness of the emitter cap layer that vertically separates the base from the emitter, the collector current of the heterojunction bipolar transistor can be tuned over a wide range, e.g. up to a factor 7.
  • An increase in effective thickness increases the thickness of the part of the emitter cap layer that forms part of the base, i.e. the part of the emitter cap layer that is not doped by the impurities in the emitter material deposited over the emitter cap layer, e.g. in an anneal or activation step. Consequently, by tuning the thickness of the emitter cap layer, the performance characteristics of the different types of heterojunction bipolar transistors, e.g. bipolar transistors for high frequency applications and bipolar transistors for high voltage applications can be individually tuned.
  • Such individual tuning may be established in a number of ways.
  • the steps of forming an emitter cap layer of a first effective thickness and a second effective thickness comprise simultaneously growing the first emitter cap layer and the second emitter cap layer to a first thickness; selectively forming an epitaxial growth inhibiting layer over the first emitter cap layer; epitaxially growing the second emitter cap layer to a second thickness; and removing the epitaxial growth inhibiting layer from over the first emitter cap layer.
  • growth rates of e.g. epitaxially grown Si layers can be accurately controlled, it is possible to accurately control the relative thickness of the first and second emitter cap layers at the cost of a single additional mask in the manufacturing process for selectively forming the epitaxial growth inhibiting layer such as an oxide layer.
  • the method further comprises selectively forming an epitaxial growth inhibiting layer over the base layer stack in the areas of the first type bipolar transistor, and wherein the steps of forming the first emitter cap layer and the second emitter cap layer comprise epitaxially growing the second emitter cap layer over the base layer stack in an area of a second type bipolar transistor to an intermediate thickness; removing the epitaxial growth inhibiting layer; and simultaneously growing the first emitter cap layer to a first thickness and the second emitter cap layer to a second thickness, which also has the advantage of being able to accurately control the relative thickness of the first and second emitter cap layers at the cost of a single additional mask in the manufacturing process.
  • the steps of forming the first emitter cap layer and the second emitter cap layer comprise simultaneously forming the first emitter cap layer and the second emitter cap layer to a second thickness; selectively oxidizing the first emitter cap layer up to a first thickness; and removing the oxidized part of the first emitter cap layer.
  • This has the advantage that the emitter cap layers can be grown in a single step. This may be achieved by providing a patterned oxidation protection mask over the second emitter cap layer prior to said selective oxidation step; and removing the patterned oxidation protection mask following said selective oxidation step, in which case a single additional mask is required in the manufacturing process for patterning the oxidation protection layer which for instance may be a nitride layer.
  • this may be achieved by the method further comprising between said simultaneously forming step and said selectively oxidizing step forming a further layer stack over the first emitter cap layer and the second emitter cap layer; forming a plurality of emitter windows in said further layer stack, exposing the first emitter cap layers and the second emitter cap layers; lining said emitter windows with a nitride layer; selectively implanting a SIC impurity into the active region of the first type of bipolar transistor through a mask; and selectively removing the nitride layer from the emitter windows over said first emitter caps using said mask.
  • This embodiment has the advantage that no additional mask is required as the SIC implant mask is reused for the selective removal of the nitride layer.
  • the steps of forming the first emitter cap layer and the second emitter cap layer comprise simultaneously forming the first emitter cap layer and the second emitter cap layer to a second thickness; forming a further layer stack over the first emitter cap layer and the second emitter cap layer; forming a plurality of emitter windows in said further layer stack, exposing the first emitter cap layers and the second emitter cap layers; masking the emitter windows of the second type of bipolar transistors; and implanting an impurity into an upper region of the first emitter cap layers to reduce the effective thickness of the first emitter cap layers to the first effective thickness.
  • This embodiment relies on converting part of the emitter cap layer into an emitter layer portion by implanting an impurity such as arsenic into part of the emitter cap layer.
  • the masking step comprising depositing a patterned resist layer covering the second emitter cap layers.
  • said masking step may comprise lining said emitter windows with a nitride layer; selectively implanting the impurity into the first emitter caps through a mask; and selectively removing the nitride layer from the emitter windows over said first emitter caps using said mask.
  • the step of forming the base layer stack comprises forming a buffer layer over the substrate and forming a carbon-doped SiGe layer over the buffer layer.
  • an integrated circuit having a substrate comprising a plurality of bipolar transistors including a first type bipolar transistor and a second type bipolar transistor; the first type bipolar transistor comprising a collector region formed in an active region in between adjacent insulation regions in the substrate, a base layer stack over said active region and an emitter separated from said base layer stack by a first emitter cap layer of a first effective thickness; and the second type bipolar transistor comprising a collector region formed in an active region in between adjacent insulation regions in the substrate, a base layer stack over said active region and an emitter separated from said base layer stack by a second emitter cap layer of a second effective thickness different to the first effective thickness.
  • Such an IC has the advantage that it comprises individually optimized bipolar transistors for different types of applications in a single substrate, thus improving the performance of the IC in general and of the bipolar transistors in particular.
  • the first type bipolar transistor comprises a collector profile that is different to the collector profile of the second type of bipolar transistor. This further improves the individualized optimization of the performance of each type of bipolar transistor for its chosen application domain.
  • the emitter of the first type of bipolar transistor comprises an first impurity profile extending from the base layer and a second impurity profile of an opposite impurity type extending from the first impurity profile to the emitter, such that the first impurity profile has the first thickness.
  • the substrate further comprises a plurality of complementary metal oxide semiconductor field effect transistors, as the various embodiments of the present invention are particularly suited to forming heterojunction bipolar transistors in a CMOS manufacturing process.
  • the method of the present invention may be applied to the manufacture of any suitable bipolar transistor.
  • An embodiment of the manufacturing method of the present invention will now be explained in more detail for a particular heterojunction bipolar transistor by way of non-limiting example only.
  • the skilled person will understand that the principles of the present invention may be applied to any bipolar transistor design that comprises a vertical layer stack in which an emitter is laterally separated from a polysilicon base layer, as will become apparent from the following description.
  • bipolar transistor' refers to a bipolar transistor having a particular layout or construction, which has been chosen based on the application domain in which the bipolar transistor is to operate.
  • bipolar transistors realized in the same technology, i.e. in the same semiconductor substrate, for which different operational parameters have been achieved by way of design variations between the bipolar transistors.
  • HBTs heterojunction bipolar transistors
  • the base-emitter profiles of high voltage and high frequency HBTs in a single BiCMOS technology are typically identical, such that optimization of the vertical base-emitter profile for one application domain negatively affects the other application domain.
  • the present invention is based on the realization that collector current density may be tuned by variation of the vertical width of the base, i.e. the thickness of the base between the collector region and the emitter.
  • the present invention provides embodiments of a manufacturing method in which the base width may be varied between different types of HBTs with minimal additional processing steps, thus making the method of the present invention commercially attractive due to its minimal cost implications.
  • FIG. 2 shows that, for two different thicknesses of a so-called silicon emitter cap, which is the silicon layer that is epitaxially grown on top of a base layer such as a SiGe:C layer, the collector current of the SiGe:C HBT under consideration is modified considerably, i.e. by a factor 7 in the ideal range. This translates into a DC current gain modification by the same factor for a fixed base current.
  • FIG. 3 explains the origin of the difference in collector current.
  • the electron potential in the base which depends on both the doping concentration and the band gap of the host material, is both relatively wide and high for the transistor with the thick emitter cap, because in this case a larger part of the emitter cap contributes to the base, i.e. the part that is not overdoped by the arsenic from the emitter such as a polysilicon emitter that is deposited on top of the emitter cap.
  • the larger band gap of silicon with respect to SiGe explains the higher electron potential in the silicon despite the lower boron concentration (grey dots).
  • the collector current could be further increased if the thickness of the emitter cap is reduced further from 35 nm to 20 - 25 nm. In that way, the parasitic potential barrier can be eliminated completely.
  • collector current density of high-voltage devices could in principle be made smaller than the collector current density of the high-speed devices by implementing a thicker emitter cap for the high-voltage devices compared to the high-speed devices, e.g. 50 nm versus 35 nm. In practice, this can be done in multiple ways.
  • bipolar transistors to be present in a single semiconductor substrate or die are shown adjacent to each other.
  • the left hand bipolar transistor may provide an example of a transistor to be optimized for high frequency applications whereas the right hand bipolar transistor may provide an example of a transistor to be optimized for high voltage applications.
  • a first embodiment of the method of the present invention is shown in FIG. 4 .
  • a substrate 10 including an active region 11 in between isolation regions 12 such as shallow trench isolation regions is provided for both types of HBT formed in this substrate 10.
  • the active region typically comprises a collector region, e.g. a buried collector formed by a buried layer grown epitaxially in the substrate 10 or an implanted collector. Any suitable implementation of the collector may be contemplated.
  • the collector may be optimized for the type of HBT, e.g. by using selectively implanted collector regions under the intrinsic base of certain types of bipolar transistors to retard the on-set of the base push-out (also known as the Kirk effect), different impurity profiles for different types of HBT to tune the collector characteristics in accordance with the requirements of the desired application domain. This may for instance be achieved by using different mask sets for the formation of the collector regions of the different types of bipolar transistors.
  • a patterned nitride layer may optionally be formed over the isolation regions 12, whilst leaving exposed the active region 11.
  • a base layer stack 14 may be epitaxially grown, resulting in monocrystalline base layer portions growing on the exposed regions of the monocrystalline substrate 10 including the active region 11 and polycrystalline base layer portions on amorphous or polycrystalline surfaces such as the isolation regions 12 or the nitride layer over the isolation regions 12 if present.
  • the base layer stack 14 comprises a Si/SiGe:C layer stack, which by way of non-limiting example may be formed as follows. Prior to the growth of the epitaxial base layer, the exposed silicon surfaces may be passivated by a hydrogen bake. The base layer is formed by first growing an undoped Si buffer layer, followed by the growth of an undoped SiGe:C collector-base spacer, a boron-doped SiGe:C base and an undoped SiGe:C base-emitter spacer. The base layer stack 14 is typically completed by a Si emitter cap 14', which is grown to a first thickness, e.g. 35 nm, for both bipolar transistors.
  • a Si emitter cap 14' is grown to a first thickness, e.g. 35 nm, for both bipolar transistors.
  • the emitter cap layer 14' forms an extension of the base of the bipolar transistor and is therefore typically doped with the same type of impurity as the base layer 14, e.g. a p-type impurity for a NPN transistor or a n-type impurity for a PNP transistor.
  • the carbon content in the SiGe layers preferably is around 0.2% and the germanium content is preferably around 20% in these layers.
  • the carbon in the SiGe:C layers prevents the outdiffusion of boron impurities from the boron-doped base, as is known per se.
  • the exact composition and structure of the base in the bipolar transistor of the present invention is not important; any suitable base construction may be chosen.
  • the emitter cap 14' of one of the transistor types is protected by a dielectric layer 30 to inhibit the epitaxial growth of silicon on the emitter cap 14.
  • a suitable embodiment of the layer 30 is SiO 2 or a similar oxide.
  • Such a pattern of dielectric layers 30 may be achieved by the addition of a non-critical mask to the mask set of the manufacturing process of the IC comprising the bipolar transistors.
  • the emitter cap 14 of the type of bipolar transistor not protected by the dielectric layer 30 is subsequently grown to a second thickness, e.g. 50 nm, after which the dielectric layer 30 is removed from the first type of bipolar transistors in any suitable manner, e.g. using a wet etch such as a HF etch, leading to the first type of bipolar transistors shown on the left hand side of FIG. 4 having an emitter cap 14' of a first thickness and the second type of bipolar transistors shown on the right hand side of FIG. 4 having an emitter cap 14' of a second thickness that is different to, e.g. larger than, the first thickness.
  • a wet etch such as a HF etch
  • the bipolar transistor may be finalized in any suitable manner. For instance, a region of the base layer stack may be protected by an etch stop layer portion 20, after which a polysilicon base contact layer 16 and a dielectric layer 18 such as a TEOS layer may be grown over the base layer stack 14 including the emitter cap layer 14'.
  • the TEOS layer electrically insulates the base contact layer from the emitter contact.
  • An emitter window 28 may be formed in the polysilicon base contact layer 16 stopping on the etch stop layer portion 20, after which sidewall spacers 22, e.g. oxide sidewall spacers or oxide-nitride-oxide (ONO) sidewall spacers are formed inside the emitter window 28, followed by the formation of a doped emitter layer 24 over the resulting structure.
  • sidewall spacers 22 e.g. oxide sidewall spacers or oxide-nitride-oxide (ONO) sidewall spacers are formed inside the emitter window 28, followed by the formation of a doped emitter layer 24 over the resulting structure.
  • Part of the base contact layer 16 is subsequently exposed and the exposed part of the base contact layer 16 and the emitter layer 16 is converted into silicide 32, after which emitter contacts 34 and base contacts 36 are formed.
  • the dielectric layer portion 30 is formed on the first type of bipolar transistor after forming the emitter cap 14' to a first thickness, it is equally feasible to form the dielectric layer portion 30 on the first type of bipolar transistor prior to formation of the emitter cap 14', i.e. on the base layer stack 14.
  • T2 is the second thickness
  • T1 is the intended thickness of the emitter cap 14' on the first type of bipolar transistor.
  • the dielectric layer portion 30 is subsequently removed, e.g.
  • a wet etch such as a HF etch, after which the emitter cap 14' on the first type of bipolar transistor is grown to T1, and the thickness of the emitter cap 14' on the second type of transistor is grown from T(i) to T(i) + T1, which equals T2.
  • FIG. 5 An alternative embodiment to tune the thickness of the silicon emitter cap 14' is shown in FIG. 5 .
  • the substrate 10 includes active (collector) regions 11 in between isolation regions 12 such as shallow trench isolation regions is provided for both types of HBT formed in this substrate 10.
  • a base layer stack 14 may be epitaxially grown, resulting in monocrystalline base layer portions growing on the exposed regions of the monocrystalline substrate 10 including the active region 11 and polycrystalline base layer portions on amorphous or polycrystalline surfaces such as the isolation regions 12 or the nitride layer over the isolation regions 12 if present.
  • the emitter cap layer 14' is grown to the second thickness, i.e. the larger thickness on both types of bipolar transistors, after which the thickness of the first type of bipolar transistor shown on the left hand side of FIG. 5 is reduced.
  • an oxide layer 40 and a nitride layer 42 are formed on the second type of bipolar transistor shown on the right hand side of FIG. 5 .
  • This may be achieved by forming the oxide and nitride stack over the whole substrate 10 and selectively removing this stack from the first type of bipolar transistors, thus exposing the emitter cap layer 14' of these transistors only.
  • the exposed emitter cap layers 14' are subsequently partially oxidized as indicated by layer 44, thereby reducing the thickness of the emitter cap layers 14' of the first type of bipolar transistors. This may for instance be achieved usingrapid thermal oxidation.
  • the oxidation process should be tuned such as to prevent or at least limit enhanced diffusion of impurities, e.g. boron, in the base layer stack 14.
  • the nitride layer 42 is subsequently removed followed by the removal of the oxide layers 40 and 44 from the second type of bipolar transistor and the first type of bipolar transistor respectively, thus yielding different types of bipolar transistor with different emitter cap layer 14' thicknesses, after which the bipolar transistors may be completed as shown in FIG. 4 .
  • An alternative embodiment of the selective emitter cap layer 14' oxidation process utilizes a HBT design in which a selectively implanted collector (SIC) is formed underneath the intrinsic base region after the epitaxial growth of the base layer stack 14 and the emitter cap 14' in the bipolar transistors of the first type, e.g. high speed bipolar transistors.
  • FIG. 6 shows the manufacturing process of an IC comprising different type of bipolar transistors following the opening of the emitter window 28 in the base contact poly 16 and the dielectric layer 18, e.g. TEOS layer 18 over the active region 11, with the emitter cap layer 14' being protected by an etch stop layer portion 20.
  • the silicon emitter cap layers 14' of both types of bipolar transistors are grown to the second thickness.
  • an oxide layer 40 and a nitride layer 42 stack is formed over the whole substrate 10 and selectively removed together with the etch stop layer 20 from the emitter window 28 of the first type of bipolar transistors only, thus exposing the emitter cap layer 14' of these transistors only.
  • the exposed emitter cap layers 14' are partially oxidized in the same manner as already explained in the context of FIG. 5 , as demonstrated by the oxide layer portion 44 on top of the reduced thickness emitter cap layers 14' of the first type of bipolar transistor shown on the left hand side of FIG. 6 , after which the nitride layer 42 is subsequently removed followed by the removal of the oxide layers 40 and 44 from the second type of bipolar transistor and the first type of bipolar transistor respectively, thus yielding different types of bipolar transistor with different emitter cap layer 14' thicknesses at least over the respective active regions 11 of these bipolar transistors as indicated by the double arrows, after which the bipolar transistors may be completed as shown in FIG. 4 .
  • the advantage of this embodiment is that the SIC implantation mask can be used for the partial oxidation of the emitter cap layer 14' of the first type of bipolar transistor, such that no additional mask is required to differentiate the thicknesses of the emitter cap layers 14' of the different types of bipolar transistors.
  • the first type of bipolar transistor comprises a silicon emitter cap layer 14' having a region over the active region 11 and the base layer 14 that has a smaller thickness than the thickness of the silicon emitter cap layer 14' of the second type of bipolar transistors in the same location.
  • the thickness of the silicon emitter cap layer 14' in the region over the active region 11 and the base layer 14, i.e. in between the emitter layer 24 and the base layer 14 is also referred to as the effective thickness of the emitter cap layer 14'.
  • the electrical properties of the emitter cap layer 14' may be altered by implanting an impurity into an emitter cap layer 14' having a thickness larger than the first thickness, wherein the implantation depth of the impurity reduces the effective thickness of the emitter cap layer 14' to the first thickness.
  • this impurity is the same impurity used to set the properties of the emitter layer 24, such that this part of the emitter cap layer 14' is converted into an extension of the emitter layer 24.
  • FIG. 7 depicts the manufacturing process of an IC comprising different type of bipolar transistors following the opening of the emitter window 28 in the base contact poly 16 and the dielectric layer 18, e.g. TEOS layer 18 over the active region 11, with the emitter cap layer 14' being protected by an etch stop layer portion 20, and the subsequent formation of side wall spacers 22 in the emitter window 28 to electrically insulate the emitter layer 24 from the base contact layer 16.
  • the silicon emitter cap layers 14' of both types of bipolar transistors are grown to the second thickness.
  • the emitter windows of the second type of bipolar transistors shown on the right hand side of FIG. 7 are subsequently protected by a resist layer 60, after which an impurity 62 is implanted into the exposed emitter cap layers 14' of the first type bipolar transistors shown on the left hand side of FIG. 7 .
  • the impurity is implanted to a depth such that the effective thickness of the exposed emitter cap layer 14' is reduced to the first thickness.
  • suitable impurities will be immediately apparent to the skilled person. For instance, n-type impurities such as arsenic and phosphorous or p-type impurities such as boron may be used.
  • the resist 60 is subsequently removed after which the bipolar transistors may be completed as shown in FIG. 4 or in any other suitable manner.
  • the resultant structure is shown in FIG. 8 , where the reduction in effective thickness of the emitter cap layer 14' for the first type of bipolar transistors by the presence of the implanted impurity 62 in the emitter cap layer 14' is demonstrated by the double arrows indicating the width, i.e. thickness, of the emitter cap layer 14' of each type of bipolar transistor.
  • the impurity 62 may be implanted prior to the formation of the sidewall spacers 22, e.g. using the same mask as used for the SIC implant as described in FIG. 6 .
  • the steps as shown in FIG. 6 may be followed with the difference that part of the emitter cap layer 14' is not oxidized but an impurity 62 is implanted into the emitter cap layer 14' instead.
  • the SIC implantation mask may be reused for the implantation of the impurity 62, thus yielding a manufacturing method of an IC comprising different types of bipolar transistors for which no additional masks are required.
  • the IC manufacturing process preferably is a CMOS process in which both MOSFETs and bipolar transistors are integrated into the same IC.
  • CMOS process in which both MOSFETs and bipolar transistors are integrated into the same IC.
  • BiCMOS process typically comprises process steps dedicated to forming aspects of the MOSFETs and process steps dedicated to forming aspects of the bipolar transistors, as well as process steps in which aspects of both MOSFET and bipolar transistors are formed simultaneously.

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Claims (15)

  1. Procédé de fabrication d'un circuit intégré comprenant une pluralité de transistors bipolaires comportant un transistor bipolaire d'un premier type et un transistor bipolaire d'un deuxième type, le procédé comprenant :
    l'obtention d'un substrat (10) comprenant une pluralité de premières régions d'isolation (12), chacune séparée d'une deuxième région d'isolation par une région active (11) comprenant une impureté de collecteur de l'un desdits transistors bipolaires ;
    la formation d'un empilement de couches de base (14) par-dessus ledit substrat ;
    la formation d'une première couche d'encapsulation d'émetteur (14') d'une première épaisseur effective par-dessus l'empilement de couches de base dans les zones du transistor bipolaire du premier type ;
    la formation d'une deuxième couche d'encapsulation d'émetteur (14') d'une deuxième épaisseur effective différente de la première épaisseur effective par-dessus l'empilement de couches de base dans les zones du transistor bipolaire du deuxième type ; et
    la formation d'un émetteur (24) par-dessus la couche d'encapsulation d'émetteur de chacun desdits transistors bipolaires.
  2. Procédé selon la revendication 1, dans lequel les étapes de formation d'une couche d'encapsulation d'émetteur (14') d'une première épaisseur effective et d'une deuxième épaisseur effective comprennent :
    la croissance simultanée de la première couche d'encapsulation d'émetteur et de la deuxième couche d'encapsulation d'émetteur jusqu'à une première épaisseur ;
    la formation sélective d'une couche d'inhibition de croissance épitaxiale (50) par-dessus la première couche d'encapsulation d'émetteur ;
    la croissance épitaxiale de la deuxième couche d'encapsulation d'émetteur jusqu'à une deuxième épaisseur ; et
    le retrait de la couche d'inhibition de croissance épitaxiale au-dessus de la première couche d'encapsulation d'émetteur.
  3. Procédé selon la revendication 1, comprenant en outre la formation sélective d'une couche d'inhibition de croissance épitaxiale (50) par-dessus l'empilement de couches de base (14) dans les zones du transistor bipolaire du premier type, et dans lequel les étapes de formation de la première couche d'encapsulation d'émetteur (14') et de la deuxième couche d'encapsulation d'émetteur (14') comprennent :
    la croissance épitaxiale de la deuxième couche d'encapsulation d'émetteur par-dessus l'empilement de couches de base dans une zone d'un transistor bipolaire du deuxième type jusqu'à une épaisseur intermédiaire ;
    le retrait de la couche d'inhibition de croissance épitaxiale ; et
    la croissance simultanée de la première couche d'encapsulation d'émetteur jusqu'à une première épaisseur et de la deuxième couche d'encapsulation d'émetteur jusqu'à une deuxième épaisseur.
  4. Procédé selon la revendication 1, dans lequel les étapes de formation de la première couche d'encapsulation d'émetteur (14') et de la deuxième couche d'encapsulation d'émetteur (14') comprennent :
    la formation simultanée de la première couche d'encapsulation d'émetteur et de la deuxième couche d'encapsulation d'émetteur jusqu'à la deuxième épaisseur ;
    l'oxydation sélective de la première couche d'encapsulation d'émetteur jusqu'à une première épaisseur ; et
    le retrait de la partie oxydée (44) de la première couche d'encapsulation d'émetteur.
  5. Procédé selon la revendication 4, comprenant en outre :
    l'application d'un masque de protection contre l'oxydation à motif (40, 42) par-dessus la deuxième couche d'encapsulation d'émetteur (14') avant ladite étape d'oxydation sélective ; et
    le retrait du masque de protection contre l'oxydation à motif après ladite étape d'oxydation sélective.
  6. Procédé selon la revendication 4, comprenant en outre, entre ladite étape de formation simultanée et ladite étape d'oxydation sélective :
    la formation d'un empilement de couches supplémentaire (16, 18) par-dessus la première couche d'encapsulation d'émetteur (14') et la deuxième couche d'encapsulation d'émetteur (14') ;
    la formation d'une pluralité de fenêtres émettrices (28) dans ledit empilement de couches supplémentaire, exposant les premières couches d'encapsulation d'émetteur et les deuxièmes couches d'encapsulation d'émetteur ;
    le revêtement desdites fenêtres émettrices avec une couche de nitrure (42) ;
    l'implantation sélective d'une impureté SiC dans la région active du transistor bipolaire du premier type à travers un masque ; et
    le retrait sélectif de la couche de nitrure des fenêtres émettrices par-dessus lesdites premières encapsulations d'émetteur à l'aide dudit masque.
  7. Procédé selon la revendication 1, dans lequel les étapes de formation de la première couche d'encapsulation d'émetteur (14') et de la deuxième couche d'encapsulation d'émetteur (14') comprennent :
    la formation simultanée de la première couche d'encapsulation d'émetteur et de la deuxième couche d'encapsulation d'émetteur jusqu'à une deuxième épaisseur ;
    la formation d'un empilement de couches supplémentaire (16, 18) par-dessus la première couche d'encapsulation d'émetteur et la deuxième couche d'encapsulation d'émetteur ;
    la formation d'une pluralité de fenêtres émettrices (28) dans ledit empilement de couches supplémentaire, exposant les premières couches d'encapsulation d'émetteur et les deuxièmes couches d'encapsulation d'émetteur ;
    le masquage des fenêtres émettrices des transistors bipolaires du deuxième type ; et
    l'implantation d'une impureté (62) dans une région supérieure des premières couches d'encapsulation d'émetteur pour réduire l'épaisseur effective des premières couches d'encapsulation d'émetteur à la première épaisseur effective.
  8. Procédé selon la revendication 7, dans lequel l'étape de masquage comprend le dépôt d'une couche de réserve à motif (60) recouvrant les deuxièmes couches d'encapsulation d'émetteur (14').
  9. Procédé selon la revendication 7, dans lequel ladite étape de masquage comprend :
    le revêtement desdites fenêtres émettrices avec une couche de nitrure (42) ;
    l'implantation sélective d'une impureté SiC dans la région active (11) du transistor bipolaire du premier type à travers un masque ; et
    le retrait sélectif de la couche de nitrure des fenêtres émettrices (28) par-dessus lesdites premières encapsulations d'émetteur à l'aide dudit masque.
  10. Procédé selon l'une quelconque des revendications précédentes, dans lequel l'étape de formation de l'empilement de couches de base (14) comprend la formation d'une couche tampon par-dessus le substrat et la formation d'une couche de SiGe dopée au carbone par-dessus la couche tampon.
  11. Circuit intégré ayant un substrat (10) comprenant une pluralité de transistors bipolaires comportant un transistor bipolaire d'un premier type et un transistor bipolaire d'un deuxième type ;
    le transistor bipolaire du premier type comprenant une région de collecteur formée dans une région active (11) entre des régions d'isolation adjacentes (12) dans le substrat, un empilement de couches de base (14) par-dessus ladite région active et un émetteur (24) séparé dudit empilement de couches de base par une première couche d'encapsulation d'émetteur (14') d'une première épaisseur effective ; et
    le transistor bipolaire du deuxième type comprenant une région de collecteur formée dans une région active (11) entre des régions d'isolation adjacentes dans le substrat, un empilement de couches de base (14) par-dessus ladite région active et un émetteur (24) séparé dudit empilement de couches de base par une deuxième couche d'encapsulation d'émetteur (14') d'une deuxième épaisseur effective différente de la première épaisseur effective.
  12. Circuit intégré selon la revendication 11, dans lequel le transistor bipolaire du premier type comprend un profil de collecteur qui est différent du profil de collecteur du deuxième type de transistor bipolaire.
  13. Circuit intégré selon la revendication 11 ou 12, dans lequel l'émetteur (24) du premier type de transistor bipolaire comprend un premier profil d'impureté (62) s'étendant depuis la couche de base et un deuxième profil d'impureté d'un type d'impureté opposé s'étendant depuis le premier profil d'impureté jusqu'à l'émetteur, de telle sorte que le premier profil d'impureté a la première épaisseur.
  14. Circuit intégré selon l'une quelconque des revendications 11 à 13, dans lequel l'empilement de couches de base (14) comprend une couche de SiGe dopée au carbone, et dans lequel les premières couches d'encapsulation d'émetteur (14') et les deuxièmes couches d'encapsulation d'émetteur (14') comprennent une couche de Si.
  15. Circuit intégré selon l'une quelconque des revendications 11 à 14, dans lequel le substrat (10) comprend en outre une pluralité de transistors à effet de champ à semi-conducteur à oxyde de métal complémentaire.
EP11176278.7A 2011-08-02 2011-08-02 Procédé de fabrication de CI comportant plusieurs transistors bipolaires et CI comportant plusieurs transistors bipolaires Active EP2555235B1 (fr)

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US13/560,517 US8901669B2 (en) 2011-08-02 2012-07-27 Method of manufacturing an IC comprising a plurality of bipolar transistors and IC comprising a plurality of bipolar transistors
CN201210270055.5A CN102915964B (zh) 2011-08-02 2012-07-31 制造包括多个双极晶体管的ic的方法和包括多个双极晶体管的ic

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US10134637B1 (en) 2017-11-30 2018-11-20 Nxp Usa, Inc. Method of forming a semiconductor component having multiple bipolar transistors with different characteristics
US10784257B2 (en) * 2018-08-31 2020-09-22 Nxp B.V. Integrating silicon-BJT to a silicon-germanium-HBT manufacturing process

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EP2555235A1 (fr) 2013-02-06

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