EP2560285A2 - Konfigurierbarer zeitkontinuierlicher Sigma-Delta-Analog-Digital-Wandler - Google Patents

Konfigurierbarer zeitkontinuierlicher Sigma-Delta-Analog-Digital-Wandler Download PDF

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Publication number
EP2560285A2
EP2560285A2 EP12175266A EP12175266A EP2560285A2 EP 2560285 A2 EP2560285 A2 EP 2560285A2 EP 12175266 A EP12175266 A EP 12175266A EP 12175266 A EP12175266 A EP 12175266A EP 2560285 A2 EP2560285 A2 EP 2560285A2
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EP
European Patent Office
Prior art keywords
filter
continuous time
dac
coupled
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12175266A
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English (en)
French (fr)
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EP2560285A3 (de
Inventor
Brandt Braswell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
North Star Innovations Inc
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Freescale Semiconductor Inc
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of EP2560285A2 publication Critical patent/EP2560285A2/de
Publication of EP2560285A3 publication Critical patent/EP2560285A3/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/392—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
    • H03M3/398—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation among different converter types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H03M3/37—Compensation or reduction of delay or phase error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/464—Details of the digital/analogue conversion in the feedback path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
    • H03M3/452—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input

Definitions

  • This disclosure relates generally to analog-to-digital converters, and more specifically, to a configurable continuous time sigma delta analog-to-digital converter.
  • ADC analog-to-digital converters
  • a continuous time sigma delta ADC can use an RC, LC, gm-C, or other continuous time filter, while a discrete time sigma delta ADC can use a switched capacitor filter.
  • An accurate clock is more important for a continuous time sigma delta ADC than it is for a discrete time sigma delta ADC.
  • a continuous time sigma delta ADC is more sensitive to clock jitter.
  • a continuous time sigma delta ADC provides better accuracy, inherent anti-aliasing, and higher operating frequency than a discrete time sigma delta ADC.
  • a system needs the performance or power advantage of a continuous time sigma delta ADC and other times it does not.
  • the FIGURE illustrates, in partial block diagram form and partial schematic diagram form, a configurable continuous time sigma delta ADC.
  • a sigma delta ADC that is configurable to have either a continuous time DAC or a discrete time DAC in a feedback path.
  • the ADC feedback path can be reconfigured with a switch to use either the continuous time DAC or the discrete time DAC depending on the quality of the available clock signal.
  • an analog-to-digital converter comprising: a continuous time filter having an input terminal and an output terminal; a quantizer having an input terminal coupled to the output terminal of the continuous time filter, and a plurality of output terminals; a continuous time digital-to-analog converter (DAC) having a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal; a discrete time DAC having a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal; and a switch having a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter.
  • ADC analog-to-digital converter
  • the ADC may further comprise a delay element coupled between the plurality of output terminals of the quantizer and the plurality of input terminals of the discrete time DAC.
  • the continuous time DAC may provide a continuous time DAC pulse.
  • the discrete time DAC may be characterized as being a switched capacitor DAC.
  • the ADC may further comprise a decimation filter having a plurality of input terminals coupled to the plurality of output terminals of the quantizer filter, and a plurality of output terminals for providing a digital output.
  • the continuous time filter may be an Nth order integrator, wherein N is an integer greater than or equal to one.
  • an analog-to-digital converter comprising: a filter having an input terminal and a plurality of output terminals; a summing circuit having a plurality of input terminals coupled to the plurality of output terminals of the filter, and an output terminal; a quantizer having an input terminal coupled to the output terminal of the summing circuit, and a plurality of output terminals; a continuous time digital-to-analog converter (DAC) having a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal; a discrete time DAC having a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal; and a switch having a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, an output terminal coupled to the input terminal of the continuous time filter, and a control terminal for receiving a control signal.
  • ADC analog-to-digital converter
  • the filter may be an Nth order integrator where N is an integer.
  • the filter may be a continuous time filter, the continuous time filter characterized as being one of an RC (resistance-capacitance) filter, an LC (inductance-capacitance) filter, or a gm-C (conductance-capacitance) filter.
  • the ADC may further comprise a delay element coupled between the plurality of output terminals of the quantizer and the plurality of input terminals of the discrete time DAC.
  • the continuous time DAC may be characterized as being a continuous time return-to-zero DAC.
  • the discrete time DAC may be characterized as being a switched capacitor DAC.
  • an analog-to-digital converter comprising: a continuous time filter having an input terminal and a plurality of output terminals; a summing circuit having a plurality of input terminals coupled to the plurality of output terminals of the continuous time filter, and an output terminal; a quantizer having an input terminal coupled to the output terminal of the summing circuit, and a plurality of output terminals; a continuous time digital-to-analog converter (DAC) having a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal; a discrete time DAC having a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal; and a switch having a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter, the switch being responsive to a control signal.
  • ADC analog-to-digital converter
  • the summing circuit may comprise: a plurality of gain elements, each of the plurality of gain elements having a first input terminal corresponding to an input of the plurality of input terminals of the summing circuit, and the plurality of gain elements each having a second terminal coupled together; and an amplifier having an input terminal coupled to the second terminals of the plurality of gain elements, and an output terminal coupled to the input terminal of quantizer.
  • the continuous time filter may be an Nth order integrator, where N is an integer.
  • the continuous time DAC may be characterized as being a continuous time return-to-zero DAC.
  • the discrete time DAC may be characterized as being a switched capacitor DAC.
  • assert or “set” and “negate” (or “deassert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
  • Each signal described herein may be designed as positive or negative logic, where negative logic can be indicated by a bar over the signal name or an asterisk (*) following the name.
  • negative logic the signal is active low where the logically true state corresponds to a logic level zero.
  • positive logic the signal is active high where the logically true state corresponds to a logic level one.
  • any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.
  • Configurable ADC 10 is constructed as part of an integrated circuit using a conventional complementary metal-oxide semiconductor (CMOS) manufacturing process technology with a power supply voltage of about 1.4 volts. In another embodiment, ADC 10 can be made differently and use a different power supply voltage.
  • Configurable ADC 10 includes resistor 12, continuous time filter 14, summing circuit 16, quantizer 18, continuous time DAC 20, delay element 22, discrete time DAC 24, and switch 26.
  • continuous time filter 14 is an Nth order integrator, where N is an integer.
  • Continuous time filter 14 includes amplifiers 30, 32, and 34, resistors 36, 38, and 40, and capacitors 42, 44, and 46.
  • Summing circuit 16 includes amplifier 50 and resistors 52, 54, 56, 58, and 60.
  • Resistor 12 has a first terminal for receiving an analog input signal labeled "ANALOG INPUT", and a second terminal.
  • Filter 14 has an input connected to the second terminal of resistor 12, and first, second, third, and fourth outputs.
  • Summing circuit 16 has a first input connected to the first output of filter 14, a second input connected to the second output of filter 14, a third input connected to the third output of filter 14, and a fourth input connected to the fourth output of filter 14.
  • Quantizer 18 has an input connected to an output of summing circuit 16, and a plurality of output terminals.
  • Delay element 22 has a plurality of input terminals connected to the plurality of output terminals of quantizer 18, and a plurality of output terminals.
  • Discrete time DAC 24 has a plurality of input terminals connected to the plurality of output terminals of delay element 22, and an output terminal.
  • Continuous time DAC 20 has a plurality of input terminals connected to the plurality of output terminals of quantizer 18, and an of output terminal for providing a continuous time DAC pulse.
  • Switch 26 has a first input terminal connected to the output terminal of continuous time DAC 20, a second input terminal connected to the output terminal of discrete time DAC 24, and an output terminal connected to the input terminal of continuous time filter 14.
  • Decimation filter 28 has a plurality of input terminals connected to the plurality of output terminals of quantizer 18, and a plurality of output terminals for providing a plurality of output bits labeled "DIGITAL OUTPUT". Note that even though ADC 10 is shown with single-ended input and output terminals, one skilled in the art will know that ADC 10 can be implemented with differential inputs and/or outputs.
  • Continuous time filter 14 includes a plurality of integration stages. Feedforward paths are provided from between each of the plurality of integration stages. A first feedforward path exists from the first input terminal of resistor 12 to the first terminal of resistor 58. A second feedforward path exists from the first input terminal resistor 36 to the first input terminal of resistor 56. A third feedforward path exists from the first input terminal of resistor 38 to the first input terminal of resistor 54.
  • the number of feedforward paths depends on the number of orders of integration. In another embodiment, the number of feedforward paths and the number of orders of integration can be different. As in another embodiment, continuous time filter 14 may include feedback paths instead of feedforward paths.
  • amplifier 30 has an input terminal connected to the second terminal of resistor 12, and an output terminal.
  • Capacitor 42 has a first plate electrode connected to the input terminal of amplifier 30, and a second plate electrode connected to the output terminal of capacitor 42.
  • Resistor 36 has a first terminal connected to the output terminal of amplifier 30, and a second terminal.
  • Amplifier 32 has an input terminal connected to the second terminal of resistor 36, and an output terminal.
  • Capacitor 44 has a first plate electrode connected to the input terminal of amplifier 32, and a second plate electrode connected to the output terminal of amplifier 32.
  • Resistor 38 has a first terminal connected to the output terminal of amplifier 32, and a second terminal.
  • Amplifier 34 has an input terminal connected to the second terminal of resistor 38, and an output terminal.
  • Capacitor 46 has a first plate electrode connected to the input terminal of amplifier 34, and a second plate electrode connected to the output terminal of amplifier 34.
  • Resistor 40 has a first terminal connected to the input terminal of amplifier 32, and a second terminal connected to the output terminal of amplifier 34.
  • sigma delta ADC 10 receives analog input signal ANALOG INPUT, and in response, provides a plurality of DIGITAL OUTPUT bits that are representative of analog input signal ANALOG INPUT.
  • the number of output bits can be any number depending, at least in part, on the desired resolution. In one embodiment, the number of output bits is equal to eight. Generally, greater resolution is obtained by increasing the number of bits.
  • continuous time filter 14 receives analog input signal ANALOG INPUT and a feedback signal from switch 26. Continuous time filter 14 is implemented as an Nth order integrator, where N is an integer greater than or equal to one. As illustrated, continuous time filter 14 includes three orders of integration. In another embodiment, continuous time filter 14 can have any number of orders or integration.
  • Continuous time filter 14 provides an integrator output plus a plurality of feedforward path outputs to a plurality of inputs of summing circuit 16.
  • Each of the plurality of inputs of summing circuit 16 includes a gain element.
  • the gain elements are resistors 52, 54, 56, and 58. In another embodiment, the gain elements may be different.
  • clock signals (not shown) are received and used by each of the blocks illustrated in the FIGURE to control the analog-to-digital conversion process.
  • Quantizer 18 is implemented as a multi-bit ADC. Quantizer 18 produces a quantized discrete multi-bit output based on the input received from summing circuit 16.
  • One feedback path includes discrete time DAC 24 and a delay element 22.
  • the other feedback path includes continuous time DAC 20.
  • Discrete time DAC 24 is implemented using a switched capacitor M-bit array.
  • the switched capacitor M-bit array has relatively good clock jitter immunity because only the rising edge of the clock signal is used for charge storage and the falling edge of the clock signal is used for charge transfer. A clock signal edge is not used to stop charge transfer.
  • Discrete time DAC 24 may be used when the clock signal has relatively high jitter.
  • Continuous time DAC 20 is implemented in the illustrated embodiment using a continuous time return-to-zero DAC M-bit array. Continuous time DAC 20 requires a higher quality clock signal with relatively lower jitter than can be used with discrete time DAC 24.
  • Delay element 22 is included in some embodiments to ensure correct timing.
  • the type of output signal provided by each of the two feedback DACs is pictorially represented in relevant blocks in the FIGURE.
  • Coupled is not intended to be limited to a direct coupling or a mechanical coupling.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
EP12175266.1A 2011-08-15 2012-07-06 Konfigurierbarer zeitkontinuierlicher Sigma-Delta-Analog-Digital-Wandler Withdrawn EP2560285A3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/210,021 US8384575B1 (en) 2011-08-15 2011-08-15 Configurable continuous time sigma delta analog-to-digital converter

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US13/210,021 Previously-Filed-Application US8384575B1 (en) 2011-08-15 2011-08-15 Configurable continuous time sigma delta analog-to-digital converter
US201113210021 Previously-Filed-Application 2011-08-15

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EP2560285A2 true EP2560285A2 (de) 2013-02-20
EP2560285A3 EP2560285A3 (de) 2017-01-18

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US (1) US8384575B1 (de)
EP (1) EP2560285A3 (de)
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KR101696269B1 (ko) * 2012-08-27 2017-01-16 한국전자통신연구원 델타-시그마 변조기 및 이를 포함하는 송신장치
JP5758434B2 (ja) * 2013-05-08 2015-08-05 株式会社半導体理工学研究センター Δσａ／ｄ変換装置
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CN102957432A (zh) 2013-03-06
EP2560285A3 (de) 2017-01-18
US8384575B1 (en) 2013-02-26
JP2013042488A (ja) 2013-02-28
US20130044013A1 (en) 2013-02-21

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