EP2599112A4 - Dispositif à semi-conducteurs, et structure associée - Google Patents

Dispositif à semi-conducteurs, et structure associée Download PDF

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Publication number
EP2599112A4
EP2599112A4 EP11812914.7A EP11812914A EP2599112A4 EP 2599112 A4 EP2599112 A4 EP 2599112A4 EP 11812914 A EP11812914 A EP 11812914A EP 2599112 A4 EP2599112 A4 EP 2599112A4
Authority
EP
European Patent Office
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11812914.7A
Other languages
German (de)
English (en)
Other versions
EP2599112A2 (fr
Inventor
Zvi Or-Bach
Deepak C. Sekar
Brian Cronquist
Zeev Wurman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Monolithic 3D Inc
Original Assignee
Monolithic 3d S A
Monolithic 3D Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/847,911 external-priority patent/US7960242B2/en
Priority claimed from US12/849,272 external-priority patent/US7986042B2/en
Priority claimed from US12/859,665 external-priority patent/US8405420B2/en
Priority claimed from US12/894,252 external-priority patent/US8258810B2/en
Priority claimed from US12/900,379 external-priority patent/US8395191B2/en
Priority claimed from US12/901,890 external-priority patent/US8026521B1/en
Priority claimed from US12/904,108 external-priority patent/US8362800B2/en
Priority claimed from US12/904,119 external-priority patent/US8476145B2/en
Priority claimed from US12/941,074 external-priority patent/US9577642B2/en
Priority claimed from US12/941,075 external-priority patent/US8373439B2/en
Priority claimed from US12/941,073 external-priority patent/US8427200B2/en
Priority claimed from US12/949,617 external-priority patent/US8754533B2/en
Priority claimed from US12/951,924 external-priority patent/US8492886B2/en
Priority claimed from US12/951,913 external-priority patent/US8536023B2/en
Priority claimed from US12/970,602 external-priority patent/US9711407B2/en
Priority claimed from US13/016,313 external-priority patent/US8362482B2/en
Priority claimed from US13/041,406 external-priority patent/US9509313B2/en
Priority claimed from US13/041,405 external-priority patent/US8901613B2/en
Application filed by Monolithic 3d S A, Monolithic 3D Inc filed Critical Monolithic 3d S A
Priority to EP18195847.1A priority Critical patent/EP3460845A1/fr
Publication of EP2599112A2 publication Critical patent/EP2599112A2/fr
Publication of EP2599112A4 publication Critical patent/EP2599112A4/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/68—Floating-gate IGFETs
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
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    • H10D84/90—Masterslice integrated circuits
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    • H10D86/01—Manufacture or treatment
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    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/232—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising connection or disconnection of parts of a device in response to a measurement
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    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
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    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
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    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
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    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/211—Through-semiconductor vias, e.g. TSVs
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    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
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    • H10B12/05—Making the transistor
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    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
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  • Nanotechnology (AREA)
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  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
EP11812914.7A 2010-07-30 2011-06-28 Dispositif à semi-conducteurs, et structure associée Withdrawn EP2599112A4 (fr)

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US12/847,911 US7960242B2 (en) 2009-04-14 2010-07-30 Method for fabrication of a semiconductor device and structure
US12/849,272 US7986042B2 (en) 2009-04-14 2010-08-03 Method for fabrication of a semiconductor device and structure
US12/859,665 US8405420B2 (en) 2009-04-14 2010-08-19 System comprising a semiconductor device and structure
US12/894,252 US8258810B2 (en) 2010-09-30 2010-09-30 3D semiconductor device
US12/900,379 US8395191B2 (en) 2009-10-12 2010-10-07 Semiconductor device and structure
US12/901,890 US8026521B1 (en) 2010-10-11 2010-10-11 Semiconductor device and structure
US12/904,108 US8362800B2 (en) 2010-10-13 2010-10-13 3D semiconductor device including field repairable logics
US12/904,119 US8476145B2 (en) 2010-10-13 2010-10-13 Method of fabricating a semiconductor device and structure
US12/941,073 US8427200B2 (en) 2009-04-14 2010-11-07 3D semiconductor device
US12/941,075 US8373439B2 (en) 2009-04-14 2010-11-07 3D semiconductor device
US12/941,074 US9577642B2 (en) 2009-04-14 2010-11-07 Method to form a 3D semiconductor device
US12/949,617 US8754533B2 (en) 2009-04-14 2010-11-18 Monolithic three-dimensional semiconductor device and structure
US12/951,924 US8492886B2 (en) 2010-02-16 2010-11-22 3D integrated circuit with logic
US12/951,913 US8536023B2 (en) 2010-11-22 2010-11-22 Method of manufacturing a semiconductor device and structure
US12/970,602 US9711407B2 (en) 2009-04-14 2010-12-16 Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US13/016,313 US8362482B2 (en) 2009-04-14 2011-01-28 Semiconductor device and structure
US13/041,406 US9509313B2 (en) 2009-04-14 2011-03-06 3D semiconductor device
US13/041,405 US8901613B2 (en) 2011-03-06 2011-03-06 Semiconductor device and structure for heat removal
PCT/US2011/042071 WO2012015550A2 (fr) 2010-07-30 2011-06-28 Dispositif à semi-conducteurs, et structure associée

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WO2012015550A9 (fr) 2012-05-31
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EP3460845A1 (fr) 2019-03-27
WO2012015550A3 (fr) 2012-04-19

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