EP2807788A2 - Procédé d'écriture et de lecture de données - Google Patents
Procédé d'écriture et de lecture de donnéesInfo
- Publication number
- EP2807788A2 EP2807788A2 EP13704705.6A EP13704705A EP2807788A2 EP 2807788 A2 EP2807788 A2 EP 2807788A2 EP 13704705 A EP13704705 A EP 13704705A EP 2807788 A2 EP2807788 A2 EP 2807788A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- data
- input
- memory element
- code
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/22—Indexing; Data structures therefor; Storage structures
- G06F16/2228—Indexing structures
- G06F16/2272—Management thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0894—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
- H04L9/0897—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/127—Trusted platform modules [TPM]
Definitions
- the invention relates to a method for writing and reading data into or from an indexed database, which comprises a data structure and an associated index structure, wherein a processing unit receives data to be written in plain text and writes into the data structure by means of a write access and index data updated in the index structure and wherein the processing unit to be read data or their storage location determined by access to the index data and read the data to be read by means of a read access from the data structure and provides in plain text.
- the invention further relates to an apparatus for writing and reading data in or from an indexed database, comprising a data structure and an associated index structure, comprising a processing unit in which data to be written can be received in plain text and which has a write access to the Has data structure to write the data in the data structure, and which cooperates with the index structure to update index data in the index structure, and having an access to the index data to determine the data or their location to be read, and a read access to has the data structure to read the data to be read from the data structure and to provide in plain text.
- an indexed database is a mass storage that has an index store attached to speed up access.
- a database index is a data structure separated index structure in a database, which accelerates the search and sorting for specific fields.
- An index consists of a collection of pointers (references) that define an ordering relation to one or more columns in a table. If an indexed column is used as a search criterion in a query, a processing unit, ie usually a database management system, searches for the desired data records on the basis of these pointers. Without an index, the column would have to be searched sequentially, which takes a long time even with fast hardware.
- the invention therefore aims to provide a method and a device with which the confidentiality of the data structure and the index structure of a data set can be protected, without the access to the data using the index being impaired by authorized users is. It should maintain the full functionality of an indexed database.
- the data in the data structure and the index data in the index structure are stored encrypted and that the read / write access of the processing unit to the index structure and to the data structure via at least one Decryption unit takes place, with which the data by means of a Strortichiffr mich be encrypted or decrypted.
- the fact that the data to be written and read is encrypted or decrypted by means of a stream cipher ensures that the image of the encrypted data and the unencrypted data on the storage medium has exactly the same dimensions (bit length), so that they are also encrypted Form can be found bit accurate and can be sent to the requesting üser in ignorance of the content.
- each individual information has exactly the same dimensions (bit length) as the unencrypted also, the position of the encrypted data can be accurately accessed by an index made in unencrypted form, so that the content of the encrypted data need not be recognized by the processing unit of the database and no consideration is given to the circumstance of the encryption in the storage space search got to .
- the procedure is such that the generation of the keystream is carried out using at least one feedback shift register, which is filled with a defined bit sequence for its initialization.
- Linear feedback shift registers can be efficiently implemented both directly in hardware such as FPGAs and in software. Feedback shift registers are fast and produce pseudo-random sequences with good statistical properties.
- a feedback shift register is implemented in digital technology as a shift register with n memory elements. The individual memory elements are typically D flip-flops, which can each store one bit. In contrast to a conventional shift register exist between certain D flip-flops Branches representing the feedbacks.
- an XOR function is usually used in each case. Instead of the XOR link, however, an XNOR link can also be used.
- the shift register can be filled with XOR feedback with arbitrary values that determine the key stream generated by the shift register in the sequence.
- the feedback shift register also has a clock input: each clock pulse is changed to the next state, i. if a bit is to be output, all bits in the shift register are shifted by one memory location; the new bit at the end of the shift register is calculated depending on the other bits. This process counts as one bar. For a complete run of all combinations are
- Such a code sequence thus has a length of 2 n -l bits ⁇ n - number of code-generating series-connected memory elements of the shift register).
- a plurality of linear feedback shift registers are generally used, which are usually of different lengths and have different feedback polynomials. This combines linear feedback shift registers to non-linear generators.
- any code that is not repeated before the end of the information to be encrypted is considered to be infinite.
- a functionally infinite code has the disadvantage that it can not be transmitted; it has to be generated.
- a disadvantage of code generators in the form of herculean feedback shift registers is the fact that it is easy to deduce the structure of the generator from the code sequence, so that it can be regenerated with an identically constructed generator.
- An increase in the Si ⁇ reliability is achieved according to a preferred procedure within the scope of the invention in that for each write access by the processing unit to the struk- structure or the index structure of another key stream is used.
- the procedure is preferably such that in each case at least one first bit sequence and one second bit sequence are used to initialize the feedback shift register or feedback signals. This is done in particular when only a single feedback shift ⁇ beregister is used to generate the key stream, such that the first and the second bit sequence are linked by means of an XOR function, and the resulting from the combination of bit string for initializing the feedback shift register is supplied.
- the procedure is that at least a first feedback shift register is filled to its initialization with the first bit sequence and at least a two ⁇ tes fed back Shift register is filled to its initialization with the second bit sequence.
- the encryption of a section of the database such as a record of the database and the decryption of the same section or record are synchronized with each other, ie that the encryption and the decryption is done with the same keystream.
- the synchronization preferably takes place using the indices of the data records.
- the procedure is such that an index number assigned to the data set to be encrypted or decrypted is selected as the first bit sequence, or that the first bit success 3.11 ⁇ is generated.
- the primary index is preferably used here.
- the second bit sequence is preferably a unique identifier of the database or is generated from this.
- a third bit sequence is used for initializing the feedback shift register (s).
- the third bit sequence is advantageously a unique identifier of the respective user or is generated from this.
- the third bit sequence is preferably fed to a third feedback shift register for initialization.
- a further advantage of the method according to the invention is that the generation of the keystream can already begin as soon as at least one of the feedback shift registers is filled with the first bit from the respective bit sequence.
- the feedback shift registers are filled simultaneously with the respective bit sequence.
- the structure of the key-current generator is preferably such that at least one XOR gate is used for the feedback of the shift register or registers.
- the Complexity of the generator can be increased in a simple manner in that the feedback shift registers are interconnected in such a way that, depending on the state of a shift register, the at least one XOR gate of the other shift register is switched on or off.
- a highly preferred embodiment results when a code generator is used, as described in WO 03/075507 AI, reference being made to claims 15 and 16 and 33 to 38 of the present application.
- the encryption can not be broken even if both the structure of the code generator and the algorithm running in it are known.
- the structure of the generator is such that it is capable of generating such a large number of different codes in such a large length that the discovery of the code just used as well as the currently produced position in the code sequence is extremely small Probability is possible.
- the code can not be regenerated if the generator can create so many different codes that one section of the single code can not conclude its continuation.
- the access of a user computer to the database or the database is usually from a remote location via a data communication connection, in particular via a computer network.
- the access of a user's computer to the data structure and the index structure is carried out via the processing unit. Since the data in the processing unit is in plain text, it is advantageous to provide provisions to prevent user computers Gain access to this plain text data.
- the invention preferably provides that the data transmitted between the processing unit and a user computer is transmitted in encrypted form.
- the procedure is such that the encrypted transmission of the data between the processing unit and the user computer takes place using in each case one user computer and one data storage unit associated with the encryption and decryption unit with which the data is encrypted or decrypted by means of a stream cipher.
- a particularly safe execution is characterized ⁇ represents townge that all communication of data to and from the processing unit via at least one encryption and decryption unit takes place, with which the data be encrypted using a stream cipher and decrypted.
- the processing unit thus does not have an unencrypted input or output to / from the surrounding network, thus ensuring that the file memory of the processing unit in which the data is in plain text can not be viewed.
- a device of the aforementioned type for writing and reading data in or from an indexed database is proposed.
- the device according to the invention is characterized in that the processing unit is connected to the data structure and to the index structure via at least one encryption and decryption unit with which the data can be encrypted or decrypted by means of a stream cipher so that the read / write access of the processing unit on the index structure and on the Data structure on the at least one encryption and decryption unit.
- the processing unit is preferably designed as a CPU assigned to the data structure and the index structure.
- FIG. 2 shows the encryption and decryption process
- FIGS. 3, 4 and 5 show different embodiments of a key-flow generator used in the context of the invention.
- FIG. 1 shows a database 1 comprising a data structure 2 and an index structure 3.
- Denoted at 4 is a processing unit in the form of a CPU which has an outgoing and incoming data interface 5 and which controls write and read access to the index structure 3 and the data structure 2.
- the processing unit 4 is connected via an encryption and decryption unit 6 to the data structure 2 and via an encryption and decryption unit 7 to the index structure 3, so that the read or write access to the data structure 2 and the index structure 3 via the encryption and decryption unit 6 or 7 takes place.
- the data to be written into the data structure 2 or the index structure 3 and the data to be read from the data structure 2 or the index structure 3 are present in plain text, so that the for indexing and for the Locating records required operations can be performed.
- the data structure 2 and in the index structure 3 however, the data are available only in encrypted form.
- the processing unit 4 can access the encrypted data, the access takes place via the encryption and decryption unit 6 or 7.
- FIG. 1 the transmission of the data in plain text is represented by a solid line and the transmission of encrypted data by a dashed line ,
- the encryption and decryption units 6 and 7 encrypt and decrypt the respective data by means of stream ciphering and accordingly comprise a keystream generator, which will be explained in greater detail with reference to the various embodiments in FIGS. 2 to 5.
- a keystream generator which will be explained in greater detail with reference to the various embodiments in FIGS. 2 to 5.
- Each of the embodiments described below can be used in the context of the encryption and decryption unit 6 or 7 or the encryption and decryption unit 10 or 11 (see below).
- a user computer 8 can access the database 1 via a communication connection 9.
- the data is transmitted via the Kirunikationsverbindimg 9 in encrypted form, wherein the encryption and decryption by means of the encryption and decryption units 10 and 11 takes place.
- the encryption and decryption are preferably carried out by means of a ciphering.
- the encryption and decryption units 6, 7, 10 and 11 may each comprise a code generator according to WO 03/075507 AI, wherein the code generators of the encryption and decryption units 6 and 7 for the encryption and the subsequent decryption of data must be synchronized. Furthermore, for example, the code generators of the encryption and decryption units 10 and 11 must be synchronized with each other.
- a user searches for specific information among the data stored by him in the database 1, he enters corresponding search words in the user computer 8. This encrypts this input and transmits it to the database 1.
- this search term is decrypted by the encryption and decryption unit 11 and the processing unit 4 provided in plain text.
- the processing unit 4 searches for the search term in the index structure 3, wherein the index structure 3 of the processing unit 4 is cleartext available due to the real-time access via the encryption and decryption unit 7.
- the index structure 3 indicates the exact location of the searched data in the encrypted data structure 2. Then the encrypted data in the data structure 2 are visited and forwarded in unchanged encrypted form to the user's computer 8 of the user.
- the user computer 8 decrypts the data using the encryption and decryption unit 10, so that they are displayed there as requested plain text data.
- the encrypted data can be read from the data structure 2 via the encryption and decryption unit 6, these data then being present in plaintext in the processing unit 4 and being encrypted again with the encryption and decryption unit 11 for transmission to the user computer 8 have to .
- the synchronization of the encryption and decryption units 6 and 7 will be explained in more detail with reference to FIG. Fig. 2 shows a schematic circuit of a keystream generator 12 with a shift register 13, which consists of a plurality of to a Godeprodufugden series interconnected memory elements, namely flip-flops FF1, FF2, ... FF9 consists.
- An XOR gate XORpl is connected so that one input of the XOR gate XORpl is connected to the output of the code-producing line memory element FF2, and the other input of the XOR gate XORpl is connected to the output of the memory element in the code-producing line FF5 and the output of the XOR gate XORPL to the input of the downstream in the flow direction to the one input of the XOR gate XORPL connected memory element FF2 in the series memory element FF3 - thus recursively - is connected. It can also be seen that the last memory element FF9 is connected to the first memory element FF1 via an inverter INV.
- bit sequences 14, 15 and 16 are supplied to the shift register 13 for its initialization in such a way that first the bit sequences 14 and 15 are generated by means of a XOR gate 17 are linked together and then the linked bit sequence with the bit string 16 by means of the XOR gate 18 is linked.
- bit sequence generated from the bit sequences 14, 15 and 16 and fed to the shift register 13 is not longer than corresponds to the number of memory elements in the shift register 13, since the bit sequence otherwise differs from that via the inverter INV from the Memory elements FF9 would be superimposed coming bit sequence.
- the first bit sequence 14 corresponds to the index number of the relevant data record.
- the second bit sequence 15 corresponds to the database ID.
- the third bit sequence 16 corresponds to the "Own ID" of the user.
- the keystream generator 12 generates a keystream 19a.
- An incoming stream 19b of plaintext data is encrypted so that the bits of the plaintext bitstream 19b are individually linked to the bits of a keystream 19a by means of an XOR gate 20. If the plaintext data represent a dataset of the database 1, the index of this dataset is determined according to the structure inherent in the database and supplied as a bit sequence 14 to the keystream generator 12 as an initialization sequence.
- the stream 19b is a stream of encrypted data
- it is decrypted so that the bits of the bitstream 19b of the encrypted data are individually linked to the bits of the keystream 19a by means of an XOR gate 20.
- the encrypted data represent an encrypted data set of the database 1
- the index of this data record is determined in accordance with the inherent structuring of the database and supplied as a bit sequence 14 to the keystream generator 12 as an initialization sequence.
- a total of three shift registers 21, 22 and 23 are used.
- the shift elements of the individual shift registers are interconnected recursively in this example in the same way as in Fig. 2.
- the shift registers are further interconnected such that, depending on the state of the second shift register 22, the function of the XOR gate of the recursive interconnection of the first Shift register 21 is turned on and off.
- the function of the XOR gate XORppl the recursive connection of the second shift register 22 is in turn turned on and off in response to the state of the third shift register 23.
- a code generator 12 with three levels, wherein the code generation is influenced on each level by initializing the respective shift register 21, 22 and 23 with the bit sequence 14, 15 and 16.
- the initialization can preferably take place in such a way that the first bit sequence 14 is supplied to the shift register 21 of the first level, the second bit sequence 15 to the shift register 22 of the second level, and the third bit sequence 16 to the shift register 23 of the third level, the bit sequences 14, 15 and 16 are preferably defined as described in FIG.
- the structure shown in FIG. 3 is made even more complex and, in particular, longer code-producing series and a plurality of recursive interconnections are provided.
- a number of uninterrupted series-connected memory elements in the form of shift registers SRG1, SRG2,... are implemented, which functionally together form a shift register 24 in the sense of the invention. It doubles the length of the code per added memory element, so the length of the code is calculated as follows
- the code will run for more than a year without the sequence repeating so that a signal to be encrypted can be sent encrypted and decrypted simultaneously over a similar period of time so that broadcasts live over an equally long period of time are possible.
- an XO gate XORpl, 2, p3 is connected to a plurality of locations of this shift register 24 between a memory element FF1, 2, 3, 4 and the next in-line memory element FF2, 3, 4, 5 4 and then feeds it with the signal from a third memory element FF8, 15, 20, 23, the respective code thus generated is changed (FIG. 5).
- FF4, 23 each has a number of 7, 13, 17 and 19 (prime numbers) memory elements. If one of the two inputs of the respective XOR gate XORpl or XORpl, p2, p3, p4, the output of an AND gate ÜNDpl or ANDP1, p2, p3, p4 whose one input at the output of the memory element FF3 or FF8, 15,20,23, then one can connect this XOR gate XORpl or XORpl, p2, p3, p4 in its code-changing action via the second input of the AND gate ANDpl or 2, p3, p4.
- the code-programming memory elements FFpl, p2, p3, p4 can be combined to form a shift register 25.
- the code-programming memory elements FFpl, p2, p3, p4 of the shift register 25 can in turn be recursively interconnected with the aid of an XOR gate XORppl.
- Nc 2 pn - 1
- ⁇ Nc number of possible different codes
- pn number of programmable XOR gates XORpl, p2, ... pn)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Storage Device Security (AREA)
Abstract
L'invention concerne un procédé d'écriture de données dans un fichier indexé (1) et de lecture de données à partir de ce dernier, ledit fichier présentant une structure de données (2) et une structure d'index (3) associée. Selon ce procédé, une unité de traitement (4) reçoit des données à écrire en clair, écrit les données au moyen d'un accès d'écriture dans la structure de données (2) et actualise des données d'index dans la structure d'index (3). L'unité de traitement (4) détermine les données à extraire ou leur emplacement en mémoire au moyen d'un accès aux données d'index (3) et extrait les données à extraire au moyen d'un accès de lecture à partir de la structure de données (2) puis les met à disposition en clair. Les données dans la structure de données (2) et les données d'index dans la structure d'index (3) sont mémorisées de manière codée, l'accès de lecture/d'écriture de l'unité de traitement (4) à la structure d'index (3) et à la structure de données (2) s'effectuant par l'intermédiaire d'au moins une unité de codage et de décodage (6, 7) qui code et décode les données au moyen d'un chiffrement de flux.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ATA106/2012A AT511842B1 (de) | 2012-01-26 | 2012-01-26 | Verfahren zum schreiben und lesen von daten |
| PCT/AT2013/000010 WO2013110103A2 (fr) | 2012-01-26 | 2013-01-22 | Procédé d'écriture et de lecture de données |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP2807788A2 true EP2807788A2 (fr) | 2014-12-03 |
Family
ID=47721875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP13704705.6A Withdrawn EP2807788A2 (fr) | 2012-01-26 | 2013-01-22 | Procédé d'écriture et de lecture de données |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20150046416A1 (fr) |
| EP (1) | EP2807788A2 (fr) |
| AT (1) | AT511842B1 (fr) |
| RU (1) | RU2014134714A (fr) |
| WO (1) | WO2013110103A2 (fr) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9449178B2 (en) * | 2012-07-24 | 2016-09-20 | ID Insight | System, method and computer product for fast and secure data searching |
| US10114850B1 (en) * | 2014-09-17 | 2018-10-30 | EMC IP Holding Company LLC | Data stream generation using prime numbers |
| US10114832B1 (en) * | 2014-09-17 | 2018-10-30 | EMC IP Holding Company LLC | Generating a data stream with a predictable change rate |
| EP3428665B1 (fr) * | 2017-07-11 | 2020-03-25 | Nxp B.V. | Détection de défaillance dans les registres |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5050213A (en) * | 1986-10-14 | 1991-09-17 | Electronic Publishing Resources, Inc. | Database usage metering and protection system and method |
| TW490611B (en) * | 2000-03-31 | 2002-06-11 | Jian-Tsz Hou | Encryption and decryption memory and access control method |
| US7043017B2 (en) * | 2001-09-13 | 2006-05-09 | Freescale Semiconductor, Inc. | Key stream cipher device |
| AT412747B (de) * | 2002-03-05 | 2005-06-27 | Rene-Michael Mag Cordes | Codegenerator und vorrichtung zur synchronen oder asynchronen sowie permanenten identifikation oder ver- und endschlüsselung von daten beliebiger länge |
| US7519835B2 (en) * | 2004-05-20 | 2009-04-14 | Safenet, Inc. | Encrypted table indexes and searching encrypted tables |
| JP4750105B2 (ja) * | 2005-03-23 | 2011-08-17 | Kddi株式会社 | キーストリーム暗号化装置および方法ならびにプログラム |
| DE102006006057B4 (de) * | 2006-02-09 | 2007-12-27 | Infineon Technologies Ag | Datenverschlüsselungsvorrichtung und Verfahren zum Verschlüsseln von Daten |
| US7734969B2 (en) * | 2007-10-30 | 2010-06-08 | Infineon Technologies Ag | Feedback shift register control |
| US7945049B2 (en) * | 2008-02-28 | 2011-05-17 | Red Hat, Inc. | Stream cipher using multiplication over a finite field of even characteristic |
| US9015181B2 (en) * | 2008-09-26 | 2015-04-21 | Commvault Systems, Inc. | Systems and methods for managing single instancing data |
-
2012
- 2012-01-26 AT ATA106/2012A patent/AT511842B1/de not_active IP Right Cessation
-
2013
- 2013-01-22 RU RU2014134714A patent/RU2014134714A/ru unknown
- 2013-01-22 WO PCT/AT2013/000010 patent/WO2013110103A2/fr not_active Ceased
- 2013-01-22 EP EP13704705.6A patent/EP2807788A2/fr not_active Withdrawn
- 2013-01-22 US US14/374,423 patent/US20150046416A1/en not_active Abandoned
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2013110103A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| AT511842A4 (de) | 2013-03-15 |
| WO2013110103A3 (fr) | 2013-09-19 |
| US20150046416A1 (en) | 2015-02-12 |
| RU2014134714A (ru) | 2016-03-20 |
| AT511842B1 (de) | 2013-03-15 |
| WO2013110103A2 (fr) | 2013-08-01 |
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