EP2872986A4 - Fourniture de données devant être récupérées - Google Patents

Fourniture de données devant être récupérées

Info

Publication number
EP2872986A4
EP2872986A4 EP12880789.8A EP12880789A EP2872986A4 EP 2872986 A4 EP2872986 A4 EP 2872986A4 EP 12880789 A EP12880789 A EP 12880789A EP 2872986 A4 EP2872986 A4 EP 2872986A4
Authority
EP
European Patent Office
Prior art keywords
retrieved
providing data
providing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12880789.8A
Other languages
German (de)
English (en)
Other versions
EP2872986A1 (fr
Inventor
Vinay Avasthi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Enterprise Development LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of EP2872986A1 publication Critical patent/EP2872986A1/fr
Publication of EP2872986A4 publication Critical patent/EP2872986A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
EP12880789.8A 2012-07-12 2012-07-12 Fourniture de données devant être récupérées Withdrawn EP2872986A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2012/046514 WO2014011181A1 (fr) 2012-07-12 2012-07-12 Fourniture de données devant être récupérées

Publications (2)

Publication Number Publication Date
EP2872986A1 EP2872986A1 (fr) 2015-05-20
EP2872986A4 true EP2872986A4 (fr) 2016-03-23

Family

ID=49916443

Family Applications (1)

Application Number Title Priority Date Filing Date
EP12880789.8A Withdrawn EP2872986A4 (fr) 2012-07-12 2012-07-12 Fourniture de données devant être récupérées

Country Status (3)

Country Link
EP (1) EP2872986A4 (fr)
CN (1) CN104520808A (fr)
WO (1) WO2014011181A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682500A (en) * 1992-06-04 1997-10-28 Emc Corporation System and method for determining sequential cache data access in progress
US20050144394A1 (en) * 2003-12-24 2005-06-30 Komarla Eshwari P. For adaptive caching

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530941A (en) * 1990-08-06 1996-06-25 Ncr Corporation System and method for prefetching data from a main computer memory into a cache memory
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US20030204675A1 (en) * 2002-04-29 2003-10-30 Dover Lance W. Method and system to retrieve information from a storage device
US7555609B2 (en) * 2006-10-27 2009-06-30 Via Technologies, Inc. Systems and method for improved data retrieval from memory on behalf of bus masters
CN101046784A (zh) * 2006-07-18 2007-10-03 威盛电子股份有限公司 存储器数据存取系统与方法以及存储器控制器
US8965819B2 (en) * 2010-08-16 2015-02-24 Oracle International Corporation System and method for effective caching using neural networks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682500A (en) * 1992-06-04 1997-10-28 Emc Corporation System and method for determining sequential cache data access in progress
US20050144394A1 (en) * 2003-12-24 2005-06-30 Komarla Eshwari P. For adaptive caching

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
KADDA BEGHDAD BEY ET AL: "CPU load prediction using neuro-fuzzy and Bayesian inferences", NEUROCOMPUTING, ELSEVIER SCIENCE PUBLISHERS, AMSTERDAM, NL, vol. 74, no. 10, 16 January 2011 (2011-01-16), pages 1606 - 1616, XP028194522, ISSN: 0925-2312, [retrieved on 20110317], DOI: 10.1016/J.NEUCOM.2011.01.009 *
See also references of WO2014011181A1 *
SHIH-WEI LIAO ET AL: "Machine learning-based prefetch optimization for data center applications", HIGH PERFORMANCE COMPUTING NETWORKING, STORAGE AND ANALYSIS, PROCEEDINGS OF THE CONFERENCE ON, ACM, 14 November 2009 (2009-11-14), pages 1 - 10, XP032341247, DOI: 10.1145/1654059.1654116 *

Also Published As

Publication number Publication date
WO2014011181A1 (fr) 2014-01-16
EP2872986A1 (fr) 2015-05-20
CN104520808A (zh) 2015-04-15

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Legal Events

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Ipc: G06N 3/02 20060101ALI20160212BHEP

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Ipc: G06F 12/08 20060101ALI20160212BHEP

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: HEWLETT PACKARD ENTERPRISE DEVELOPMENT L.P.

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