EP3017461A1 - Boîtier de puce sans substrat ayant des fils à revêtements diélectrique et métallique et son procédé de fabrication - Google Patents

Boîtier de puce sans substrat ayant des fils à revêtements diélectrique et métallique et son procédé de fabrication

Info

Publication number
EP3017461A1
EP3017461A1 EP14734744.7A EP14734744A EP3017461A1 EP 3017461 A1 EP3017461 A1 EP 3017461A1 EP 14734744 A EP14734744 A EP 14734744A EP 3017461 A1 EP3017461 A1 EP 3017461A1
Authority
EP
European Patent Office
Prior art keywords
die
leads
dielectric
metal
metal core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP14734744.7A
Other languages
German (de)
English (en)
Other versions
EP3017461B1 (fr
Inventor
Sean S. Cahill
Eric A. Sanjuan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rosenberger Hochfrequenztechnik GmbH and Co KG
Original Assignee
Rosenberger Hochfrequenztechnik GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rosenberger Hochfrequenztechnik GmbH and Co KG filed Critical Rosenberger Hochfrequenztechnik GmbH and Co KG
Publication of EP3017461A1 publication Critical patent/EP3017461A1/fr
Application granted granted Critical
Publication of EP3017461B1 publication Critical patent/EP3017461B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/465—Bumps or wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/206—Wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01551—Changing the shapes of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01551—Changing the shapes of bond wires
    • H10W72/01553—Changing the shapes of bond wires by etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
    • H10W72/523—Multilayered bond wires, e.g. having a coating concentric around a core characterised by the structures of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/527—Multiple bond wires having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/553—Materials of bond wires not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/555—Materials of bond wires of outermost layers of multilayered bond wires, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to die packages with at least one die having a plurality of connection pads and a plurality of leads extending from the connection pads, the leads having metal cores with a defined core diameter and a dielectric layer surrounding the metal cores having a defined dielectric thickness, respectively.
  • packaging can be expensive, particularly if the substrate requires costly materials or precision drilling, etch, or formation of vias.
  • a die package comprising a die having a plurality of connection pads, a plurality of leads having metal cores with a defined core diameter, and a dielectric layer surrounding the metal cores having a defined dielectric thickness, at least one first connection pad held in a mold compound covering the die and the plurality of leads, the first connection pad being connected to the metal core of a first lead, and at least one second connection pad held in the mold compound covering the die and the plurality of leads, the second connection pad being connected to the metal core of a second lead.
  • the die package is preferably a "coreless" package without a permanent substrate for die attachment.
  • the die package according to the invention can be connected to a printed circuit board or to a substrate by means of solder balls, for example.
  • connection pads can be held in the mold component in such a way that they are exposed so that they can be connected to the PCB or to the substrate.
  • the connection pads are held be the overmold compound without being supported by a die substrate.
  • the first connection pad may be connected to the metal core of a first lead and the second connection pad may be connected to the metal core of a second lead, whereas the first lead is longer than the second lead, has a different core diameter and/or has a different dielectric diameter.
  • the die package can include several dies which may be arranged as stacked dies. Further, at least one of the leads may be a ribbon lead formed by total or partial fusion of the dielectric coatings of two or more leads.
  • the present invention is directed to a method of manufacturing a die package according to the invention, the method comprising the following steps: placing of one or more dies on a temporary workpiece including temporarily attached pads, using wirebonding to connect the die to the temporarily attached pads, coating of metal cores of the wirebonds with a dielectric coating, overmolding the die assembly and the leads, and removing at least part of the temporary workpiece and/or at least part of the overmold to expose the attached pads for connecting them to a printed circuit board or another substrate, for example by means of solder balls.
  • the method may further include one or more of the additional method steps shown in Fig. 2.
  • coreless semiconductor die packages can be produced.
  • these die packages have leads attached between the die and pads on a temporary substrate. After the overmold, the temporary substrate is removed to allow exposure of the lead attached pads.
  • the leads include a metal core surrounded by a dielectric. Preferably, they further include a metallized outer layer attached to ground pad connections.
  • Fig. 1 is an illustration of dielectric and metal coated leads in a coreless package
  • Fig. 2 illustrates one embodiment of a method for manufacture of a coreless package
  • Fig. 3 illustrates method steps for manufacture of dielectric coated leads with outer ground connected metallization useful in the embodiment illustrated with respect to Fig. 1 and 2, and
  • Fig. 4 illustrates a subtractive method for manufacture of dielectric coated leads with outer ground connected metallization.
  • a "coreless" package 10 without a permanent substrate for die attachment can be constructed.
  • Such a semiconductor die packaging system can be formed to have leads 12, 14 with a dielectric layer 16 deposited over an inner metal core 18, as well as an outer metal layer 20 deposited over the dielectric layer 16.
  • the outer metal layer 20 is attached to a ground pad 22.
  • the leads 12, 14 are attached to die 30 that can include multiple connection pads for signal, power, or other functionality required by the die 30.
  • the die 30 does not have to be attached to a permanent substrate.
  • Leads 12, 14 can connect to conductive pads 34, while the conductive pads can be attached by means of solder balls 32, gold bumps, or other suitable interconnects to a printed circuit board or other substrate.
  • the leads 12, 14 are surrounded by an epoxy or other mold packaging compound, and may have substantially different lengths.
  • all leads have substantially the same impedance due to lead construction, even though lengths may differ.
  • the leads can be constructed to have distinctly different impedances.
  • leads that have a metal core of a defined diameter along its length can be sequentially coated with a thin dielectric layer and a conductive metal layer. Such leads are suitable for transfer of power because the consequent low impedance reduces power sag.
  • leads that have a much thicker dielectric layer are more suitable for transmission of signal data.
  • leads having substantially different lengths but the same core diameter can have substantially the same impedance, within 10% of target impedance, despite having lengths that vary 50% or greater.
  • lead differences can be even greater, with two leads having the same cross sectional structure and impedance, but one lead being as much as ten (10) times the length of the other.
  • stacked die are contemplated, as are ribbon connections formed by total or partial fusion of dielectric coatings forming the leads.
  • Fig. 2 is one embodiment of a method for manufacture of a coreless package such as described with respect to Fig. 1.
  • Multiple dies can be temporarily attached (40) to a workpiece that can be later physically released and removed, or otherwise etched or chemically eliminated.
  • the workpiece includes temporarily attached pad to support both metal core and outer metal ground layer attachment of each lead.
  • Wirebonding (41) is used to connect the die to the temporarily attached pads surrounding the die, followed by a dielectric coating (42) of the metal core.
  • the dielectric layer is metallized (43), with connections to ground pads being formed, and the entire multiple die assembly and leads are overmolded (44).
  • the temporary workpiece is removed (45), and the overmold may be etched or otherwise removed (46) by grinding or polishing to better expose the lead attached pads. Individual die and their connected leads can be singulated, and readied for solder ball or other connection to a printed circuit board (PCB) or another substrate (47).
  • PCB printed circuit board
  • thin dielectric layers will provide low impedance, suitable for power lines, thick dielectric is good for signal, and outer metal layers are connected to same ground. Note that a combination of core diameters and dielectric thicknesses is possible and a series of such steps may be performed to achieve more than two impedances. In certain embodiments it may be desirable to have large cores on power lines to increase power handling capacity, reduce power line temperatures, and/or further compensate any inductance on power supply and ground lines that would exacerbate ground bounce or power sag. Dielectric layers of intermediate thickness are also useful, since many packages could benefit from having leads of three (3) or more different dielectric thicknesses. For example, a lead have an intermediate dielectric thickness could be used to connect a source and load of substantially different impedance to maximize power transfer.
  • a 10 ohm source can be coupled to a 40 ohm load with a 20 ohm lead.
  • cost of dielectric can be high, critical signal pathways can interconnected using thick dielectric, with less critical status, reset, or the like leads can be coated with a dielectric layer having a thickness greater than the power leads, but less than (intermediate) to the critical signal leads.
  • this can reduces dielectric deposition material cost and time.
  • the precise thickness of the dielectric coating may be chosen, in combination with the wirebond diameter, to achieve a particular desired impedance value for each lead.
  • the characteristic impedance of a coax line is given in Eq. (1), where L is the inductance per unit length, C is the capacitance per unit length, a is the diameter of the bond wire, b is the outside diameter of the dielectric and ⁇ ⁇ is relative permittivity of the coaxial dielectric.
  • manufacture of dielectric coated leads with outer ground connected metallization can proceed using the following steps. Connection pads are cleaned (50) on the die and the substrate and a wirebonder is used to connect the die to the connection pads (51).
  • a second diameter wire can be attached (52) (e.g. a larger diameter wire suitable for power connections), or areas of the die can be masked (53) or otherwise protected to allow for selective deposition.
  • One or more layers of dielectric of the same or different composition can be deposited (54), followed by selective laser or thermal ablation, or chemical removal of portions of the dielectric to allow access to ground connections covered in the dielectric deposition step (55). This step is optional, since in some embodiments, the need for a ground via can be eliminated.
  • Metallization follows, covering the dielectric with a metal layer that forms the outermost metallized layer of the leads, and also connecting the leads to ground. The entire process can be repeated multiple times (58), useful for those embodiments using selective deposition techniques, and particularly for those embodiments supporting multiple die or complex and varied impedance leads.
  • an overmold can be used to encapsulate leads (59).
  • Alternative embodiments and additional or variant method steps are also described in US20120066894 and US Patent 6,770,822, the disclosures of which are fully incorporated by reference.
  • providing conformal coatings of dielectric can be accomplished through a variety of methods using chemical (electrophoretic), mechanical (surface tension), catalytic (primer, electromagnetic [UV, IR], electron beam, other suitable techniques.
  • Electrophoretic polymers are particularly advantageous because they can rely on self-limiting reactions that can deposit precise thicknesses readily by adjusting process parameters and or simple additive, concentration, chemical, thermal, or timing changes to an electrophoretic coating solution.
  • dielectric precoated bondwires can be used to form leads. While commercially available coated wires typically are thinner in dielectric thickness than is necessary to create, for example, 50 ohm leads, the foregoing discussed dielectric deposition steps can be used to increase dielectric thickness to set the desired impedance. Use of these precoated wires can simplify other process steps necessary to create coaxes, and can allow for thinner layers of needed vapor deposited dielectrics and faster processing times to create ground vias. Precoated bondwires can be used to prevent shorting for narrowly spaced or crossing leads. In certain embodiments the precoated bondwire can have a dielectric made from a photosensitive material to allow for selective patterning techniques.
  • the dielectric parylene can be used.
  • Parylene is the trade name for a variety of chemical vapor deposited poly(p-xylylene)polymers used as moisture and dielectric barriers. Parylene can be formed in a growth limited condensation reaction using a modified parylene deposition system where the die, substrate, and leads are aligned to a photoplate which allows EM radiation (IR, UV or other ) to strike in a precise manner causing selective growth rate of dielectric.
  • EM radiation IR, UV or other
  • this can minimize or eliminate the need for processes to create contact vias, bulk removal of parylene, etc. Parylene and other dielectrics are known to suffer from degradation due to oxygen scission in the presence of oxygen, water vapor and heat.
  • Damage can be limited by metal layers that form excellent oxygen vapor barriers, with thin layers of 3-5 micron thickness capable of forming true hermetic interfaces.
  • metal has been selectively removed, or not deposited in certain areas due to electrical, thermal, or manufacturing requirements, a wide range of polymer based vapor oxygen barriers can be used, with polyvinyl alcohol (PVA) being one widely used polymer.
  • PVA polyvinyl alcohol
  • These polymers can be glob topped, screen printed, stenciled, gantry dispensed, sprayed onto parylene surface that will be exposed to the oxygen or H20 vapor environment.
  • use of vapor barrier polymers can be a part of a cost reduction strategy, since thicker layers of high cost parylene or other oxygen sensitive might otherwise be required.
  • Selective deposition can be by physical masking, directed polymer deposition, photoresist methods, or any other suitable method for ensuring differential deposition thickness on the metal core, dielectric layer, or other outermost layer at time of deposition. While selective deposition allows for additive methods to build leads, it also allows for subtractive techniques in which dielectric or metal is removed to form multiple impedance interconnects. For example, a package populated by one or more die can be wire-bonded as appropriate for interconnect of all package and device pads. As seen with respect to Fig.
  • the dielectric coating 200 can be deposited (step A) to a thickness X-A over a wirebond metal conductor 202, where A is the thickness of the dielectric needed for the secondary interconnect impedance.
  • the secondary impedance wirebond dielectrics can be removed (step B) for example by an etch step, followed by a second coating 204 deposition (step C) followed by metallization 206 of both interconnects (step D). This subtractive process will create wirebonds of two distinct impedances.
  • the present invention is directed to a die package comprising a die having a plurality of connection pads, a plurality of leads having a metal cores with a defined core diameter, and a dielectric layer surrounding the metal cores having a defined dielectric thickness, first connection pads held in a mold compound covering the die and the plurality of leads connected to the metal cores, and second connection pads held in a mold compound covering the die and the plurality of leads connected to the metal cores.
  • the metal core diameters of the plurality of leads may differ in diameter.
  • the impedance of a subset of the plurality the leads may be within 10%.
  • the invention relates to a method of manufacture the above die package, selected steps of the method being shown in Fig. 2 and elsewhere.

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

La présente invention concerne des boîtiers de puce (10) comprenant une puce (30) ayant une pluralité de pastilles de connexion, une pluralité de fils conducteurs (12, 14) ayant des noyaux métalliques (18) avec un diamètre de noyau défini, et une couche diélectrique (16) entourant les noyaux métalliques avec une épaisseur diélectrique définie, au moins une première pastille de connexion (34) étant maintenue dans un composé de moule (35) recouvrant la puce (30) et la pluralité de conducteurs (12, 14) connectés à au moins un noyau métallique (18), et au moins une seconde pastille de connexion (33) étant maintenue dans le composé de moule (35) recouvrant la puce (30) et la pluralité de conducteurs (12, 14) connectés à au moins un noyau métallique (18). En outre, la présente invention concerne un procédé de fabrication d'un boîtier de puce sans substrat.
EP14734744.7A 2013-07-03 2014-07-02 Boîtier de puce sans substrat ayant des fils à revêtements diélectrique et métallique et son procédé de fabrication Active EP3017461B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361842950P 2013-07-03 2013-07-03
PCT/EP2014/001822 WO2015000593A1 (fr) 2013-07-03 2014-07-02 Boîtier de puce sans substrat ayant des fils à revêtements diélectrique et métallique et son procédé de fabrication

Publications (2)

Publication Number Publication Date
EP3017461A1 true EP3017461A1 (fr) 2016-05-11
EP3017461B1 EP3017461B1 (fr) 2020-03-11

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Country Status (8)

Country Link
US (1) US9711479B2 (fr)
EP (1) EP3017461B1 (fr)
JP (1) JP6457505B2 (fr)
KR (1) KR102035777B1 (fr)
CN (1) CN105359263B (fr)
CA (1) CA2915406C (fr)
TW (1) TWM506375U (fr)
WO (1) WO2015000593A1 (fr)

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JP2016531416A (ja) 2016-10-06
EP3017461B1 (fr) 2020-03-11
US9711479B2 (en) 2017-07-18
US20160372440A1 (en) 2016-12-22
TWM506375U (zh) 2015-08-01
HK1221821A1 (zh) 2017-06-09
CN105359263A (zh) 2016-02-24
CN105359263B (zh) 2018-07-06
KR20160029035A (ko) 2016-03-14
KR102035777B1 (ko) 2019-10-24
JP6457505B2 (ja) 2019-01-23
WO2015000593A1 (fr) 2015-01-08
CA2915406A1 (fr) 2015-01-08
CA2915406C (fr) 2019-11-12

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