EP3049244A4 - Verbindungen mit vollständig ummantelten leitungen - Google Patents

Verbindungen mit vollständig ummantelten leitungen Download PDF

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Publication number
EP3049244A4
EP3049244A4 EP14847477.8A EP14847477A EP3049244A4 EP 3049244 A4 EP3049244 A4 EP 3049244A4 EP 14847477 A EP14847477 A EP 14847477A EP 3049244 A4 EP3049244 A4 EP 3049244A4
Authority
EP
European Patent Office
Prior art keywords
interconnects
fully clad
lines
clad lines
fully
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP14847477.8A
Other languages
English (en)
French (fr)
Other versions
EP3049244A1 (de
EP3049244B1 (de
Inventor
Manish Chandhok
Hui Jae Yoo
Christopher Jezewski
Ramanan V. Chebiam
Colin T. CARVER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP18202287.1A priority Critical patent/EP3509095A1/de
Publication of EP3049244A1 publication Critical patent/EP3049244A1/de
Publication of EP3049244A4 publication Critical patent/EP3049244A4/de
Application granted granted Critical
Publication of EP3049244B1 publication Critical patent/EP3049244B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H10W20/0372—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal comprising multiple barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/059—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by reflowing or applying pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
EP14847477.8A 2013-09-27 2014-09-25 Interconnects mit vollständig ummantelten leitungen Active EP3049244B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP18202287.1A EP3509095A1 (de) 2013-09-27 2014-09-25 Verbindungen mit vollständig ummantelten leitungen

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/039,893 US9165824B2 (en) 2013-09-27 2013-09-27 Interconnects with fully clad lines
PCT/US2014/057413 WO2015048259A1 (en) 2013-09-27 2014-09-25 Interconnects with fully clad lines

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP18202287.1A Division-Into EP3509095A1 (de) 2013-09-27 2014-09-25 Verbindungen mit vollständig ummantelten leitungen
EP18202287.1A Division EP3509095A1 (de) 2013-09-27 2014-09-25 Verbindungen mit vollständig ummantelten leitungen

Publications (3)

Publication Number Publication Date
EP3049244A1 EP3049244A1 (de) 2016-08-03
EP3049244A4 true EP3049244A4 (de) 2017-04-26
EP3049244B1 EP3049244B1 (de) 2019-10-23

Family

ID=52739312

Family Applications (2)

Application Number Title Priority Date Filing Date
EP14847477.8A Active EP3049244B1 (de) 2013-09-27 2014-09-25 Interconnects mit vollständig ummantelten leitungen
EP18202287.1A Ceased EP3509095A1 (de) 2013-09-27 2014-09-25 Verbindungen mit vollständig ummantelten leitungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP18202287.1A Ceased EP3509095A1 (de) 2013-09-27 2014-09-25 Verbindungen mit vollständig ummantelten leitungen

Country Status (7)

Country Link
US (2) US9165824B2 (de)
EP (2) EP3049244B1 (de)
KR (1) KR102520743B1 (de)
CN (2) CN105473326B (de)
MY (1) MY175833A (de)
TW (1) TWI544576B (de)
WO (1) WO2015048259A1 (de)

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US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
WO2013095396A1 (en) 2011-12-20 2013-06-27 Intel Corporation Conformal low temperature hermetic dielectric diffusion barriers
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR101861455B1 (ko) 2013-12-19 2018-05-25 인텔 코포레이션 향상된 프라이버시를 갖는 보안 차량 데이터 관리
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US10950747B2 (en) * 2015-07-01 2021-03-16 Sensor Electronic Technology, Inc. Heterostructure for an optoelectronic device
KR102334736B1 (ko) * 2015-12-03 2021-12-03 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9812353B2 (en) 2015-12-03 2017-11-07 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
KR102449199B1 (ko) * 2015-12-14 2022-09-30 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
CN110366778B (zh) * 2017-04-04 2024-04-09 英特尔公司 薄膜晶体管嵌入式动态随机存取存储器
US11180373B2 (en) 2017-11-29 2021-11-23 Samsung Electronics Co., Ltd. Nanocrystalline graphene and method of forming nanocrystalline graphene
US11450669B2 (en) 2018-07-24 2022-09-20 Intel Corporation Stacked thin-film transistor based embedded dynamic random-access memory
US11217531B2 (en) * 2018-07-24 2022-01-04 Samsung Electronics Co., Ltd. Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure
KR102532605B1 (ko) 2018-07-24 2023-05-15 삼성전자주식회사 나노결정질 그래핀 캡층을 포함하는 인터커넥트 구조체 및 이 인터커넥트 구조체를 포함하는 전자 소자
KR102785398B1 (ko) 2018-07-25 2025-03-21 삼성전자주식회사 탄소물 직접 성장방법
WO2020118100A1 (en) * 2018-12-05 2020-06-11 Lam Research Corporation Void free low stress fill
SG11202108725XA (en) 2019-02-13 2021-09-29 Lam Res Corp Tungsten feature fill with inhibition control
KR102912591B1 (ko) 2019-04-30 2026-01-13 삼성전자주식회사 그래핀 구조체 및 그래핀 구조체의 형성방법
WO2022006349A1 (en) * 2020-07-02 2022-01-06 Lam Research Corporation Removable cvd polymer film for surface protection and queue period extension
CN114203814A (zh) * 2020-09-02 2022-03-18 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN114156255B (zh) * 2020-09-07 2025-01-14 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20250277312A1 (en) * 2024-03-01 2025-09-04 Applied Materials, Inc. Sacrificial liner for copper interconnect
CN118380383A (zh) * 2024-06-27 2024-07-23 杭州积海半导体有限公司 互联层结构的形成方法

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US20040137714A1 (en) * 2002-12-31 2004-07-15 Michael Friedemann Method of forming a conductive barrier layer having improve adhesion and resistivity characteristics
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Title
See also references of WO2015048259A1 *

Also Published As

Publication number Publication date
TWI544576B (zh) 2016-08-01
MY175833A (en) 2020-07-13
KR20160063313A (ko) 2016-06-03
US20150091175A1 (en) 2015-04-02
US9385085B2 (en) 2016-07-05
WO2015048259A1 (en) 2015-04-02
US9165824B2 (en) 2015-10-20
CN108615703A (zh) 2018-10-02
CN105473326B (zh) 2018-04-27
EP3049244A1 (de) 2016-08-03
EP3049244B1 (de) 2019-10-23
US20160005692A1 (en) 2016-01-07
CN105473326A (zh) 2016-04-06
KR102520743B1 (ko) 2023-04-11
CN108615703B (zh) 2023-02-17
EP3509095A1 (de) 2019-07-10
TW201535593A (zh) 2015-09-16

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