EP3105679B1 - Codierung von fehlerszenarien eines multikern-prozessors - Google Patents

Codierung von fehlerszenarien eines multikern-prozessors Download PDF

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EP3105679B1
EP3105679B1 EP15702721.0A EP15702721A EP3105679B1 EP 3105679 B1 EP3105679 B1 EP 3105679B1 EP 15702721 A EP15702721 A EP 15702721A EP 3105679 B1 EP3105679 B1 EP 3105679B1
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processor
scenarios
scenario
fault
symmetries
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EP3105679A1 (de
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Mohamed BENAZOUZ
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/142—Reconfiguring to eliminate the error
    • G06F11/1428—Reconfiguring to eliminate the error with loss of hardware functionality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/203—Failover techniques using migration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2051—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant in regular structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare

Definitions

  • the invention relates to the field of parallel computing and in particular that of the allocation of computing and communication resources, that is to say the placement and routing of software applications on single processor or multiprocessor computing platforms.
  • a microprocessor “multi-core” ( “multicore” or “multicore” in English) is a processor having a plurality of physical cores working in parallel.
  • Today systems called “ manycore “ (or “many-core” ) refer to systems with tens or even hundreds of hearts.
  • These calculation units, which can be clustered or not, are interconnected, for example by a communication network (Network on Chip or NoC).
  • Zhang et al. [ Lei Zhang et al. "On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 9, September 2009 ] discloses a technique based on virtualization to solve the problem of deploying an application on different irregular architectures that result from manufacturing failures of the same and unique initial architecture. Virtualization proposes to unify all these degraded physical architectures under a single reference virtual topology.
  • this approach offers only a part of the total power actually present on the chip, degraded or not (so-called AMAD logic for As Many As Demand ) . Thus, only one and only power range can be defined. Degraded processors that do not provide enough resources for reconfiguration will be rejected.
  • Such an approach is only efficient if it is applied to manycore architectures Clustered (in other words, when redundancy is at the level of computational cores, the cost associated with reserve cores being minimized). For clustered manycore architectures (corresponding to the most common case), redundancy at the cluster level would be too expensive and difficult to pay.
  • the abstraction of the physical NoC as it is performed greatly reduces the routing possibilities actually offered and may even reduce the feasibility space.
  • a method and apparatus for compact encoding of a processor's (or "chip") failure (or failure) scenarios exploiting the interconnect symmetries of an architecture is disclosed.
  • a method of placement and / or routing (in English mapping / routing ) of applications on degraded many-core processors are classified in ranges. Each range includes processors whose calculation capacity is the same, fixed and known in advance, but whose fault locations are known only when the processor is turned on (ie "online”).
  • the placement / routing phases are usually performed "offline” (for example during the compilation phase) as they consume a lot of time and power. Calculation.
  • decompression The placement / routing solutions for the scenarios not included in this reduced set can subsequently be obtained by decompression, which decompression can be executed at the chip.
  • decompression A decompression that must be fast and consume little computing power and memory given the embedded context.
  • no limit is imposed on the maximum number of failures.
  • All processors can be operated, categorized and marketed. Compared to the AMAD type approaches, such as Zhang, the rejection rate at the factory outlet will therefore be lower according to the invention (so-called AMAA logic for As Many As Available ).
  • AMAA logic for As Many As Available ).
  • computing resources present on a chip can be fully used, by classifying degraded processors in several commercial ranges, for example according to the level or number of failures. For example, if an application does not need all the power offered by a range, it can be deployed on a lower range that will necessarily be cheaper and deliver sufficient performance. For example, if an application needs 9 clusters of computations, we will use the range with 9 functional clusters. It will not be necessary to use a range greater than 10, 11 or 12 clusters (unlike the technique of virtualization that will need more clusters to rebuild its virtual architecture to 9 clusters).
  • the symmetry makes it possible to identify cases of equivalent faults, with some operations of symmetry. Following these operations, the space of the architectures coming from the same range can be compressed. In one step, the equivalent cases are detected and grouped into so-called equivalence classes. In another step the placement / routing solutions are calculated (one solution per class). Usually after the processor starts and / or the fault case and its class are identified, the placement / routing solution of this class can be decoded / decompressed to reconfigure it.
  • the global symmetry offered by all the interconnection elements is exploited, and generically.
  • This implementation is particularly delicate and technically difficult.
  • Existing techniques for exploiting symmetry in remote technical fields can use this "inference engine” to detect equivalent cases.
  • These engines are usually of exponential complexity and the optimizations that are generally made to them are detrimental to their generic character.
  • the convergence of the inference engines is not guaranteed in the general case (ie non-guaranteed calculation time), nor their accuracy (ie equivalent cases can be listed several times because they have not been detected as such by the inference engine).
  • the exploitation of the symmetry that is proposed is characterized by its optimality (eg two equivalent cases are listed only once), its speed (eg associated with a very low algorithmic complexity) and its genericity (eg it is easily adaptable to different architectures).
  • the invention will find application for embedded solutions (with limited computing and memory resources).
  • the symmetry can be used to reduce the number of architectures to be treated in order to guarantee the deployment of an application on a range of processors that offer the same computing capacity but whose architectures are different.
  • the invention can also be used for "on-line" reconfiguration when a failure occurs during the execution and that a new mapping / routing solution is needed in order to reconfigure the chip and continue the process. execution of the application.
  • the invention can be used for reconfiguring "on-line" as a preventive measure, for example in order to preserve the lifetime of a chip.
  • "on-line” a preventive measure
  • some computing resources can be deactivated in this zone and are replaced by other resources from another zone where the temperature is lower, which can impose or trigger a reconfiguration ( Dynamic Thermal Management ).
  • the method can be used to evaluate the failure resistance of certain NoC structures.
  • manycore can be selected processors whose architecture allows a high compression rate of spaces scenarios failure.
  • the disclosed methods may find application for gate mapping (LUT) and routing of communications in Field-Programmable Gate Array FPGA solutions for simulation or implementation purposes.
  • LUT gate mapping
  • s symmetry
  • graph-based mapping / routing techniques can be accelerated by detecting equivalent solutions, reducing the search space ( Symmetry Breaking ).
  • a computer-implemented method for compressing all fault scenarios of a processor including computational units interconnected by a communication network having topology symmetries, each failure scenario corresponding to the number and type of failure. location of one or more faulty calculation and the method comprising the steps of receiving or determining one or more topology symmetries; determining equivalent scenarios using said topology symmetries; each of the fault equivalence classes being associated with a resource allocation solution determining a specific placement of the tasks of the applications on the computing units and a specific routing of the data exchanges on the communication network.
  • topology symmetry may also be referred to as “symmetry topology " or " symmetry of topology “ or “topology symmetry” or “topological symmetry " .
  • the notion of topology can, for example and in some cases, refer to the graph of the topology.
  • the expression "symmetry of topology” or “topological symmetries” is to be taken in its broadest acceptation. In particular, a topological symmetry is not reducible to only symmetries of geometry.
  • Topological symmetry can be logical and / or physical: ie "logical” or “physical” or “logical and physical”. The physical arrangement, that is, the spatial configuration of the network is called physical topology.
  • Logical topology represents how data flows through communication lines.
  • the symmetries according to the invention may correspond to "logical" or “functional” or “architectural” geometries, that is to say operating at a higher level of abstraction than the only physical arrangement of the components on the circuit.
  • processor which may not have geometric symmetries strictly speaking (physical symmetries are not excluded, however, if they find their counterparts in logical or functional symmetries).
  • a processor with circuits, "cores" or computing units unequally distributed in space can nevertheless be seen functionally as a set of computational units or clusters having symmetries exploitable by the invention.
  • the symmetries according to the invention are based on a topological (or architectural) approach.
  • the topology of the communication network is chosen from the list comprising: Bus, Point to Point, Daisy Chain, Crossbar, Ring, Star, Tree, Fat Tree, Hypertree, Clos, Y, Delta, Omega, Hypercube, Folded Cube, Fibonacci Cube, Cube-connected cycles, as well as their extensions; Grid, 2D Mesh, 3D Mesh 3D Multi-mesh and larger dimensions, as well as their extensions; 2D Torus, 3D Torus, and higher dimensions as well as their extensions; hybrid of previous topologies; Fully connected (ie complete or Full Mesh ).
  • a graphical modeling approach is possible.
  • the physical and / or logical topology of a computing platform eg multi-core processor, multiprocessor, calculation server, ...) can indeed be modeled by a graph G (V, E) (oriented or not, weighted or not, labeled or untagged, etc.) where the set of nodes V models the computing units of the platform, and the set of arcs and / or edges E models the interconnection links between these units.
  • Each node v of V can be characterized by its architecture, its computing power, its number of elementary calculation units, its memories and their size, the number of registers, etc. (non-exhaustive list).
  • Two nodes are said to be identical based on a predefined list of characteristics if and only if they are identical on each of these characteristics.
  • two links are said to be identical (based on a predefined list of characteristics) if and only if they are identical on each of these characteristics.
  • a graph isomorphism denotes a bijection of nodes that preserves the adjacency and non-adjacency of the nodes as well as the degrees of the edges. This bijection is said to preserve the structure of the graph.
  • graph automorphism which is the case here, the isomorphism of the graph is the graph representing the physical and / or logical topology towards it. even).
  • Automorphisms define permutations with the characteristics that are those of isomorphisms. In other words, it is a bijection of the set of vertices from the graph to itself that preserves all the edges.
  • Geometric symmetries can be optionally used to graphically represent an automorphism. However, this is usually dependent on the drawing representing the graph of the topology. In addition, some graph automorphisms can not be visualized graphically by a geometric symmetry operation. In this case, automorphisms of graphs in general are considered: in no case are there limitations to only geometric symmetries. Symmetries are topological in nature.
  • a symmetry operation can be defined or interpreted in the sense of an automorphism of the graph G modeling the physical and / or logical topology of the architecture (ie the computing platform), whether the graph is oriented or non-oriented, weighted or unweighted, labeled or untagged (See Glossary of Graph Theory).
  • the graph obtained after a symmetry operation differs from the initial graph only by the labels of the nodes and edges. Their structures are completely equivalent.
  • a simple relabellization allows to find the initial graph.
  • Symmetry operations transform or associate a failure scenario into another equivalent failure scenario (in form and functionality).
  • classes can be determined as equivalent following the application of a sequence of symmetry operations followed by relabeling (for example). All the scenarios are explored in order to obtain fault equivalence classes.
  • Equivalent scenarios form an equivalence class and each equivalence class is associated with a resource allocation solution.
  • the symmetries can be "received” (for example from an external software module or from a circuit designer person) or "determined” by analysis and calculation means.
  • the detection of the symmetries of a topology amounts to constituting the set of automorphisms of the graph G modeling the topology ("Graph automorphism problem").
  • Graph automorphism problem a certain number of techniques can make it possible to perform the analysis of the physical and / or logical topology, and this automatically. These techniques include the use (possibly combinatorial) of search trees permutations that meet the requirements of isomorphism of graphs.
  • composition of automorphisms is an automorphism.
  • composition of symmetry operations is a symmetry operation.
  • any symmetry operation we can associate an inverse operation which is then also a symmetry operation.
  • An operation of symmetry designates a transformation which includes (non-exhaustive list, the indicated elements being combinable between them): displacements (preserving the distances and the oriented angles), isometries (keeping the distances and the angles), the similarities (retaining distance ratios), affine transformations (conserving parallelisms), homographic transformations (conserving the lines), and inversions for example (keeping all the lines and circles in the plane case).
  • a transformation may also include one or more bidifferentiable transformations (or diffeomorphisms), conformal or anticonforming transformations (conserving angles), equivalent or equiartial transformations (conserving areas in the plane case), bicontinuous transformations, or homeomorphisms (preserving neighborhoods). points), displacements (reflections, central symmetries, translations, rotations), homotheties, affinities, etc.
  • each of the equivalence classes (grouping equivalent scenarios) is associated with a computing resource allocation solution.
  • one or more equivalence classes is associated with one or more computing resource allocation solutions .
  • schemas (a class, a solution), (a class, several solutions), (several classes, a solution) and (several classes, several solutions) are possible.
  • the determination of the equivalent scenarios is done by applying an inference engine.
  • the inference engine can be based on symmetry operations or even use tools to solve isomorphisms of graphs (to determine that two finite graphs are isomorphic ie bijection between vertices which preserves the edges).
  • Various symmetry detection software tools can be used.
  • the determination of equivalent scenarios includes the association of a set of identifiers to each failure scenario.
  • Each scenario is associated with a set of identifiers, each of these identifiers corresponding to a fault statement order of the scenario. It may be that two different statements result in the same identifier. In this case, it is only filled once.
  • the identifiers have several properties. Two equivalent scenarios have the same set of identifiers. If an identifier is common to the sets of identifiers of two different scenarios, then these scenarios are equivalent. So, to prove the equivalence of two scenarios, it is sufficient to find an identifier common to both.
  • one way of proceeding is to a) choose a scenario in the set of scenarios not yet tested, to test the equivalence by calculating one of its identifiers and checking its membership to sets of identifiers classes of equivalence already identified. If in step b) the comparison shows that the identifier of the tested scenario belongs to one of these sets, then the scenario is indicated as being tested, skip the next step c) and proceed directly to step d ). Otherwise, in step c) a new class is created, equivalence class whose tested scenario becomes the "representative". All of its identifiers are then calculated and these identifiers are saved for future tests.
  • step d if the set of failure scenarios not yet tested is not empty, it is proceeded to step a) (recursive process). Otherwise, the algorithm ends because all the scenarios have been traversed (and all the equivalence classes and their identifiers have been determined).
  • the determination of equivalent scenarios includes the association of a unique identifier to each failure scenario.
  • identifiers that have the characteristic of having a total order relationship.
  • the identifiers can then be ordered and it then becomes possible to calculate the minimum (or the maximum) of a set of identifiers according to this order relation.
  • This minimum (or maximum) is the same for equivalent scenarios.
  • the technique previously described is repeated, but this time using (calculating, comparing and saving) only the minimum (or maximum) of the identifiers of a scenario and its equivalence class.
  • This minimum (or maximum) will be advantageously calculated by the use of an alphabetic / alphanumeric labeling and character concatenation techniques, this development will be detailed below.
  • the unique identifier is obtained by concatenation of the character strings forming said identifiers.
  • Strings can be numeric (eg 5125255) or alphabetic (eg abhdgjkie) and / or alphanumeric (54sde454h).
  • Integers all bases included: binary, decimal, octal, hexadecimal, etc.
  • strings of characters present this aspect of existence of a relation of total order, but a relation of order can be defined exhaustively on n any set. For example, it is possible to establish a total order relation R on the set ⁇ 0,1, a, b, bx ⁇ according to which bx>0>a>1> b. It is enough for a relation to be total, in other words capable of ordering the set of possible words that it is possible to compose from an alphabet (in the mathematical sense and not only alphanumeric) given.
  • the proposed concatenation technique is efficient and fast.
  • the symmetries comprise one or more axial rotations around an axis comprising one or more calculation units, at angles -90 ° / + 90 / + 180 ° and one or more displacements or vertical or horizontal displacements.
  • An offset is still called "shift" in English.
  • the equivalent failure scenarios are determined by combinatorial exploration, said combinatorial exploration including the construction of one or more equivalence class trees.
  • the method further includes creating a file specifying resource allocation.
  • the method further comprises determining a compression ratio of the space of the failure scenarios, the compression ratio being associated with the type of architecture of the processor.
  • the method for decompressing all of the failure scenarios of a processor includes determining one or more failures associated with one or more computing units at the start of the processor; the characterization of the corresponding failure scenario; identifying the fault equivalence class and the computing resource allocation solution associated with said fault equivalence class.
  • the method further includes reconfiguring the started processor, the reconfiguration comprising applying to the processor the computing resource allocation solution.
  • a “reconfiguration” refers to an operation that consists of placing tasks on new computing resources other than those originally assigned to them. This also involves recalculating new routing paths that result from the replacement of these tasks.
  • the reconfiguration takes place at the time of, or after, the occurrence of one or more failures of one or more processor units of the processor in order to continue the execution of the application on the processor.
  • the reconfiguration takes place before the occurrence of a failure of one or more failures of one or more processor units of the processor in a preventive manner, one or more faults being simulated or anticipated.
  • one or more reconfigurations can be performed preventively, for example to preserve the life of a processor.
  • This technique can be combined with the "dynamic temperature management" (DHM) of the CPUs of the processor.
  • the method comprises classifying the processor in a range comprising processors whose number of faulty calculation units is identical.
  • a range includes all architectures whose topology meets certain predefined criteria. These criteria are generally global (overall computing capacity, overall bandwidth, etc.) to which more specific criteria can be added (eg architecture comprising x capacitance calculation units C, x 'capacitance calculation units C' and that y flow links D, y 'flow links D', etc).
  • Graph automorphisms define equivalence relations of graphs. In the present case, graph automorphisms (ie symmetry) make it possible to define classes of equivalence of topologies that partition all the topologies of a range. Each partition gathers graphs of topologies that are equivalent according to the predefined characteristics to an automorphism.
  • a failing calculation unit is associated with a failure rate or execution confidence, said failure being total or partial.
  • calculation units are manipulated in a binary state: these calculation units are functional or they are not. Failure management as described guarantees better execution certainty on healthy hearts.
  • a probabilistic or "strata" approach can also be pursued.
  • a computing unit may be associated with a "runtime confidence rate”.
  • a healthy unit will then have, for example, a 100% confidence rate, but a calculation unit whose memory is partially out of order (or presenting other problems) may be associated with a confidence level of 80% (for example ).
  • the method further includes identifying one or more symmetric links from the determination or receipt of one or more topology symmetries.
  • Symmetric links refer to the interconnection links, ie the links of communication between the calculation units. Once received or calculated the symmetries of the topology of the network, a set of symmetrical links can be determined. As a result, after labeling, these symmetrical links can be manipulated, for example to determine the equivalence classes.
  • a computer program product comprising code instructions for performing any of the steps of the method when said program is run on a computer.
  • a "multi-core” microprocessor ( multicore in English) is a processor having several physical cores that work in parallel.
  • a physical heart is a set of circuits capable of running programs autonomously. All the functionalities necessary for the execution of a program are present in these cores: ordinal counter, registers, units of computation, etc.
  • the term "multi-core” is generally used to describe a processor composed of at least two cores (or computing units) etched within the same chip. These calculation units can be clustered (or not). The calculation units are interconnected by a communication network (Network on Chip or NoC).
  • the exploitation - and thus the marketing of a degraded chip - can be obtained by various means and / or methods.
  • a first approach is to perform an allocation (placement and routing, routing and mapping in English) of an application (software) on the computing and communication resources of a degraded manycore processor. Typically, these operations are static and "off-line" (that is, when the chip is not powered). These techniques also assume a total and complete knowledge of the architecture of the processors on which the software application will be deployed. For example, an approach for selling these degraded processors may be to define ranges of computing power. A given range then brings together all the processors that guarantee the availability of a fixed overall minimum of computing resources. Thus, by following this marketing strategy and because of the lack of differentiation according to the location of healthy resources, processors corresponding to different architectures can be found within the same range.
  • a first solution consists in fully explore the space of the architectures of a range and reiterate the placement / routing algorithms for each architecture (failure scenario) and save the resulting solutions.
  • this technique is accurate (ie optimal) and provides the guarantee, at the compilation phase, of the possibility (or not) to deploy the application regardless of the failure scenario within a range.
  • this technique is generally expensive in execution time because the number of configurations to explore is very large.
  • a solution storage problem also arises because of the large size of the resulting binary. Indeed, each failure scenario requires its own binary; the size of the final binary could be very large if we had to store all the reconfigurations for the specified range.
  • some embodiments of the invention can advantageously deal with failures in terms of computing resources.
  • Some embodiments of the invention in fact consider processors with a fully functional NoC, that is to say without failing routers (or links). Communication links and routers are generally less prone to failure.
  • resource allocation consists of placement and routing operations to allocate computing resources and necessary to execute and communicate the different tasks of an application.
  • placement therefore designates the operation that assigns each of the tasks of an application to execution media (i.e. computing units e.g. core, processor, cluster, server, etc.), which implicitly assume memory means. Tasks assigned to one or more media will then be executed only by them. The scheduling (or “scheduling") of a medium will determine the order and times during which the tasks access these shared resources (which are allocated to them).
  • execution media i.e. computing units e.g. core, processor, cluster, server, etc.
  • routing refers to the operation that calculates a path consisting of communication links that connect the units of calculation (Bus, NoC, local network, internet, ...) to ensure the transfer of data between tasks that communicate with each other and run on different media.
  • the figure 1 schematically illustrates a processor manycore 100 to 9 clusters 110 (or “cores” / “hearts” or “calculation units”) type 2D torus 3x3.
  • the clusters are numbered from 1 to 9 and are interconnected by a NoC or interconnects 120 (represented by the lines in the figure).
  • Most of the many-core processors have symmetries. These symmetries make it possible to define operations that transform the initial architecture into another that is totally identical to it (the architecture is called “equivalent”) in terms of form and functionalities.
  • the architecture of its NoC a homogeneous manycore processor Tore 2D has several symmetries. Some symmetries are shared with the underlying Mesh architecture (Damier).
  • FIGS. 2A, 2B and 2C illustrate the labeling before and after a symmetry operation.
  • the Figure 2A shows the labels before symmetry (rotation).
  • the Figure 2B shows the labels after the rotation.
  • the figure 3B shows the labels after relabeling.
  • Each symmetry operation is associated with a relabellization function that makes it possible to find the initial order of the labels of the architecture. For example, at the 180 ° rotation in the space around the axis that passes through clusters 1, 5 and 9 corresponds to the relabellization function of clusters [1,4,7,2,5,8,3,6 , 9] -> [1,2,3,4,5,6,7,8,9]. It is the same for the interconnection links whose labels are not mentioned or represented for the sake of simplification.
  • a failure scenario is defined by the number and location of the compute units (ie clusters in this example) that are defective.
  • a scenario (i, j, k) is a scenario for which only the three clusters i, j and k are Out of order.
  • the order of statement of these failures is not important, ie the scenarios (i, j, k), (i, k, j), (j, i, k), (j, k, i), (k, i, j) or (k, j, i) are the same.
  • FIGS. 3A, 3B and 3C show how symmetry can be used to compress the space of failure scenarios.
  • the figure 3A illustrates a simplified example of a two-fault scenario (1,2).
  • the figure 3B shows the scenario (1,2) after rotation.
  • the figure 3C shows the relabellization after the rotation.
  • Defining equivalence classes has the advantage of not having to solve the placement / routing problem and saving the solution only for the one and only representative of each class.
  • a first solution could be to implement a symmetry-based inference engine, implemented for example by means of languages such as LISP or Prolog.
  • the inference engine searches for a sequence of rules to apply in order to establish equivalence with the representative of an already listed class or to create a new class. equivalence if no equivalence is established (ie absence of sequence). In the latter case, the scenario becomes the representative of the new class.
  • symmetry rules and the relabellization operations associated with them it is then necessary to define a) the symmetry rules and the relabellization operations associated with them and b) the priority (or order or occurrence) of application of each of these rules and at each stage of the research process (priorities, orders or occurrences may vary from one stage to another of the research process).
  • the technique may also not be accurate and the maximum compression ratio may not be reached (a class could correspond to more than one partition, if the equivalence between all its elements does not match). is not established).
  • the adaptation of such a process for each architecture will also take a long time and will be very complex.
  • the figure 4 serves as a support for illuminating the complexity of the technical problem of identifying equivalent cases.
  • the figure 4 shows two scenarios with three failures.
  • the Figure 4A shows a scenario (1,2,9) and a scenario (2,4,7).
  • a rotation in the plane of + 90 ° in a clockwise direction around the central cluster 5 changes the labels of the adjacent clusters 4 and 7 to 1 and 2.
  • Cluster 2 becomes 6
  • the application of a horizontal shift downward on the scenario (1,2,6) leads to the scenario (4,5,9).
  • an axial rotation of 180 ° around the axis that crosses the units 4, 5 and 6, and after labeling the scenario becomes (4,5,3).
  • each scenario is associated with an identifier, so that two scenarios associated with the same identifier are necessarily or necessarily equivalent and are therefore interchangeable.
  • the identifier may be that of the equivalence class itself. By construction, such an identifier integrates the symmetry transformations and does not depend on the labels associated with the faulty clusters. To this end, a distance is introduced: an inter-cluster distance that adds the notion of symmetry to the usual inter-cluster distances. Then, based on this new distance, means and / or steps identify a particular scenario.
  • the compression process comprises four steps or phases.
  • a distance called "symmetrical inter-cluster distance" In a first step is defined a distance called "symmetrical inter-cluster distance".
  • an equivalent remote cluster identification means of another cluster is described below.
  • an inter-cluster distance a first solution consists in taking into account the number of links that separate these clusters (eg hop count). This measurement makes it possible to evaluate the length of the shortest inter-cluster routing path and thus provides a measure of the data rate consumed relative to the overall routing capacity of the network. The smaller it is, the more network congestion can be avoided (and the energy saved).
  • the improved inter-cluster distance proposed here takes into account - in addition to the hop count and the nature of the interconnection links - the symmetry schemes. As a corollary, two pairs of clusters that are at different hop count will have different "symmetrical distances". These distances are introduced in figure 5 .
  • the Figures 5A and 5B illustrate the notion of symmetrical distance.
  • Ui a calculation unit denoted Ui.
  • Units Uj and Uk are said to have the same "symmetrical distance" of Ui if there is a sequence of symmetry operations to save the location of Ui while bringing the location of Uk to that of Uj.
  • the Figure 5A gives an example for the 2D 3x3 torus and the cluster 5.
  • rotations of -90 ° / + 90 ° / + 180 ° in the plane around the cluster 5 it appears that the clusters 2, 4, 6 and 8 are at the same symmetrical distance of the cluster 5 labeled as distance A.
  • the clusters 1, 3, 7 and 9 are at the same symmetrical distance from the cluster 5 and are labeled B.
  • the result of all the clusters can be grouped in a matrix symmetrical distance M represented at the Figure 5B , of dimension 3x3.
  • Mij is the distance between Ui and Uj.
  • the number of symmetrical links is two (A and B).
  • the figure 6 introduces the scenario identifiers and illustrates a use of them to establish equivalence of the (2,4,7) and (1,2,9) failure scenarios previously provided to the figure 4 .
  • a failure scenario is identified and characterized. To do this, the positions of the failures relative to each other are used, by means of the notion of symmetrical distance defined above.
  • the identifier of a scenario is a word taken from an alphabet composed exclusively of symmetrical distance labels.
  • the identifier denoted Identity (Ui, Uj) is given by the distance Mij.
  • the identifier Identity (Ui, Uj, Uk) is obtained by Mji (MkiMkj). For scenarios with a higher number of failures, it is done by recursion using a concatenation operator of strings.
  • Identity Ui, Uj, ..., Um
  • Identity Ui, Uj, Uk, ..., Um, Uq
  • the identification depends on the order considered in the statement of failures of the scenario. In other words, without additional process, several identifiers can be calculated for the same scenario. In order to avoid that equivalent scenarios are not detected as such because of the order of the fault statement, an additional and optional step ensures that they have a unique identifier and therefore ensures the accuracy of the technique and a maximum compression ratio.
  • the fault statement order is selected which gives the smallest identification against the string comparison.
  • the interest of the concatenation for the comparison of identifiers justifies the use of alphabetical labels. Alternatively, alphabetic, numeric and / or alphanumeric characters may be used.
  • the number of failures is greater than half the number of units initially planned on a chip, rather than defining a scenario by its units in breakdowns, it may be advisable to define it by its functional units to optimize the size of the identifiers scenarios.
  • the technique of calculating the Identity ID will remain valid by reporting the positions of the healthy units in relation to themselves. For example, from 5 failures, it is more efficient to enumerate the remaining 4 healthy clusters of the 2D 3x3 Tore.
  • the scenario space is explored.
  • a tree of equivalence classes This operation consists in traversing the space of possible failure scenarios in order to partition it into equivalence classes according to the definition given during the previous step. For each scenario traveled, it is checked whether there is not in the tree a listed scenario that is equivalent to it. If this is not the case, a new node is added to the tree (the scenario and its identifier being the representatives of the new equivalence class).
  • the different levels of the tree indicate the different ranges. For example, at the top of the tree, classes will be found in the range of a single failure. In the example of the 3x3 2D torus processor, it consists of only one node.
  • the construction of the tree stops when we have reached the maximum level of failures considered (ie the most degraded range).
  • This tree is built only once by manycore architecture because it is independent of the applications that will be deployed there.
  • the provider of the manycore processor will be able to build and integrate this tree in development tools (for example). Users or developers will also be able to use such trees, for example when designing applications to calculate and save placement and / or routing solutions for each of the nodes of the level that represents the range on which they want to deploy. the application.
  • different variants of the explorer can be implemented, for example with the choice of a search width or depth, according to different choices of the representative of an equivalence class (for example choose the one whose labels of clusters are the smallest).
  • the space explored to build the equivalence class tree may itself be reduced. Indeed, it is not always necessary to browse the entire space. For the example of the 2D 3x3 torus, any failure can be reduced - by symmetry operations - to be placed (or relabellized) as a failure of the cluster 1. In order to reduce the space to be explored, it is therefore possible to consider that the number 1 computing unit is still down. Thus, the size of the space to be explored is divided by 9. Optionally, for greater certainty, a test can also be implemented to verify that the equivalence class tree obtained covers all possible scenario cases.
  • a relabellization is performed. After starting the chip and detecting the failure scenario, the identifier and therefore the equivalence class to which the chip belongs can be determined according to the technique presented in the second step. Thus, from the tree of the scenarios constructed during phase 3, it is possible to extract the equivalent scenario and the placement / routing solution that are associated with the situation of failure of the chip. It will then be necessary to adapt this equivalent solution to the scenario of the chip. This adaptation constitutes the stage or phase of relabellisation.
  • This relabeling step is executed on the chip since it is necessary to know the scenario of the failure.
  • this phase can be optimized due to or for limited resources in calculation and memory (low complexity in time and execution space).
  • the NoC architecture may be the same for all the manycore processors (when hypothetically the NoC is fully functional or Fault-Free).
  • the proposed re-labeling step is not very computationally intensive. Indeed, contrary to the reasons which invite to relativize the use of an inference engine, the fact of knowing beforehand that two scenarios are equivalent (by calculating their identifier and thus the order of statement of the breakdowns) makes it possible the determination of a sequence of symmetry operations that is both generic and efficient to bring back one scenario to another that is equivalent to it. For example, for a 2D 4x4 torus, the algorithm requires less than 3 instructions to detect the sequence and thus relabel a scenario to its equivalent.
  • the Figures 7A, 7B and 7C illustrate different aspects of the process.
  • the Figure 7A illustrates examples of operations usually performed offline (processor off). Generally, these operations do not depend on software applications "mapped" on the said processor.
  • the symmetries are identified in step 711.
  • the symmetric links are labeled in step 712.
  • the symmetric inter-cluster distance matrix is constructed at step 713.
  • Scenarios are explored (equivalence classes and identifiers) at step 714.
  • the identifiers and equivalence class representatives are stored in step 715.
  • the Figure 7B illustrates examples of operations usually performed offline (processor off), for deploying an application software for example.
  • step 721 the class representative scenarios and their identifiers are received or identified or calculated.
  • step 722 for each class representative scenario, the appropriate placement / routing solution is calculated.
  • step 723 the solutions are stored (each solution can specify the scenario for which it was calculated).
  • the Figure 7C illustrates examples of operations generally performed at the time of or after the start of the chip (for example after the deployment of an application according to the Figure 7B ).
  • the steps listed below may be performed (some steps may be optional or modifiable or modified, or the required data received from plug-ins, etc.).
  • Step 731 Start the chip.
  • Step 732 identification of the failure scenario.
  • Step 733 calculation of the identifier of the fault.
  • Step 734 recovery of the scenario representing the class bearing the same identifier as that of the failure scenario observed on the processor.
  • Step 735 calculating one or more sequences of symmetry operations to reduce the failure scenario of the processor to that of the representative of its equivalence class.
  • Step 736 Calculation of relabellization from the sequence of symmetry operations that has been obtained.
  • Step 737 Relabellization of the placement / routing solution associated with the class representative.
  • Step 738 Deploy the application according to the relabellated placement / routing solution.
  • the invention will find advantageous application for "Cloud Computing", distributed computing environments, “Grid Computing”, etc.
  • the invention can indeed allow fault management on a set of processors, because of the topological abstraction which is performed to exploit the symmetries.
  • an 800-core processor can be topologically equivalent to two hundred 4-core processors.
  • the exploitation of symmetries in both cases carry the same advantages, namely static reconfigurations (packaging in ranges, pre-marketing) or dynamic reconfigurations during the runtime.
  • the present invention can be implemented from hardware and / or software elements. It may be available as a computer program product on a computer readable medium.
  • the support can be electronic, magnetic, optical, electromagnetic or be an infrared type of diffusion medium.

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Claims (18)

  1. Computerimplementiertes Verfahren für die Komprimierung der Gesamtheit von Fehlerszenarien eines Prozessors, der Recheneinheiten umfasst, die durch ein Kommunikationsnetz miteinander verbunden sind, das Topologiesymmetrien aufweist, wobei jedes Fehlerszenario der Anzahl und Stelle einer oder mehrerer fehlerhafter Recheneinheiten entspricht und das Verfahren die folgenden Schritte umfasst:
    Empfangen oder Bestimmen einer oder mehrerer Topologiesymmetrien;
    Bestimmen von äquivalenten Szenarien mittels der Topologiesymmetrien, wobei die äquivalenten Szenarien in Äquivalenzklassen zusammengefasst sind;
    wobei jede der Fehleräquivalenzklassen mit einer Ressourcenzuweisungslösung verbunden ist, die eine spezifische Platzierung der Aufgaben der Anwendungen auf den Recheneinheiten und ein spezifisches Routing des Datenaustauschs auf dem Kommunikationsnetz bestimmt.
  2. Verfahren nach Anspruch 1, wobei das Bestimmen von äquivalenten Szenarien durch Anwendung eines Inferenzmotors umgesetzt wird.
  3. Verfahren nach Anspruch 1, wobei das Bestimmen von äquivalenten Szenarien das Verbinden einer Gesamtheit von Kennungen mit jedem Fehlerszenario umfasst.
  4. Verfahren nach Anspruch 3, wobei das Bestimmen von äquivalenten Szenarien das Verbinden einer einmaligen Kennung mit jedem Fehlerszenario umfasst.
  5. Verfahren nach Anspruch 4, wobei die einmalige Kennung durch Konkatenation der Zeichenketten, die die Kennungen bilden, erhalten wird.
  6. Verfahren nach Anspruch 1, wobei die Symmetrien eine oder mehrere Axialdrehungen um eine Achse, die eine oder mehrere Recheneinheiten umfasst, nach Winkeln von -90°/+90/+180°, und eine oder mehrere vertikale oder horizontale Verschiebungen oder Versätze umfassen.
  7. Verfahren nach Anspruch 1, wobei die äquivalenten Fehlerszenarien durch kombinatorische Exploration bestimmt werden, wobei die kombinatorische Exploration die Erstellung eines oder mehrerer Äquivalenzklassenbäume umfasst.
  8. Verfahren nach einem der vorhergehenden Ansprüche, ferner umfassend die Erstellung einer Datei, die die Ressourcenzuweisung spezifiziert.
  9. Verfahren nach Anspruch 1 bis 8, ferner umfassend das Bestimmen eines Komprimierungsverhältnisses des Fehlerszenarienraums, wobei das Komprimierungsverhältnis mit der Art der Architektur des Prozessors verbunden ist.
  10. Verfahren nach Anspruch 1 zur Dekomprimierung der Gesamtheit von Fehlerszenarien eines Prozessors, nach dem Hochfahren des Prozessors, ferner umfassend:
    - Bestimmen eines oder mehrerer Fehler, die mit einer oder mehreren Recheneinheiten verbunden sind, beim Hochfahren des Prozessors;
    - Charakterisieren des entsprechenden Fehlerszenarios;
    - Identifizieren der Fehleräquivalenzklasse und der Rechenressourcenzuweisungslösung, die mit der Fehleräquivalenzklasse verbunden ist.
  11. Verfahren nach Anspruch 10, ferner umfassend die Neukonfiguration des hochgefahrenen Prozessors, wobei die Neukonfiguration die Anwendung der Rechenressourcenzuweisungslösung auf dem Prozessor umfasst.
  12. Verfahren nach Anspruch 11, wobei die Neukonfiguration im Moment des oder nach dem Auftreten eines oder mehrerer Fehler einer oder mehrerer Recheneinheiten des Prozessors ausgeführt wird, um die Ausführung der Anwendung auf dem Prozessor fortzusetzen.
  13. Verfahren nach Anspruch 11, wobei die Neukonfiguration auf präventive Weise vor dem Auftreten eines oder mehrerer Fehler einer oder mehrerer Recheneinheiten des Prozessors ausgeführt wird, wobei ein oder mehrere Fehler simuliert oder erwartet werden.
  14. Verfahren nach einem der vorhergehenden Ansprüche, ferner umfassend die Klassifizierung des Prozessors in einem Bereich, der Prozessoren umfasst, deren Anzahl an defekten Recheneinheiten identisch ist.
  15. Verfahren nach einem der vorhergehenden Ansprüche, wobei eine defekte Recheneinheit mit einer Defekt- oder Ausführungsvertrauensquote verbunden ist, wobei der Defekt total oder partiell ist.
  16. Verfahren nach einem der vorhergehenden Ansprüche, ferner umfassend die Identifizierung einer oder mehrerer symmetrischer Beziehungen basierend auf der Bestimmung oder des Empfangs einer oder mehrerer Topologiesymmetrien.
  17. Computerprogrammprodukt, wobei das Computerprogramm Code-Anweisungen umfasst, die es ermöglichen, die Schritte des Verfahrens nach einem der Ansprüche 1 bis 16 durchzuführen, wobei das Programm auf einem Computer ausgeführt wird.
  18. System für die Komprimierung oder die Dekomprimierung des Fehlerszenarienraums eines Prozessors, wobei das System Mittel zur Umsetzung der Verfahrensschritte nach einem der Ansprüche 1 bis 16 umfasst.
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