EP3240028A2 - Structure de plages de contact et son procédé de fabrication - Google Patents

Structure de plages de contact et son procédé de fabrication Download PDF

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Publication number
EP3240028A2
EP3240028A2 EP17162861.3A EP17162861A EP3240028A2 EP 3240028 A2 EP3240028 A2 EP 3240028A2 EP 17162861 A EP17162861 A EP 17162861A EP 3240028 A2 EP3240028 A2 EP 3240028A2
Authority
EP
European Patent Office
Prior art keywords
regions
region
contact pad
conductive layer
pad structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP17162861.3A
Other languages
German (de)
English (en)
Other versions
EP3240028A3 (fr
EP3240028B1 (fr
Inventor
Yu-Wei Jiang
Teng-Hao Yeh
Chia-Jung Chiou
Chih-Yao Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
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Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/099,316 external-priority patent/US9508645B1/en
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of EP3240028A2 publication Critical patent/EP3240028A2/fr
Publication of EP3240028A3 publication Critical patent/EP3240028A3/fr
Application granted granted Critical
Publication of EP3240028B1 publication Critical patent/EP3240028B1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/337—Multiple die-attach connectors having different shapes

Definitions

  • This invention relates to a structure applicable to integrated circuits and its fabrication, and particularly relates to a contact pad structure for electrical connections of multiple levels of conductors, and a method for fabricating the contact pad structure.
  • a three-dimensional (3D) device array such as a 3D memory
  • the conductive lines of the respective levels of devices need electrical connection, so the conductive layers of the respective levels have to be exposed in a contact area for later electrical connection.
  • a staircase contact pad structure is formed.
  • N-1 photomasks are used to perform N-1 lithography and etching processes to remove different numbers of levels of conductive layers from N-1 regions in the contact area.
  • N-1 photomasks are used to perform N-1 lithography and etching processes to remove different numbers of levels of conductive layers from N-1 regions in the contact area.
  • this invention provides a contact pad structure that can be formed with much less than N-1 times of lithography and etching processes for N levels of devices.
  • This invention also provides a method for fabricating the contact pad structure of this invention.
  • the contact pad structure of this invention comprises alternately stacked N insulating layers (N ⁇ 6) and N conductive layers, and has N regions exposing the respective conductive layers.
  • the regions are arranged in a P ⁇ Q array (P ⁇ 3, Q ⁇ 2).
  • substantially no insulating layer or conductive layer higher than the Ln i,j -th conductive layer is present in the region (i, j).
  • the Ln i,j -th conductive layer is exposed in a contact hole formed in upper layers among the insulating layers and the conductive layers.
  • the contact pad structure of this invention may be disposed in a 3D memory.
  • the contact pad structure of this invention can be formed with much less than N-1 times of lithography and etching processes for N levels of devices, the formation process can be significantly simplified, and the process control is easier.
  • the topology height difference is minor, especially in the ADT boundary, and the area of each staircase can be divided equally well.
  • the protrusion structure can divide the wide trench to avoid dishing issue by a subsequent CMP process.
  • FIG. 1A illustrates a perspective view of a contact pad structure of an example according to the first embodiment of this invention.
  • FIG. 1B illustrates a top view of the contact pad structure illustrated in FIG. 1A , wherein the number Ln i,j of the conductive layer exposed in each region and the number Tn i,j of the conductive layer(s) requiring to be removed in each region are shown.
  • substantially no insulating layer or conductive layer higher than the Ln i,j -th conductive layer is present in the region (i, j).
  • 12 insulating layers 102 and 12 conductive layers 104 are alternately stacked, and the 12 regions exposing the respective conductive layers 104 are arranged in a 4 ⁇ 3 array.
  • the column direction and the row direction are designated as i-direction and j-direction, respectively, in the figures, but the i-direction and the j-direction are not necessarily the x-direction and the y-direction, or the y-direction and the x-direction, respectively, of the wafer.
  • Ln i,j decreases with increase of the j-value, satisfying the relationships of Ln i,1 >Ln i,2 >Ln i,3 .
  • Ln i,j decreases from the two ends toward the center, satisfying the relationship of Ln 1,j , Ln 4,j >Ln 2,j , Ln 3,j .
  • Tn 2,3 11.
  • the Tn i,j distribution can be achieved by using much less than N-1 (11) photomasks to perform the same number (M) of lithography and etching processes, with a certain combination of photomask patterns and numbers of etched conductive layers. An example of such combination is illustrated in FIG. 2 .
  • the photomask pattern 21 includes removal regions 212 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 214 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 212 and non-removal regions 214 are distributed as shown in the figure.
  • the photomask pattern 22 includes removal regions 222 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 224 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 222 and non-removal regions 224 are distributed as shown in the figure.
  • the photomask pattern 23 includes removal regions 232 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 234 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 232 and the non-removal regions 234 are distributed as shown in the figure.
  • the photomask pattern 24 includes removal regions 242 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 244 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 242 and non-removal regions 244 are distributed as shown in the figure.
  • the conductive layers 104 may include a metal material, N-doped polysilicon, P-doped polysilicon, or a combination thereof
  • the insulating layers 102 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
  • the contact pad structure 100 in which the respective conductive layers 104 are exposed is formed, it is possible to form an upper insulating layer (not shown) over it and then form in the same a plurality of contact plugs (not shown) having different depths to electrically connect the respective conductive layers 104 in the contact pad structure 100.
  • FIG. 3A illustrates a perspective view of a contact pad structure of another example according to the first embodiment of this invention.
  • FIG. 3B illustrates a top view of the contact pad structure illustrated in FIG. 3A , wherein the number Ln i,j of the conductive layer exposed in each region and the number Tn i,j of the conductive layer(s) requiring to be removed in each region are shown..
  • the i-direction and the j-direction are defined as above.
  • Ln i,j decreases with increase of the j-value, satisfying the relationship of Ln i,1 >Ln i,2 .
  • Ln i,j decreases from the two ends toward the center, satisfying the relationship of Ln 1,j , Ln 6,j >Ln 2,j , Ln 5,j >Ln 3,j , Ln 4,j .
  • the Tn i,j distribution can be achieved by using much less than N-1 (11) photomasks to perform the same number (M) of lithography and etching processes, with a certain combination of photomask patterns and numbers of etched conductive layers. An example of such combination is illustrated in FIG. 4 .
  • the photomask pattern 31 includes removal regions 312 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 314 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 312 and non-removal regions 314 are distributed as shown in the figure.
  • the photomask pattern 32 includes removal regions 322 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 324 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 322 and non-removal regions 324 are distributed as shown in the figure.
  • the photomask pattern 33 includes removal regions 332 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 334 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 332 and the non-removal regions 334 are distributed as shown in the figure.
  • the photomask pattern 34 includes removal regions 342 corresponding to the pad regions where one or more conductive layers are to be removed, and non-removal regions 344 corresponding to the pad regions where no conductive layer is to be removed, wherein the removal regions 342 and non-removal regions 344 are distributed as shown in the figure.
  • FIG. 5A illustrates a top view of a contact pad structure of an example according to a second embodiment of this invention, wherein the number Tn i,j of the conductive layer(s) requiring to be removed in each region is shown.
  • FIG. 5B illustrates a B-B' cross-sectional view of the contact pad structure illustrated in FIG. 5A .
  • the Tn i,j distribution of the contact pad structure 500 is the same as that shown in FIG. 1B , and the combination of photomask pattern distributions and numbers of etched conductive layers for its formation may be the same as that shown in FIG. 2 .
  • each insulating layer 102 and each conductive layer 104 above the Ln i,j -th conductive layer is merely partially removed in the M lithography and etching processes, so that a contact hole 106 is formed in the layers 102 and 104 above the Ln i,j -th conductive layer and the Ln i,j -th conductive layer is exposed in the contact hole 106.
  • a spacer 108 may be formed on the sidewall of each contact hole 106, so that the contact plug of the Ln i,j -th conductive layer that will be formed later in the contact hole 106 in the region (i, j) can be insulated from the conductive layer(s) 104 above the region (i, j) Ln i,j -th conductive layer.
  • the spacer 108 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
  • the above contact pad structure 100, 300 or 500 of the above embodiments may be disposed in a 3D memory.
  • the contact pad structure of this invention can be disposed adjacent to a word-line pad in a 3D memory.
  • FIG. 6 illustrates a perspective view of an example of such 3D-memory structure of an embodiment of this invention.
  • FIG. 6 An example of a concave shape of the asymmetric structure of the contact regions in the same column is illustrated in FIG. 6 .
  • an asymmetric structure having the protrusion shape may be disposed on a surface lower than adjacent surfaces, as shown in FIG. 7A , or alternatively be disposed on a surface coplanar with adjacent surfaces as shown in FIG. 7B .
  • the adjacent surfaces may be top surfaces of the word-line pad of a 3D memory.
  • FIG. 8 illustrates an example of the concave shape of the contact regions that meets the requirement
  • FIG. 9 illustrates an example of the protrusion shape of the contact regions that meets the requirement, wherein each number is the number Tn i,j of the conductive layers being removed in the corresponding contact region.
  • Contact pad structures 800 and 900 are shown in FIG. 8 and FIG. 9 , respectively.
  • the steps include row definition steps and column definition steps, but these definition steps can be performed in any order.
  • the number Tn i,j of the conductive layer(s) being removed in each region is also shown in the figure.
  • Q 3 in this example, so the m values and the column definition steps are the same as the above example.
  • the number Tn i,j of the conductive layer(s) being removed in each region is also shown in the figure.
  • the process as shown in FIG. 15 is different from the process as shown in FIG. 11 in that the target regions are masked, instead of being exposed and etched, in each etching step.
  • the number Tn i,j of the conductive layer(s) being removed in each region is also shown in the figure.
  • FIG. 16 illustrates the number Tn i,j of the conductive layer(s) requiring to be removed in each region in various embodiments where a concave shape is formed and P is 5 or 6.
  • the number n of the etched rows in each of the 1-layer etching step and the 2-layer etching step(s), and the number d [integer part of (P-1)/2] of the 2-layer etching step(s) are indicated by the equalities shown in the parentheses.
  • the concave shape has a central lowest point at an h-th region that is at the middle of a column or is one region shifted from the middle of a column.
  • the 3-rd, 2-nd or 4-th region h is 3, 2 or 4
  • the 4-th or 5-th region h is 4 or 5
  • ⁇ 2 when Tn i,1 (i h+1 to P) is P-1-
  • ⁇ 2 when Tn i,1 (i h+1 to P) is P-
  • Tn i,j (i ⁇ 1, j>1) can be calculated as Tn i,1 +(j-1) ⁇ P.
  • FIG. 17 illustrates the number Tn i,j of the conductive layer(s) requiring to be removed in each region in various embodiments where a protrusion shape is formed and P is 5 or 6.
  • the number n of the masked rows in each of the 1-layer etching step and the 2-layer etching step(s), and the number d [integer part of (P-1)/2] of the 2-layer etching step(s) are also indicated by the equalities shown in the parentheses.
  • the protrusion shape has a central highest point at an h-th region that is at the middle of a column when P is an odd number, or is at the middle of a column or is one region shifted from the middle of a column when P is an even number.
  • the 3-rd or 4-th region h is 3 or 4
  • the 5-th region h is 5
  • Tn 1,1 is P-1
  • Tn h,1 is 0,
  • ⁇ 2 when Tn i,1 (i h+1 to P) is
  • ⁇ 2+1 when Tn i,1 (i h+1 to P) is
  • ⁇ 2, and Tn i,1 (i h+1 to P) is
  • Tn i,j (i ⁇ 1, j>1) can be calculated as Tn i,1 +(j-1) ⁇ P.
  • the contact pad structure of this invention can be formed with much less than N-1 times (e.g., 4 times) of lithography and etching processes for N (e.g., 12) levels of devices, the formation process can be significantly simplified, and the process control is easier.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
EP17162861.3A 2016-04-14 2017-03-24 Structure de plages de contact et son procédé de fabrication Active EP3240028B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/099,316 US9508645B1 (en) 2016-04-14 2016-04-14 Contact pad structure
US15/362,718 US9685408B1 (en) 2016-04-14 2016-11-28 Contact pad structure and method for fabricating the same

Publications (3)

Publication Number Publication Date
EP3240028A2 true EP3240028A2 (fr) 2017-11-01
EP3240028A3 EP3240028A3 (fr) 2017-11-15
EP3240028B1 EP3240028B1 (fr) 2023-08-02

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EP17162861.3A Active EP3240028B1 (fr) 2016-04-14 2017-03-24 Structure de plages de contact et son procédé de fabrication

Country Status (6)

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US (1) US9685408B1 (fr)
EP (1) EP3240028B1 (fr)
JP (1) JP6457581B2 (fr)
KR (1) KR101923566B1 (fr)
CN (1) CN107301990B (fr)
TW (1) TWI612637B (fr)

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KR102428273B1 (ko) 2017-08-01 2022-08-02 삼성전자주식회사 3차원 반도체 소자
CN111149206B (zh) * 2017-11-15 2023-08-18 桑迪士克科技有限责任公司 在平台区中具有加厚字线的三维存储器器件及其制造方法
US10804284B2 (en) * 2018-04-11 2020-10-13 Sandisk Technologies Llc Three-dimensional memory device containing bidirectional taper staircases and methods of making the same
JP2020047797A (ja) 2018-09-19 2020-03-26 キオクシア株式会社 記憶装置及びその製造方法
WO2021189189A1 (fr) * 2020-03-23 2021-09-30 Yangtze Memory Technologies Co., Ltd. Structure d'escaliers dans un dispositif de mémoire tridimensionnel et procédé de formation associé
JP7604346B2 (ja) * 2021-09-21 2024-12-23 キオクシア株式会社 半導体記憶装置
CN117979685A (zh) * 2022-10-19 2024-05-03 长鑫存储技术有限公司 半导体结构及其形成方法

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US8530350B2 (en) * 2011-06-02 2013-09-10 Micron Technology, Inc. Apparatuses including stair-step structures and methods of forming the same
JP2013055136A (ja) * 2011-09-01 2013-03-21 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JP2014027104A (ja) * 2012-07-26 2014-02-06 Toshiba Corp 半導体装置及びその製造方法
US9165823B2 (en) * 2013-01-08 2015-10-20 Macronix International Co., Ltd. 3D stacking semiconductor device and manufacturing method thereof
KR102046504B1 (ko) * 2013-01-17 2019-11-19 삼성전자주식회사 수직형 반도체 소자의 패드 구조물 및 배선 구조물
JP2014183225A (ja) * 2013-03-19 2014-09-29 Toshiba Corp 不揮発性半導体記憶装置
JP6181441B2 (ja) * 2013-06-24 2017-08-16 新光電気工業株式会社 パッド構造、実装構造、及び、製造方法
JP2015176923A (ja) * 2014-03-13 2015-10-05 株式会社東芝 不揮発性半導体記憶装置
US9142538B1 (en) * 2014-09-18 2015-09-22 Macronix International Co., Ltd. Three-dimensional semiconductor device
US9196567B1 (en) 2015-01-14 2015-11-24 Macronix International Co., Ltd. Pad structure

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Also Published As

Publication number Publication date
JP2017191937A (ja) 2017-10-19
KR20170117892A (ko) 2017-10-24
EP3240028A3 (fr) 2017-11-15
US9685408B1 (en) 2017-06-20
KR101923566B1 (ko) 2019-02-20
CN107301990B (zh) 2019-10-18
EP3240028B1 (fr) 2023-08-02
TWI612637B (zh) 2018-01-21
JP6457581B2 (ja) 2019-01-23
CN107301990A (zh) 2017-10-27
TW201737454A (zh) 2017-10-16

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