EP3302003A1 - Optoelektronischer schaltkreis, der elektrolumineszenzdioden umfasst - Google Patents

Optoelektronischer schaltkreis, der elektrolumineszenzdioden umfasst Download PDF

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Publication number
EP3302003A1
EP3302003A1 EP17193974.7A EP17193974A EP3302003A1 EP 3302003 A1 EP3302003 A1 EP 3302003A1 EP 17193974 A EP17193974 A EP 17193974A EP 3302003 A1 EP3302003 A1 EP 3302003A1
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EP
European Patent Office
Prior art keywords
voltage
circuit
current
conduction
source
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EP17193974.7A
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English (en)
French (fr)
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EP3302003B1 (de
Inventor
David GRAS
Thomas PEYSSON
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EASII IC
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EASII IC
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H05B45/48—Details of LED load circuits with an active control inside an LED matrix having LEDs organised in strings and incorporating parallel shunting devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix

Definitions

  • the present description relates to an optoelectronic circuit, in particular an optoelectronic circuit comprising light-emitting diodes.
  • an optoelectronic circuit comprising light-emitting diodes with an alternating voltage, in particular a sinusoidal voltage, for example the mains voltage.
  • the figure 1 represents an example of an optoelectronic circuit 10 comprising input terminals IN 1 and IN 2 between which an AC voltage V IN is applied.
  • the optoelectronic circuit 10 further comprises a rectifying circuit 12 comprising a diode bridge 14, receiving the voltage V IN and supplying a rectified voltage V ALIM which supplies light-emitting diodes 16, for example, connected in series with a resistor 15. Calls I ALIM the current passing through the light-emitting diodes 16.
  • the figure 2 is a timing diagram of the supply voltage V ALIM and the supply current I ALIM for an example in which the alternating voltage V IN corresponds to a sinusoidal voltage.
  • the voltage V ALIM is greater than the sum of the threshold voltages of the light-emitting diodes 16, the light-emitting diodes 16 turn on.
  • the supply current I ALIM then follows the supply voltage V ALIM . There is therefore an alternation of OFF phases of absence of light emission and ON phases of light emission.
  • a disadvantage is that as long as the voltage V ALIM is less than the sum of the threshold voltages of the light-emitting diodes 16, no light is emitted by the optoelectronic circuit 10. An observer can perceive this absence of light emission when the duration of each OFF phase of absence of light emission between two ON phases of light emission is too important. One possibility to increase the duration of each ON phase is to reduce the number of light-emitting diodes 16. A disadvantage is that the share of the electrical power lost in the resistance is important.
  • the publication US 2014/0252968 discloses an optoelectronic circuit in which the number of light-emitting diodes receiving the supply voltage V ALIM increases progressively during a phase of growth of the supply voltage and decreases progressively during a phase of decrease of the supply voltage . This is achieved by a switching device adapted to short-circuit a larger or smaller number of groups of light-emitting diodes according to the evolution of the voltage V ALIM . This makes it possible to reduce the duration of each phase of absence of light emission.
  • a disadvantage of the optoelectronic circuit described in the publication US 2014/0252968 is that it requires the use of a difference amplifier for each group of light-emitting diodes. The manufacturing cost of the optoelectronic circuit can therefore be high. Another disadvantage is that the power consumption of the optoelectronic circuit can be significant. Another disadvantage is the complexity of the optoelectronic circuit which can lead to reliability problems.
  • the publication US-2013/0200802 discloses an optoelectronic circuit having a plurality of diodes connected in series and a switching device adapted to short-circuit a larger or smaller number of light-emitting diodes according to the evolution of the supply voltage.
  • the switching circuit comprises a differential amplifier.
  • An object of an embodiment is to overcome all or part of the disadvantages of the optoelectronic circuits described above.
  • Another object of an embodiment is to reduce the duration of the phases of absence of light emission of the optoelectronic circuit.
  • Another object of an embodiment is that the current supplying the light-emitting diodes varies substantially continuously.
  • Another object of an embodiment is that the number of components of the switching device of the optoelectronic circuit is reduced.
  • the difference amplifier receives as input a differential voltage corresponding to the difference between the first voltage and the second voltage.
  • the difference amplifier is adapted to supply a first current and a second current
  • the control circuit comprising a first multi-output current mirror adapted to copy, for each conduction circuit, the first current or a third current multiplied by a first copy factor, and a second multi-output current mirror adapted to copy, for each conduction circuit, the second current or the third current multiplied by a second copy factor, the ratio between the first copy factor and the second copy factor being different for each conduction circuit.
  • the sets of light-emitting diodes are arranged in increasing ranks from a first set at a first end of the series to a last set at a second end of the series, and for each conduction circuit the control is adapted to enslave the first voltage to the second voltage decreased by a third voltage which is decreasing with the rank of the assembly to which the conduction circuit is connected.
  • the difference amplifier comprises a differential pair comprising a first transistor receiving the first voltage and a second transistor receiving the second voltage.
  • the first transistor is a MOS transistor whose gate receives the first voltage and the second transistor is a MOS transistor whose gate receives the second voltage.
  • the optoelectronic circuit comprises, for each conduction circuit, a capacitor connected to the conduction circuit or integrated in the conduction circuit, the first current mirror comprising a capacitor charging circuit and the second current mirror comprising a capacitor discharge circuit.
  • each conduction circuit comprises an MOS transistor.
  • the first current mirror comprises, for each conduction circuit, a first copy block connected to the gate of the MOS transistor of the conduction circuit and adapted to supply the first current multiplied by the first copy factor and the second current mirror comprises, for each conduction circuit, a second copy block connected to the gate of the MOS transistor of the conduction circuit and adapted to supply the second current multiplied by the second copy factor.
  • the optoelectronic circuit comprises a current source connected to said node.
  • the current source comprises at least one resistor.
  • the current source is adapted to supply a current which increases with the rank of the assembly to which the conduction circuit is connected.
  • the third voltage varies as a function of the temperature.
  • a “signal binary” is a signal that alternates between a first constant state, for example a low state, denoted "0", and a second constant state, for example a high state, denoted "1".
  • the high and low states of different binary signals of the same electronic circuit can be different.
  • the binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.
  • the term “connected” is used to denote a direct electrical connection, without intermediate electronic component, for example by means of a conductive track, and the term “coupled” or the term “connected”, to designate either a direct electrical connection (meaning “connected”) or a connection via one or more intermediate components (resistor, capacitor, etc.).
  • the term “power factor” of an electronic circuit is the ratio between the active power consumed by the electronic circuit and the product of the rms values of the current and of the voltage supplying the electronic circuit.
  • the figure 3 represents a circuit diagram of an embodiment of an optoelectronic circuit 20 comprising a light emitting diode switching device and illustrating the general operating principle of the optoelectronic circuit.
  • the elements of the optoelectronic circuit 20 common with the optoelectronic circuit 10 are designated by the same references.
  • the optoelectronic circuit 20 comprises the rectifier circuit 12 receiving the supply voltage V IN between the terminals IN 1 and IN 2 and supplying the voltage V ALIM rectified between nodes A 1 and A 2 .
  • the circuit 20 can directly receive a rectified voltage, the rectifier circuit may then not be present.
  • the potential at the node A 2 may correspond to a low reference potential Voff, for example 0 V, with respect to which are referenced the voltages of the optoelectronic circuit 20. Unless otherwise indicated, the potentials are referenced in the following description with respect to the Voff low reference potential.
  • a high reference potential, called Von can be provided from the supply voltage V ALIM .
  • the optoelectronic circuit 20 comprises N series sets of elementary light-emitting diodes, called global electroluminescent diodes D i in the remainder of the description, where i is an integer ranging from 1 to N and where N is an integer between 2 and 200
  • Each global light-emitting diode D 1 to D N comprises at least one elementary light-emitting diode.
  • each global electroluminescent diode is composed of placing in series and / or in parallel at least two elementary light-emitting diodes.
  • the N global light-emitting diodes D i are connected in series, the cathode of the diode overall electroluminescent D i being connected to the anode of the global light emitting diode D i + 1 , for i ranging from 1 to N-1.
  • the anode of the global light-emitting diode D 1 is connected, preferably connected, to the node A 1 .
  • the global light emitting diodes D i , i ranging from 1 to N may comprise the same number of elementary light emitting diodes or different numbers of elementary light emitting diodes.
  • the optoelectronic circuit 20 comprises a current source 22, one terminal of which is connected to the node A 2 and whose other terminal is connected to a node A 3 .
  • the current source 22 may have any structure and may in particular correspond to an impedance, for example a resistor.
  • the cathode of the global light-emitting diode D N is connected, preferably connected, to the node A 3 . Called V SOURCE the voltage across the current source 22 and I SOURCE the current flowing through the current source 22.
  • the optoelectronic circuit 20 may comprise a circuit, not shown, which provides a reference voltage for supplying the current source, possibly obtained from the voltage V ALIM .
  • the current source 22 can be continuously controlled by a circuit external to the optoelectronic circuit 20.
  • the conduction circuit SW i is a circuit whose equivalent electrical resistance varies between a maximum value and a minimum value as a function of the signal S i . According to a mode of realization, when the equivalent electrical resistance of the conduction circuit SW i is at the maximum value, the conduction circuit SW i is substantially equivalent to an open switch. Alternatively, current can flow through the circuit SW i even when the equivalent electrical resistance of the conduction circuit SW i is the highest. For i varying from 1 to N, I i is the current flowing in the conduction circuit SW i . In the remainder of the description, G i is a node connected to the conduction circuit and receiving the signal S i .
  • the conduction circuit SW N which protects the current source 22 from overvoltages, may not be controlled by the control module 28 and may still be on or may not be present and the cathode of the light emitting diode D N global can be connected to the node A 3 .
  • the optoelectronic circuit 20 may further comprise a circuit, not shown, which provides a reference voltage for the supply of the switching device 24, possibly obtained from the voltage V ALIM .
  • the control signal Si of each conduction circuit SW i is a signal which can vary continuously between a first value and a second value, the equivalent electrical resistance of the conduction circuit SW i decreasing when the signal Si varies from the first value to the second value.
  • the first and second values of the signals S i , i varying from 1 to N, may not be the same for all the conduction circuits SW i .
  • the conduction circuit SW i is substantially not conducting when the signal S i is at the first value.
  • each conduction circuit SW i is, for example, based on at least one transistor, in particular a metal oxide oxide or MOS transistor field effect transistor, enriched or depleted.
  • the signal S i is then the potential at the gate of the transistor SW i .
  • each conduction circuit SW i comprises an N-channel enrichment MOS transistor whose drain is connected to the cathode of the global light emitting diode D i , whose source is connected to the node A 3 and whose gate is connected to the node G i .
  • the conduction circuit SW i comprises two MOS transistors, for example N-channel, between the cathode of the global light-emitting diode D i and the node A 3 , the transistor connected to the global light-emitting diode D i being a high-voltage transistor mounted in cascode and the transistor connected to the node A 3 being a low-voltage transistor controlled by the signal S i .
  • each conduction circuit may correspond to a transistor other than a MOS transistor, to a relay, to an electromechanical microsystem and in general to any element whose electrical conductivity can be controlled in terms of voltage or current. monotone.
  • the circuit 26 for supplying the reference voltage V REF is internal to the optoelectronic circuit 20.
  • the reference voltage V REF is supplied to the optoelectronic circuit 20 by a circuit external to the optoelectronic circuit 20 or is obtained from a modulation signal supplied to the optoelectronic circuit 20 by a circuit external to the optoelectronic circuit 20.
  • the optoelectronic circuit 20 may comprise a terminal dedicated to receiving the reference voltage V REF or the modulation signal from which the reference voltage V REF is obtained.
  • the reference voltage V REF or the modulation signal can be provided by a dimmer, in particular a dimmer that can be actuated by a user or a brightness sensor.
  • the figure 4 represents a circuit diagram of one embodiment of the control circuit 28.
  • the control circuit 28 comprises a transconductance operational amplifier comprising a differential pair 30 and current mirrors 32, 34 and 36.
  • the signal S i corresponds to the potential at the node G i .
  • the differential pair 30 comprises a transistor T 1 , for example a P-channel MOS transistor, the source of which is connected to the terminal of a current source I diff and whose gate is controlled by the voltage V SOURCE .
  • the other terminal of the current source I diff can be connected to the source of the high reference potential Von.
  • the differential pair 30 further comprises a transistor T 2 , for example a P-channel MOS transistor, the source of which is connected to the current source I diff and whose gate is controlled by the voltage V REF . Called I 1 the current to the drain of transistor T 1 and I 2 the current to the drain of transistor T 2.
  • the transistors T 1 and T 2 have the same characteristics.
  • the form factor (W / L) of the channel of the transistor T 1 is equal to the channel form factor of the transistor T 2 .
  • the channel aspect ratio of a transistor is the ratio of the width to the length of the channel.
  • the channel form factor of the transistor T3 is taken as the reference form factor.
  • the current mirror 32 comprises a transistor T 3 , for example an N-channel MOS transistor, the drain of which is connected, preferably connected, to the drain of the transistor T 1 , the source of which is connected, preferably connected, to the source Voff low reference potential, for example the node A 2 , and whose gate is connected to the drain.
  • the current mirror 32 comprises a transistor T 4 , for example an N-channel MOS transistor, the source of which is connected, preferably connected, to the source of the low reference potential Voff and whose gate is connected to the gate of the transistor T 3 .
  • the transistors T 3 and T 4 have the same characteristics.
  • the channel form factor of the transistor T 3 is equal to the channel form factor of the transistor T 4 .
  • the current flowing in the transistor T 4 is therefore equal to I 1 flowing in T 3 .
  • the current mirror 34 comprises a transistor T 5 , for example a P-channel MOS transistor, the drain of which is connected, preferably connected, to the drain of the transistor T 4 , the source of which is connected, preferably connected, to the source potential of Von top reference, and whose gate is connected to the drain.
  • the current mirror 34 furthermore comprises, for each conduction circuit SW i , i varying from 1 to N, a transistor T sup-i , for example a P-channel MOS transistor, the source of which is connected, preferably connected, to the source of the high reference potential Von, whose gate is connected to the gate of the transistor T 5 and whose drain is connected, preferably connected to the node G i .
  • the transistors T sup-i may not have the same characteristics with respect to each other and with respect to the transistor T 5 .
  • the ratio between the channel form factor of the sup-i transistor T and the channel form factor of the transistor T 5 is called R sup-i .
  • R sup-i may be different from R sup-j , with i different from j.
  • IG i is the current at the drain of the transistor T sup-i .
  • the current mirror 36 comprises a transistor T 6 , for example an N-channel MOS transistor, the drain of which is connected, preferably connected, to the drain of the transistor T 2 , the source of which is connected, preferably connected, to the source of the low reference potential Voff, and whose gate is connected to the drain.
  • the current mirror 36 furthermore comprises, for each conduction circuit SW i , i varying from 1 to N, a MOS transistor T i , which is, for example, an N channel, the source of which is connected, preferably connected, to the source the low reference potential Voff, whose gate is connected to the gate of the transistor T 6 and whose drain is connected, preferably connected to the node G i .
  • the transistors T i may not have the same characteristics with respect to each other and with respect to the transistor T 6 .
  • the ratio between the channel form factor of the transistor T i-1 and the channel form factor of the transistor T 6 is called R i-i .
  • R inf-i may be different from R inf-j , with i different from j.
  • IG ' i the current at the drain of the transistor T inf-i .
  • RatioPN i is the ratio between the channel form factor of transistor T sup-i and the channel form factor of transistor T i-i , i.e. ratio between R sup-i and R inf-i .
  • the ratio RatioPN i is strictly greater than the ratio RatioPNj for i strictly greater than j.
  • the ratio RatioPN i may vary between 1 / N and N.
  • the difference between the ratios RatioPN i and RatioPN i + 1 is strictly greater than 1 / (N-1) -1 / N.
  • the figure 5 represents a circuit diagram of a control circuit 40 comprising all the elements of the control circuit 28 shown in FIG. figure 4 with the difference that only one conduction circuit SW i is present and that the light-emitting diodes are not present.
  • the current IG i is equal to the current I 1 and the current IG ' i is equal to the current I 2 .
  • the voltage V SOURCE is equal to the voltage V REF
  • the currents I 1 , I 2 , IG i and IG ' i are equal to I diff / 2
  • the potential at the node G i is equal to the sum the voltage V SOURCE and the gate-source voltage of the transistor SW i .
  • the transistor T 1 conducts less than the transistor T 2 , so that the current I 1 becomes lower than the current I 2 .
  • the current IG i decreases with respect to the current IG ' i . Due to the capacity of the node G i , this causes a decrease in the voltage at the gate of the transistor SW i . The transistor SW i therefore becomes less active and the voltage V SOURCE decreases until it is again equal to V REF .
  • the transistor T 1 conducts more than the transistor T 2 , so that the current I 1 becomes greater than the current I 2 .
  • the current IG i increases with respect to the current IG ' i . Due to the capacity of the node G i , this causes an increase in the voltage at the gate of the transistor SW i .
  • the transistor SW i therefore becomes more active and the voltage V SOURCE rises until that it is again equal to V REF .
  • the control circuit 40 thus slaves the voltage V SOURCE to the voltage V REF .
  • the OFFSET offset voltage i is proportional to the difference between currents I 1 and I 2 and inversely proportional to the conductance of the differential pair.
  • the offset voltage OFFSET i therefore depends on the ratio RatioPN i .
  • a variation of the voltage V SOURCE with respect to its equilibrium value causes a variation of the voltage at the gate of the transistor SW i which tends to reduce the voltage V SOURCE to its value at the balance.
  • the control circuit 40 thus slaves the voltage V SOURCE to the voltage V REF less the offset voltage OFFSET i .
  • the control circuit 28 supplies the signals S 1 to S N at values adapted to modify the conduction of the conduction circuits SW 1 to SW N so that the voltage V SOURCE is slaved to the reference voltage V REF at an offset voltage OFFSET near that may vary depending on the operating point of the optoelectronic circuit.
  • An advantage of the switching device 24 is that it has a reduced power consumption.
  • the control circuit 28 slaves the voltage V SOURCE to the reference voltage V REF at an offset voltage OFFSET by controlling the gates of transistors SW i .
  • the differential pair 30 receives as input the difference between the voltage V SOURCE and the voltage of reference V REF .
  • the reference voltage is identical for all output stages, but the offset voltage is different for each output stage.
  • the control module 28 then slaves the voltage V SOURCE to the voltage V REF reduced by OFFSET i by the conduction circuit SW i , the OFFSET i offset voltage between the V SOURCE voltage and the V REF voltage being lower than the OFFSET i-1 offset voltage.
  • each conduction circuit SW i comprises a MOS transistor whose gate receives the signal Si, this means that the gate voltage of the transistor SW i-1 decreases and the transistor SW i-1 becomes less and less until it reaches its non-passing state.
  • the potential at the node G i is equal to the sum of the voltage V SOURCE and the gate-source voltage of the transistor SW i .
  • the control module 28 then slaves the voltage V SOURCE at the voltage V REF reduced by OFFSET i-1 by the conduction circuit SW i-1 , the offset voltage OFFSET i-1 being higher than the offset voltage OFFSET i .
  • each conduction circuit SW i comprises a MOS transistor whose gate receives the signal Si, this means that the gate voltage of the transistor SW i-1 increases and that the transistor SW i-1 becomes more and more. passing and the transistor SW i reaches its completely conducting state.
  • control circuit 28 does not include state finite state machines and that the control order of the conduction circuits SW i is imposed by the differences between the ratios RatioPN i .
  • the embodiment of the switch control method SW i described above does not depend on the number of elementary light-emitting diodes that make up each global light-emitting diode D i and therefore does not depend on the threshold voltage of each global light-emitting diode. .
  • the offset voltage OFFSET i decreasing with the index i
  • the voltage at which is stabilized at the voltage V SOURCE increases with index i.
  • the current I SOURCE flowing in the global light emitting diodes D 1 to D i increases with the index i.
  • the power factor of the optoelectronic circuit is thus increased.
  • the circuit 26 for supplying the reference voltage V REF is adapted to modify the value of the reference voltage V REF among several values as a function of a control signal supplied by the control module 28.
  • the circuit 26 is controlled to increase the value of the reference voltage VREF with the index i.
  • the voltage at which voltage stabilizes V SOURCE then increases with the index i, regardless of the increase described above due to the variation of offset voltage OFFSET i .
  • the current I SOURCE flowing in the global light emitting diodes D 1 to D i increases with the index i.
  • the power factor of the optoelectronic circuit is thus increased.
  • the current source 22 is adapted to supply a current I SOURCE whose intensity can take several values according to a control signal supplied by the control module 28. According to one embodiment, considering that the diodes D 1 to D i are on and the global light emitting diodes D i + 1 to D N are off, the current source 22 is controlled to increase the intensity of the current I SOURCE with the index i. Advantageously, the power factor of the optoelectronic circuit is thus increased.
  • Offset offset voltage i for i given may be constant or vary depending on the temperature, either increasing as the temperature increases or decreasing as the temperature increases.
  • the current source 22 is a resistor and the offset voltage OFFSET i decreases as the temperature increases, an increase in the temperature results in a decrease in the current I SOURCE and therefore a decrease in the thermal power supplied by the optoelectronic circuit 20. This provides protection of the optoelectronic circuit 20 against thermal runaway.
  • the figure 6 represents timing diagrams, obtained by simulation, of voltage V ALIM , current I SOURCE , voltages V SOURCE and V REF , voltages S 1 , S 2 , S 3 and S 4 and currents I 1 , I 2 , I 3 and I 4 in the case where the voltage V ALIM is obtained from a sinusoidal V IN voltage and in the case where N is equal to 4.
  • the ratio RatioPN 1 was equal to 1/4
  • the ratio RatioPN 2 was 1/3
  • the ratio RatioPN 3 was 1 ⁇ 2
  • the ratio RatioPN 4 was 1 and the intensity of the current supplied by the power source I diff was equal to 20 ⁇ A.
  • each conduction circuit SW i corresponds to a non-conducting state
  • these embodiments can also be implemented with a conduction circuit SW i for which the least electrically conductive state nevertheless corresponds to a state in which current flows through the circuit SW i , for example a current whose intensity is less than or equal to the theoretical limit which is the maximum intensity inducing a power in the conduction circuit SW i can be dissipated without causing malfunction thereof.
  • each transistor T sup-i is adapted to copy the current I 1 multiplied by the copy factor Rsup i and each transistor T i-i is adapted to copy the current I 2 multiplied by the copy factor Rinf i .
  • each transistor T i-1 may be adapted to copy a reference current, for example a constant current, and each transistor T i is adapted to copy the current I 1 multiplied by the copy factor Rsup i .
  • each transistor T i can be adapted to copy a reference current, for example a constant current
  • each transistor T i-1 is adapted to copy the current I 2 multiplied by the copy factor Rinf i . It can thus also be obtained different RatioPN i ratios for each conduction circuit SW i and OFFSET i offset voltages different for the conduction circuit SW i .

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  • Amplifiers (AREA)
EP17193974.7A 2016-09-30 2017-09-29 Optoelektronischer schaltkreis, der elektrolumineszenzdioden umfasst Active EP3302003B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1659452A FR3057135B1 (fr) 2016-09-30 2016-09-30 Circuit optoelectronique comprenant des diodes electroluminescentes

Publications (2)

Publication Number Publication Date
EP3302003A1 true EP3302003A1 (de) 2018-04-04
EP3302003B1 EP3302003B1 (de) 2019-04-24

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US (1) US9974133B2 (de)
EP (1) EP3302003B1 (de)
FR (1) FR3057135B1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3144481A1 (fr) * 2022-12-26 2024-06-28 Easii Ic Circuit optoelectronique comprenant des diodes electroluminescentes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120299484A1 (en) * 2010-02-05 2012-11-29 Bong Sub Shin Constant current driving apparatus for leds
US20130200802A1 (en) * 2012-02-03 2013-08-08 Nichia Corporation Light-emitting diode driving apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120299484A1 (en) * 2010-02-05 2012-11-29 Bong Sub Shin Constant current driving apparatus for leds
US20130200802A1 (en) * 2012-02-03 2013-08-08 Nichia Corporation Light-emitting diode driving apparatus

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US9974133B2 (en) 2018-05-15
FR3057135B1 (fr) 2020-11-13
US20180098394A1 (en) 2018-04-05
FR3057135A1 (fr) 2018-04-06
EP3302003B1 (de) 2019-04-24

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