EP3588562A1 - Substrat de réseau, et dispositif d'affichage - Google Patents

Substrat de réseau, et dispositif d'affichage Download PDF

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Publication number
EP3588562A1
EP3588562A1 EP17851942.7A EP17851942A EP3588562A1 EP 3588562 A1 EP3588562 A1 EP 3588562A1 EP 17851942 A EP17851942 A EP 17851942A EP 3588562 A1 EP3588562 A1 EP 3588562A1
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EP
European Patent Office
Prior art keywords
electrode
drain electrode
array substrate
active layer
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP17851942.7A
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German (de)
English (en)
Other versions
EP3588562A4 (fr
Inventor
Ke CAO
Chengshao YANG
Wenlong Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Publication of EP3588562A1 publication Critical patent/EP3588562A1/fr
Publication of EP3588562A4 publication Critical patent/EP3588562A4/fr
Withdrawn legal-status Critical Current

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13685—Top gates
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    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
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    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a display device.
  • TFT-LCD thin film transistor liquid crystal display device
  • TFT-LCD generally includes a liquid crystal cell cell-assembled by an array substrate having a thin film transistor (TFT) array and an opposed substrate, and a liquid crystal molecule layer filled in the liquid crystal cell.
  • At least one embodiment of the present disclosure provides an array substrate and a display device, which can solve the problems that an ordinary array substrate has a relatively slow responding speed and a relatively lower charging efficiency, and can avoid increasing the aperture opening ratio at the same time.
  • At least one embodiment of the present disclosure provides an array substrate which includes a base substrate; a first active layer, located on the base substrate; a first insulating layer, located on the first active layer and the base substrate; a gate electrode, located at a side of the first insulating layer away from the first active layer; a second insulating layer, located on the gate electrode and the first insulating layer; a second active layer, located at a side of the second insulating layer away from the gate electrode; a first drain electrode and a first source electrode, being in partial contact with the first active layer, respectively; a second drain electrode and a second source electrode, being in partial contact with the second active layer, respectively; and a pixel electrode, the first drain electrode and the second drain electrode are electrically connected, the first source electrode and the second source electrode are electrically connected, and the pixel electrode is electrically connected with at least one of the first drain electrode and the second drain electrode.
  • an orthographic projection of the gate electrode on the base substrate falls into an orthographic projection of the first active layer and the second active layer on the base substrate.
  • the array substrate further including: a first via hole, located in the first insulating layer and the second insulating layer and partially exposing the first drain electrode, the second drain electrode is connected with the first drain electrode through the first via hole.
  • the array substrate further includes a passivation layer, located at a side of the second drain electrode and the second source electrode away from the second active layer, the pixel electrode is located between the second drain electrode and the passivation layer and is in partial contact with the second drain electrode.
  • the array substrate further includes a second via hole, located in the first insulating layer and the second insulating layer and partially exposing the first source electrode, the second source electrode is connected with the first source electrode through the second via hole.
  • the array substrate further includes a passivation layer, located at a side of the second drain electrode and the second source electrode away from the second active layer; a third via hole, located in the first insulating layer, the second insulating layer, the second drain electrode and the passivation layer and partially exposing the first drain electrode; and a first conductive structure, located in the third via hole to electrically connect the first drain electrode and the second drain electrode.
  • the array substrate further includes a fourth via hole, located in the first insulating layer, the second insulating layer, the second source electrode and the passivation layer and partially exposing the first source electrode; and a second conductive structure, located in the fourth via hole to electrically connect the first source electrode and the second source electrode.
  • the pixel electrode is located between the second drain electrode and the passivation layer and is in partial contact with the second drain electrode.
  • the array substrate further includes a fifth via hole, located in the passivation layer and partially exposing a portion of the pixel electrode being in contact with the second drain electrode, the first conductive structure is further located in the fifth via hole.
  • the pixel electrode includes the first conductive structure.
  • At least one embodiment of the present disclosure provides a display device, which includes any one of the abovementioned array substrate.
  • At least one embodiment of the present disclosure provides a manufacturing method of an array substrate, which includes: forming a first active layer on a base substrate; forming a first drain electrode and a first source electrode on the base substrate to be in partial contact with the first active layer, respectively; forming a first insulating layer at a side of the first active layer, the first source electrode and the first drain electrode away from the base substrate; forming a gate electrode at a side of the first insulating layer away from the first active layer; forming a second insulating layer at a side of the gate electrode away from the first insulating layer; forming a second active layer at a side of the second insulating layer away from the gate electrode; forming a second drain electrode and a second source electrode at a side of the second insulating layer away from the gate electrode to be in partial contact with the second active layer; and forming a pixel electrode, the first source electrode and the second source electrode are electrically connected, the first drain electrode and the second drain electrode are electrically connected, the pixel electrode is
  • the manufacturing method includes: etching the first insulating layer and the second insulating layer to form a first via hole partially exposing the first source electrode and a second via hole partially exposing the first drain electrode, the second source electrode is connected with the first source electrode through the first via hole, the second drain electrode is connected with the first drain electrode through the second via hole.
  • forming the second active layer at a side of the second insulating layer away from the gate electrode includes: forming a second semiconductor layer at a side of the second insulating layer away from the gate electrode; and patterning the second semiconductor layer to form the second active layer, patterning the second semiconductor layer to form the second active layer and etching the first insulating layer and the second insulating layer to form the first via hole and the second via hole are formed through a mask process.
  • the manufacturing method further includes: forming a passivation layer at a side of the pixel electrode away from the base substrate, the passivation layer is disposed at a side of the second drain electrode and the second source electrode away from the second active layer.
  • the manufacturing method of the array substrate provided by an embodiment of the present disclosure further includes: forming a common electrode at a side of the passivation layer away from the base substrate.
  • a dual thin film transistor (Dual-TFT) structure In order to allow a TFT-LCD to have a faster responding speed and a higher charging efficiency, a dual thin film transistor (Dual-TFT) structure is widely applied. As illustrated by Fig. 1 , a Dual-TFT structure includes a gate line 1, a gate electrode 2 electrically connected with the gate line 1, a data line 3, a source electrode 4 electrically connected with the data line 3, a drain electrode 5, and a pixel electrode 6 electrically connected with the drain electrode 5.
  • a dual-TFT structure includes a gate line 1, a gate electrode 2 electrically connected with the gate line 1, a data line 3, a source electrode 4 electrically connected with the data line 3, a drain electrode 5, and a pixel electrode 6 electrically connected with the drain electrode 5.
  • the source electrode 4 includes a first source electrode 41 and a second source electrode 42
  • the drain electrode 5 includes a drain electrode 51 and a second drain electrode 52
  • the first source electrode 41 and the first drain electrode 51 are disposed opposite to each other
  • the second source electrode 42 and the second drain electrode 52 are disposed opposite to each other
  • the first source electrode 41, the second source electrode 42, the first drain electrode 51 and the second drain electrode 52 share the gate electrode 2.
  • Embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a display device.
  • the array substrate includes a base substrate, a first active layer located on the base substrate, a first insulating layer located on the first active layer and the base substrate, a gate electrode located at a side of the first insulating layer away from the first active layer, a second insulating layer located on the gate electrode and the first insulating layer, a second active layer located at a side of the second insulating layer away from the gate electrode, a first drain electrode and a first source electrode being in partial contact with the first active layer, respectively, a second drain electrode and a second source electrode being in partial contact with the second active layer, and a pixel electrode.
  • the first source electrode and the second source electrode are electrically connected, the first drain electrode and the second drain electrode are electrically connected, the pixel electrode is electrically connected with at least one of the first drain electrode and the second drain electrode.
  • FIG. 2 illustrates a sectional schematic diagram of an array substrate.
  • the array substrate includes a base substrate 101, a first active layer 102 located on the base substrate 101, a first insulating layer 103 located on the first active layer 102 and the base substrate 101, a gate electrode 104 located at a side of the first insulating layer 103 away from the first active layer 102, a second insulating layer 105 located on the gate electrode 104 and the first insulating layer 103, a second active layer 106 located at a side of the second insulating layer 105 away from the gate electrode 104, a first drain electrode 1071 and a first source electrode 1072 being in partial contact with the first active layer 102, respectively, a second drain electrode 1081 and a second source electrode 1082 being in partial contact with the second active layer 106, and a pixel electrode 109.
  • the first source electrode 1072 and the second source electrode 1082 are electrically connected, the first drain electrode 1071 and the second drain electrode 1081 are electrically connected, and the pixel electrode 109 is electrically connected with at least one of the first drain electrode 1071 and the second drain electrode 1081.
  • a region of the first active layer 102 contacting the first source electrode 1072 is a source electrode region, a region of the first active layer 102 contacting the first drain electrode 1071 is a drain electrode region, and a region of the first active layer 102 between the source electrode region and the drain electrode region is a channel region; a region of the second active layer 106 contacting the second source electrode 1082 is a source electrode region, a region of the second active layer 106 contacting the second drain electrode 1081 is a drain electrode region, and a region of the second active layer 106 between the source electrode region and the drain electrode region is a channel region.
  • the first source electrode and the second source electrode are electrically connected, the first drain electrode and the second drain electrode are electrically connected, the pixel electrode is electrically connected with an electrical signal through at least one of the first drain electrode and the second drain electrode, and is simultaneously connected with the first drain electrode and the second drain electrode.
  • the gate electrode can simultaneously control the channel regions of the first active layer and the second active layer.
  • the array substrate can improve the responding speed and charging efficiency. For example, an electrical signal can enter from the first source electrode be spread to the second source electrode, and be transferred to the first drain electrode and the second drain electrode through the channel regions of the first active layer and the second active layer, so as to utilize a single gate electrode to control two channels, thereby avoiding a delay.
  • Fig. 3 is a top view of the array substrate, as illustrated by Fig. 3 , orthographic projections of the second active layer, the second drain electrode and the second source electrode on the base substrate are overlapped with the orthographic projections of the first active layer, the first drain electrode and the first source electrode on the base substrate, so that the array substrate does not increase the area occupied by thin film transistor switches and reduce the aperture opening ratio.
  • the first drain electrode 1071 and the first source electrode 1072 are respectively lapped on the first active layer 102; the second drain electrode 1081 and the second source electrode 1082 are respectively lapped on the second active layer 106.
  • a distance between the first drain electrode 1071 and the base substrate 101 is smaller than a distance between the second drain electrode 1081 and the base substrate 101, and a distance between the first source electrode 1072 and the base substrate 101 is smaller than a distance between the second source 1082 and the base substrate 101; that is to say, there are other layer structures located between the first drain electrode 1071 and the second drain electrode 1081, for example, a first insulating layer 103 and a second insulating layer 105. Similarly, there are other layer structures located between the first source electrode 1072 and the second source electrode 1082, for example, a first insulating layer 103 and a second insulating layer 105.
  • an orthographic projection of the gate electrode 104 on the base substrate 101 falls into an orthographic projection of the first active layer 102 and the second active layer 106 on the base substrate 101. That is to say, the gate electrode 104 is disposed corresponding to the channel region of the first active layer 102 and the channel region of the second active layer 106. Thus, it can be guaranteed that the gate electrode can control the channel regions of the first active layer and the second active layer.
  • the array substrate further includes a first via hole 121 located in the first insulating layer 103 and the second insulating layer 105 and partially exposing the first drain electrode 1071, the second drain electrode 1081 is electrically connected with the first drain electrode 1071 through the first via hole 121.
  • the first drain electrode and the second drain electrode are electrically connected through the first via hole.
  • the array substrate further includes a second via hole 122 located in the first insulating layer 103 and the second insulating layer 105 and partially exposing the first source electrode 1072, the second source electrode 1082 is electrically connected with the first source electrode 1072 through the second via hole 122.
  • the first source electrode and the second source electrode are electrically connected through the second via hole.
  • the array substrate further includes a passivation layer 110 located at a side of the second drain electrode 1081 and the second source electrode 1082 away from the second active layer 106, the pixel electrode 109 is located between the second drain electrode 1081 and the passivation layer 110, and is in partial contact with the second drain electrode 1081.
  • the pixel electrode 109 can be lapped on the second drain electrode 1081.
  • the array substrate does not use a via hole to connect the pixel electrode and the second drain electrode, so as to simplify the structure of the array substrate and improve the stability.
  • the embodiments of the present disclosure comprise but are not limited thereto, the pixel electrode can be disposed on the passivation layer and electrically connected with the second drain electrode through the via hole.
  • the array substrate further includes a common electrode line 111, located in a same layer with the gate electrode 104.
  • the common electrode line can be disposed in other layers, and the embodiments of the present disclosure are not limited thereto.
  • the array substrate further includes a common electrode 112, located on the passivation layer 110 and electrically connected with the common electrode line 111 through a via hole 113.
  • FIG. 4a illustrates a sectional schematic diagram of another array substrate.
  • the array substrate further includes a passivation layer 110, the passivation layer 110 is disposed at a side of the second drain electrode 1081 and the second source electrode 1082 away from the second active layer 106.
  • the array substrate further includes a third via hole 123 located in the first insulating layer 103, a second insulating layer 105, the second drain electrode 1081 and the passivation layer 110 and partially exposing the first drain electrode 1071, and a first conductive structure 114 located in the third via hole 123 to electrically connect the first drain electrode 1071 and the second drain electrode 1081.
  • the first drain electrode 1071 and the second drain electrode 1081 are electrically connected through the first conductive structure 114 and the third via hole 123.
  • the array substrate further includes a fourth via hole 124 located in the first insulating layer 103, the second insulating layer 105, the second source electrode 1082 and the passivation layer 110 and partially exposing the first source electrode 1072, and a second conductive structure 115 located in the fourth via hole 124 to electrically connect the first source electrode 1072 and the second source electrode 1082.
  • the first source electrode 1072 and the second source electrode 1082 arc electrically connected through the second conductive structure 115 and the fourth via hole 124.
  • the array substrate includes a common electrode line 111 and a common electrode 112, the common electrode 112 is electrically connected with the common electrode line 111 through the via hole 113.
  • the third via hole 123 and/or the forth via hole 124 and the via hole 113 can be formed through a mask process, so as to save processes and save the costs.
  • the pixel electrode 109 is disposed between the second drain electrode 1081 and the passivation layer 110 and is in partial contact with the second drain electrode 1081, so as to be electrically connected with the second drain electrode 1081.
  • the pixel electrode 109 can be lapped on the second drain electrode 1081.
  • the array substrate does not use a via hole to connect the pixel electrode and the second drain electrode, so as to be able to simplify the structure of the array substrate, and improve the stability.
  • the embodiments of the present disclosure comprise but are not limited thereto, and the pixel electrode can be disposed on the passivation layer and electrically connected with the second drain electrode through the via hole.
  • the array substrate further includes a fifth via hole 125 located in the passivation layer 110 and partially exposing a portion of the pixel electrode 109 contacting the second drain electrode 1081, and the first conductive structure 114 is further disposed in the fifth via hole 125.
  • the stability of the electrical connection of the pixel electrode and the second drain electrode can be further improved.
  • the pixel electrode 109 includes a first conductive structure 114, that is to say, the first conductive structure 114 can be a part of the pixel electrode 109.
  • the pixel electrode upon the array substrate provided by the present embodiment adopting a TN structure, i.e., upon the array substrate being only provided with a pixel electrode, the pixel electrode includes a first conductive structure, which can increase the stability and reliability of the connection of the pixel electrode and the first drain electrode and the second drain electrode, and can further increase the aperture opening ratio.
  • An embodiment of the present disclosure provides a display device, which includes the array substrate according to any one of the abovementioned embodiments.
  • the display device has favorable effects corresponding to the favorable effects of the array substrate according to any one of the abovementioned embodiments, the favorable effects can refer to the relevant descriptions in the abovementioned embodiments for details, and the repeated portions are omitted herein.
  • the display device because the display device has a relatively fast responding speed and a relatively fast charging efficiency, the display device can be applied to a display device with a large size, such as a television and a stage screen.
  • An embodiment of the present disclosure provides a manufacturing method of an array substrate, as illustrated by Fig. 5 , the manufacturing method of the array substrate includes the following steps S401-S408.
  • Step S401 as illustrated by Fig. 6a , forming a first active layer 102 on a base substrate 101.
  • the base substrate can be selected as a glass substrate, a quartz substrate, and a plastic substrate; the material of the first active layer can adopt oxide semiconductor, amorphous silicon, poly-silicon and so on.
  • the embodiments of the present disclosure comprise but are not limited thereto.
  • Step S402 as illustrated by Fig. 6b , forming a first drain electrode 1071 and a first source electrode 1072 on a base substrate 101 to be in partial contact with the first active layer 102.
  • the first drain electrode 1071 and the first source electrode 1072 are respectively lapped at two sides of the first active layer 102, i.e., a source electrode region and a drain electrode region of the first active layer 102.
  • the first drain electrode 1071 and the first source electrode 1072 are disposed at a side of the first active layer 102 away from the base substrate 101.
  • the first drain electrode 1071 and the first source electrode 1072 can also be disposed at a side of the first active layer 102 close to the base substrate, and the embodiments of the present disclosure are not limited thereto.
  • Step S403 as illustrated by Fig. 6c , forming a first insulating layer 103 at a side of the first active layer 102, the first source electrode 1072, and a first drain electrode 1071 away from the base substrate 101.
  • the material of the first insulating layer can adopt an organic insulating material or an inorganic insulating material, and the embodiments of the present disclosure are not limited thereto.
  • Step S404 as illustrated by Fig. 6d , forming a gate electrode 104 at a side of the first insulating layer 103 away from the first active layer 102.
  • the material of the gate electrode can be one or more selected from a group consisting of aluminum, aluminum alloy, copper, copper alloy, molybdenum, and molybdenum alloy.
  • Step S405 as illustrated by Fig. 6e , forming a second insulating layer 105 at a side of the gate electrode 104 away from the first insulating layer 103.
  • the material of the second insulating layer can adopt an organic insulating material or an inorganic insulating layer, and the embodiments of the present disclosure are not limited thereto.
  • Step S406 as illustrated by Fig. 6f , forming a second active layer 106 at a side of the second insulating layer 105 away from the gate electrode 104.
  • the material of the second active layer can adopt oxide semiconductor, amorphous silicon, poly-silicon, or the like; certainly, the embodiments of the present disclosure comprise are not limited thereto.
  • Step S407 as illustrated by Fig. 6g , forming a second drain electrode 1081 and a second source electrode 1082 at a side of the second insulating layer 105 away from the gate electrode 104 to be in partial contact with the second active layer 106.
  • the second drain electrode 1081 and the second source electrode 1082 are electrically connected with the first drain electrode 1071 and the first source electrode 1072 through via holes, respectively.
  • Step S408 as illustrated by Fig. 6h , forming a pixel electrode, the pixel electrode is electrically connected with at least one of the first drain electrode and the second drain electrode.
  • the first source electrode and the second source electrode are electrically connected, the first drain electrode and the second drain electrode are electrically connected, the pixel electrode is electrically connected with an electrical signal through at least one of the first drain electrode and the second drain electrode, and is simultaneously connected with the first drain electrode and the second drain electrode.
  • the gate electrode can simultaneously control the channel regions of the first active layer and the second active layer.
  • the array substrate can improve the responding speed and charging efficiency. For example, an electrical signal can enter from the first source electrode, be spread to the second source electrode, and be transferred to the first drain electrode and the second drain electrode through the channel regions of the first active layer and the second active layer, so as to utilize a single gate electrode to control two channels, thereby avoiding a delay.
  • the array substrate does not increase the area occupied by thin film transistor switches and reduce the aperture opening ratio.
  • the orthographic projections of the second active layer, the second drain electrode and the second source electrode are overlapped with the orthographic projections of the first active layer, the first drain electrode, and the first source electrode, the array substrate does not increase the area occupied by thin film transistor switches and reduce the aperture opening ratio.
  • step S406 i.e., after forming the second active layer at a side of the second insulating layer away from the gate electrode, as illustrated by Fig. 7 , etching the first insulating layer 103 and the second insulating layer 105 to form a first via hole 121 partially exposing the first source electrode 1072 and a second via hole 122 partially exposing the first drain electrode 1071.
  • the second source electrode 1082 is connected with the first source electrode 1072 through the first via hole 121
  • the second drain electrode 1081 is connected with the first drain electrode 1071 through the second via hole 122.
  • the processing steps can be saved, and the manufacturing costs can be reduced.
  • the manufacturing method further includes: forming a passivation layer 110 on the formed substrate.
  • the manufacturing method of the array substrate further includes a common electrode line 111, for example, the common electrode line 111 and the gate electrode 104 are formed in a same layer.
  • the common electrode line can be formed in the other layer, and the embodiments of the present disclosure are not limited thereto.
  • the array substrate further includes: etching a via hole 113 in the passivation layer 110 and the second insulating layer 105.
  • the manufacturing method of the array substrate further includes forming a common electrode 112 on the passivation layer 110, the common electrode 112 is electrically connected with the common electrode line 111 through the via hole 113.
  • step S408 i.e., forming a pixel electrode, as illustrated by Fig. 9a , forming a passivation layer 110 on the formed substrate, and the passivation layer 110 is disposed at a side of the second drain electrode 1081 and the second source electrode 1082 away from the second active layer 106.
  • a third via hole 123 partially exposing the first drain electrode 1071 and a fourth via hole 124 partially exposing the first source electrode 1072 in the first insulating layer 103, the second insulating layer 105, the second drain electrode 1081 and the passivation layer 110.
  • a first conductive structure 114 in the third via hole 123 to electrically connect the first drain electrode 1071 and the second drain electrode 1081; forming a second conductive structure 115 in the fourth via hole 124 to electrically connect the first source electrode 1072 and the second source electrode 1082.
  • first drain electrode 1071 and the second drain electrode 1081 are electrically connected through the first conductive structure 114 and the third via hole 123.
  • first conductive structure 114 and the second conductive structure 115 can be formed by a same conductive layer through a patterning process, and the first source electrode 1072 and the second source electrode 1082 are electrically connected through the second conductive structure 115 and the fourth via hole 124.
  • the embodiments of the present disclosure comprise but are not limited thereto.
  • the manufacturing method of the array substrate further includes a fifth via hole 125 partially exposing a portion of the pixel electrode 109 contacting the second drain electrode 1081 in the passivation layer 110.
  • the pixel electrode 109 and the second drain electrode 1081 can be electrically connected by further disposing the first conductive structure 114 in the fifth via hole 125, so as to further improve the reliability of the electric connection between the pixel electrode and the second drain electrode.
  • the step of forming the fifth via hole and the step of forming the third via hole and the fourth via hole can be accomplished through a mask process.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
EP17851942.7A 2017-02-08 2017-09-21 Substrat de réseau, et dispositif d'affichage Withdrawn EP3588562A4 (fr)

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WO2023272480A1 (fr) * 2021-06-29 2023-01-05 京东方科技集团股份有限公司 Substrat d'affichage, dispositif d'affichage et procédé de fabrication de substrat d'affichage
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CN108400139A (zh) 2018-08-14
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US20180374874A1 (en) 2018-12-27
WO2018145465A1 (fr) 2018-08-16

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