EP3711092A4 - Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication - Google Patents

Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication Download PDF

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Publication number
EP3711092A4
EP3711092A4 EP18878898.8A EP18878898A EP3711092A4 EP 3711092 A4 EP3711092 A4 EP 3711092A4 EP 18878898 A EP18878898 A EP 18878898A EP 3711092 A4 EP3711092 A4 EP 3711092A4
Authority
EP
European Patent Office
Prior art keywords
wordlines
thickened
production
storage device
dimensional storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18878898.8A
Other languages
German (de)
English (en)
Other versions
EP3711092A1 (fr
Inventor
Senaka Krishna Kanakamedala
Yoshihiro Kanno
Raghuveer S. Makala
Yanli Zhang
Jin Liu
Murshed CHOWDHURY
Yao-Sheng Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
SanDisk Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/813,625 external-priority patent/US10453854B2/en
Priority claimed from US15/813,579 external-priority patent/US10461163B2/en
Application filed by SanDisk Technologies LLC filed Critical SanDisk Technologies LLC
Priority to EP21173855.4A priority Critical patent/EP3893277A1/fr
Publication of EP3711092A1 publication Critical patent/EP3711092A1/fr
Publication of EP3711092A4 publication Critical patent/EP3711092A4/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
EP18878898.8A 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication Pending EP3711092A4 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP21173855.4A EP3893277A1 (fr) 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/813,625 US10453854B2 (en) 2017-11-15 2017-11-15 Three-dimensional memory device with thickened word lines in terrace region
US15/813,579 US10461163B2 (en) 2017-11-15 2017-11-15 Three-dimensional memory device with thickened word lines in terrace region and method of making thereof
PCT/US2018/052227 WO2019099103A1 (fr) 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP21173855.4A Division EP3893277A1 (fr) 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication

Publications (2)

Publication Number Publication Date
EP3711092A1 EP3711092A1 (fr) 2020-09-23
EP3711092A4 true EP3711092A4 (fr) 2020-12-02

Family

ID=66538741

Family Applications (2)

Application Number Title Priority Date Filing Date
EP18878898.8A Pending EP3711092A4 (fr) 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication
EP21173855.4A Pending EP3893277A1 (fr) 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP21173855.4A Pending EP3893277A1 (fr) 2017-11-15 2018-09-21 Dispositif de mémoire tridimensionnel avec lignes de mots plus épaisses dans une région de terrasse et son procédé de fabrication

Country Status (4)

Country Link
EP (2) EP3711092A4 (fr)
KR (1) KR102235246B1 (fr)
CN (1) CN111149206B (fr)
WO (1) WO2019099103A1 (fr)

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KR102697629B1 (ko) * 2019-07-18 2024-08-26 삼성전자주식회사 게이트 영역 및 절연 영역을 갖는 적층 구조물을 포함하는 반도체 소자
CN111201602B (zh) * 2019-11-22 2021-04-27 长江存储科技有限责任公司 存储器件以及其混合间隔物
KR102689656B1 (ko) 2019-12-10 2024-07-30 삼성전자주식회사 반도체 소자
CN111801797B (zh) * 2020-05-27 2021-05-25 长江存储科技有限责任公司 用于形成三维存储器件的方法
WO2021237491A1 (fr) 2020-05-27 2021-12-02 Yangtze Memory Technologies Co., Ltd. Dispositifs de mémoire tridimensionnels
WO2021237488A1 (fr) 2020-05-27 2021-12-02 Yangtze Memory Technologies Co., Ltd. Dispositifs de mémoire tridimensionnels
WO2021237489A1 (fr) 2020-05-27 2021-12-02 Yangtze Memory Technologies Co., Ltd. Procédés de formation de dispositifs de mémoire tridimensionnels
US11610842B2 (en) * 2020-12-02 2023-03-21 Macronix International Co., Ltd. Memory device and method of manufacturing the same
CN118742041A (zh) 2021-03-22 2024-10-01 长江存储科技有限责任公司 三维存储器件及其形成方法
EP4282004A4 (fr) 2021-03-22 2024-11-27 Yangtze Memory Technologies Co., Ltd. Dispositifs de mémoire tridimensionnels et procédés de formation de ceux-ci
CN113169188B (zh) 2021-03-22 2024-08-06 长江存储科技有限责任公司 三维存储器件及其形成方法
CN113950742B (zh) * 2021-08-30 2025-10-03 长江存储科技有限责任公司 三维nand存储器器件及其形成方法
CN114023752B (zh) * 2021-10-29 2025-08-29 长江存储科技有限责任公司 半导体器件及其制备方法、三维存储器、电子设备
CN114883332A (zh) * 2022-03-11 2022-08-09 长江存储科技有限责任公司 三维存储器及其制备方法、存储系统
CN114823689B (zh) * 2022-04-20 2026-03-24 上海华力集成电路制造有限公司 存储器的制造方法

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US20150179564A1 (en) * 2013-12-20 2015-06-25 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US20150287710A1 (en) * 2014-04-08 2015-10-08 Tae-Hwan YUN Semiconductor devices having conductive pads and methods of fabricating the same
US20170271354A1 (en) * 2016-03-15 2017-09-21 SK Hynix Inc. Semiconductor device

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KR101787041B1 (ko) * 2010-11-17 2017-10-18 삼성전자주식회사 식각방지막이 구비된 반도체 소자 및 그 제조방법
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KR102134912B1 (ko) * 2014-03-21 2020-07-20 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US9728546B2 (en) * 2014-09-05 2017-08-08 Sandisk Technologies Llc 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same
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US9685408B1 (en) * 2016-04-14 2017-06-20 Macronix International Co., Ltd. Contact pad structure and method for fabricating the same
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US20140191389A1 (en) * 2013-01-07 2014-07-10 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US20150179564A1 (en) * 2013-12-20 2015-06-25 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US20150287710A1 (en) * 2014-04-08 2015-10-08 Tae-Hwan YUN Semiconductor devices having conductive pads and methods of fabricating the same
US20170271354A1 (en) * 2016-03-15 2017-09-21 SK Hynix Inc. Semiconductor device

Also Published As

Publication number Publication date
CN111149206A (zh) 2020-05-12
KR20200035473A (ko) 2020-04-03
CN111149206B (zh) 2023-08-18
KR102235246B1 (ko) 2021-04-02
EP3711092A1 (fr) 2020-09-23
WO2019099103A1 (fr) 2019-05-23
EP3893277A1 (fr) 2021-10-13

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Owner name: SANDISK TECHNOLOGIES, INC.