EP3888128A4 - Speicheranordnungen und verfahren zur herstellung einer speicheranordnung - Google Patents

Speicheranordnungen und verfahren zur herstellung einer speicheranordnung Download PDF

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Publication number
EP3888128A4
EP3888128A4 EP19889842.1A EP19889842A EP3888128A4 EP 3888128 A4 EP3888128 A4 EP 3888128A4 EP 19889842 A EP19889842 A EP 19889842A EP 3888128 A4 EP3888128 A4 EP 3888128A4
Authority
EP
European Patent Office
Prior art keywords
memory
forming
methods used
networks
network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19889842.1A
Other languages
English (en)
French (fr)
Other versions
EP3888128A1 (de
Inventor
Yoshiaki Fukuzumi
M. Jared BARCLAY
Emilio Camerlenghi
Paolo Tessariol
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP3888128A1 publication Critical patent/EP3888128A1/de
Publication of EP3888128A4 publication Critical patent/EP3888128A4/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
EP19889842.1A 2018-11-26 2019-10-10 Speicheranordnungen und verfahren zur herstellung einer speicheranordnung Pending EP3888128A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/200,158 US10756105B2 (en) 2018-11-26 2018-11-26 Memory arrays and methods used in forming a memory array
PCT/US2019/055521 WO2020112256A1 (en) 2018-11-26 2019-10-10 Memory arrays and methods used in forming a memory array

Publications (2)

Publication Number Publication Date
EP3888128A1 EP3888128A1 (de) 2021-10-06
EP3888128A4 true EP3888128A4 (de) 2022-01-26

Family

ID=70771567

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19889842.1A Pending EP3888128A4 (de) 2018-11-26 2019-10-10 Speicheranordnungen und verfahren zur herstellung einer speicheranordnung

Country Status (7)

Country Link
US (1) US10756105B2 (de)
EP (1) EP3888128A4 (de)
JP (1) JP2022507989A (de)
KR (1) KR20210080571A (de)
CN (1) CN113039644B (de)
TW (1) TWI728529B (de)
WO (1) WO2020112256A1 (de)

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KR102830364B1 (ko) * 2019-06-11 2025-07-04 삼성전자주식회사 수직형 반도체 장치 및 그의 제조 방법
US11069598B2 (en) * 2019-06-18 2021-07-20 Micron Technology, Inc. Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs)
US11037944B2 (en) 2019-07-10 2021-06-15 Micron Technology, Inc. Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias
US10985179B2 (en) 2019-08-05 2021-04-20 Micron Technology, Inc. Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias
US11527630B2 (en) * 2020-06-24 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for fabricating the same
US11744069B2 (en) * 2020-08-27 2023-08-29 Micron Technology, Inc. Integrated circuitry and method used in forming a memory array comprising strings of memory cells
US11581330B2 (en) * 2020-11-06 2023-02-14 Micron Technology, Inc. Memory array and method used in forming a memory array comprising strings of memory cells
US11974429B2 (en) 2020-11-06 2024-04-30 Micron Technology, Inc. Method used in forming a memory array comprising strings of memory cells and using bridges in sacrificial material in a tier
US11915974B2 (en) * 2021-04-12 2024-02-27 Micron Technology, Inc. Integrated circuitry, a memory array comprising strings of memory cells, a method used in forming a conductive via, a method used in forming a memory array comprising strings of memory cells
US11948639B2 (en) * 2021-07-06 2024-04-02 Micron Technology, Inc. Methods including a method of forming a stack and isotropically etching material of the stack
KR20230016411A (ko) * 2021-07-26 2023-02-02 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조방법
US12598972B2 (en) * 2021-08-10 2026-04-07 Micron Technology, Inc. Methods used in forming a memory array comprising strings of memory cells including insulator walls in a through-array-via region
US12068255B2 (en) * 2021-08-11 2024-08-20 Micron Technology, Inc. Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
US12230325B2 (en) 2021-08-23 2025-02-18 Micron Technology, Inc. Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
CN114391181A (zh) * 2021-08-23 2022-04-22 长江存储科技有限责任公司 三维存储装置及其形成方法
CN114631185B (zh) 2021-08-23 2026-04-07 长江存储科技有限责任公司 三维存储装置及其形成方法
US12198762B2 (en) * 2021-08-23 2025-01-14 Micron Technology, Inc. Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
US12040253B2 (en) 2021-09-01 2024-07-16 Micron Technology, Inc. Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
KR102914380B1 (ko) 2021-10-07 2026-01-20 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US12439592B2 (en) 2021-10-13 2025-10-07 Micron Technology, Inc. Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
KR20230103389A (ko) * 2021-12-31 2023-07-07 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
KR20230134281A (ko) 2022-03-14 2023-09-21 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 제조 방법
US20230380158A1 (en) * 2022-05-17 2023-11-23 Micron Technology, Inc. Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
US12525536B2 (en) * 2022-08-31 2026-01-13 Micron Technology, Inc. Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
US12499944B2 (en) 2022-08-31 2025-12-16 Micron Technology, Inc. Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

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Also Published As

Publication number Publication date
JP2022507989A (ja) 2022-01-18
WO2020112256A1 (en) 2020-06-04
CN113039644B (zh) 2024-10-25
CN113039644A (zh) 2021-06-25
KR20210080571A (ko) 2021-06-30
TW202038444A (zh) 2020-10-16
US10756105B2 (en) 2020-08-25
TWI728529B (zh) 2021-05-21
US20200168622A1 (en) 2020-05-28
EP3888128A1 (de) 2021-10-06

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