EP3931870A4 - Quellenstruktur einer dreidimensionalen speichervorrichtung und herstellungsverfahren dafür - Google Patents

Quellenstruktur einer dreidimensionalen speichervorrichtung und herstellungsverfahren dafür Download PDF

Info

Publication number: EP3931870A4
Authority: EP; European Patent Office
Prior art keywords: forming; memory devices; dimensional memory; staircase structure; staircase
Prior art date: 2020-03-23
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

EP20926360.7A

Other languages

English (en)

French (fr)

Other versions

EP3931870A1 (de

EP3931870B1 (de

Inventor

Zhong Zhang

Zhongwang SUN

Wenxi Zhou

Zhiliang Xia

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Yangtze Memory Technologies Co Ltd

Original Assignee

Yangtze Memory Technologies Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2020-03-23

Filing date

2020-03-23

Publication date

2022-06-22

Family has litigation

First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=72074022&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP3931870(A4) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.

2020-03-23 Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd

2020-03-23 Priority to EP24174671.8A priority Critical patent/EP4391762A3/de

2022-01-05 Publication of EP3931870A1 publication Critical patent/EP3931870A1/de

2022-06-22 Publication of EP3931870A4 publication Critical patent/EP3931870A4/de

2024-05-15 Application granted granted Critical

2024-05-15 Publication of EP3931870B1 publication Critical patent/EP3931870B1/de

Status Active legal-status Critical Current

2040-03-23 Anticipated expiration legal-status Critical

Links

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

EP20926360.7A 2020-03-23 2020-03-23 Quellenstruktur einer dreidimensionalen speichervorrichtung und herstellungsverfahren dafür Active EP3931870B1 (de)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
EP24174671.8A EP4391762A3 (de)	2020-03-23	2020-03-23	Treppenstruktur in einer dreidimensionalen speichervorrichtung und verfahren zur formung davon

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
PCT/CN2020/080670 WO2021189190A1 (en)	2020-03-23	2020-03-23	Staircase structure in three-dimensional memory device and method for forming the same

Related Child Applications (2)

Application Number	Title	Priority Date	Filing Date
EP24174671.8A Division EP4391762A3 (de)	2020-03-23	2020-03-23	Treppenstruktur in einer dreidimensionalen speichervorrichtung und verfahren zur formung davon
EP24168497.6 Division-Into		2024-04-04

Publications (3)

Publication Number	Publication Date
EP3931870A1 EP3931870A1 (de)	2022-01-05
EP3931870A4 true EP3931870A4 (de)	2022-06-22
EP3931870B1 EP3931870B1 (de)	2024-05-15

Family

ID=72074022

Family Applications (2)

Application Number	Title	Priority Date	Filing Date
EP20926360.7A Active EP3931870B1 (de)	2020-03-23	2020-03-23	Quellenstruktur einer dreidimensionalen speichervorrichtung und herstellungsverfahren dafür
EP24174671.8A Pending EP4391762A3 (de)	2020-03-23	2020-03-23	Treppenstruktur in einer dreidimensionalen speichervorrichtung und verfahren zur formung davon

Family Applications After (1)

Application Number	Title	Priority Date	Filing Date
EP24174671.8A Pending EP4391762A3 (de)	2020-03-23	2020-03-23	Treppenstruktur in einer dreidimensionalen speichervorrichtung und verfahren zur formung davon

Country Status (7)

Country	Link
US (3)	US11696439B2 (de)
EP (2)	EP3931870B1 (de)
JP (2)	JP7375039B2 (de)
KR (2)	KR20240095301A (de)
CN (2)	CN113270414B (de)
TW (1)	TWI743768B (de)
WO (1)	WO2021189190A1 (de)

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WO2022094796A1 (en) *	2020-11-04	2022-05-12	Yangtze Memory Technologies Co., Ltd.	Bottom select gate contacts for center staircase structures in three-dimensional memory devices
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2020
- 2020-03-23 KR KR1020247017644A patent/KR20240095301A/ko active Pending
- 2020-03-23 KR KR1020217033164A patent/KR102671265B1/ko active Active
- 2020-03-23 EP EP20926360.7A patent/EP3931870B1/de active Active
- 2020-03-23 JP JP2021561773A patent/JP7375039B2/ja active Active
- 2020-03-23 CN CN202110538898.8A patent/CN113270414B/zh active Active
- 2020-03-23 CN CN202080000610.5A patent/CN111566813B/zh active Active
- 2020-03-23 EP EP24174671.8A patent/EP4391762A3/de active Pending
- 2020-03-23 WO PCT/CN2020/080670 patent/WO2021189190A1/en not_active Ceased
- 2020-05-05 TW TW109114900A patent/TWI743768B/zh active
- 2020-05-22 US US16/881,168 patent/US11696439B2/en active Active
2023
- 2023-05-08 US US18/144,650 patent/US12232313B2/en active Active
2024
- 2024-12-24 US US19/001,214 patent/US20250133734A1/en active Pending
2026
- 2026-01-15 JP JP2026005271A patent/JP2026050497A/ja active Pending

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Also Published As

Publication number	Publication date
CN113270414B (zh)	2024-09-13
US11696439B2 (en)	2023-07-04
TW202137407A (zh)	2021-10-01
KR102671265B1 (ko)	2024-05-31
CN111566813A (zh)	2020-08-21
JP7375039B2 (ja)	2023-11-07
KR20240095301A (ko)	2024-06-25
WO2021189190A1 (en)	2021-09-30
TWI743768B (zh)	2021-10-21
EP4391762A3 (de)	2024-12-18
US20230276620A1 (en)	2023-08-31
US20210296334A1 (en)	2021-09-23
EP3931870A1 (de)	2022-01-05
US12232313B2 (en)	2025-02-18
KR20210141563A (ko)	2021-11-23
EP3931870B1 (de)	2024-05-15
US20250133734A1 (en)	2025-04-24
CN113270414A (zh)	2021-08-17
JP2023181313A (ja)	2023-12-21
JP2026050497A (ja)	2026-03-19
CN111566813B (zh)	2021-05-14
JP2022530357A (ja)	2022-06-29
EP4391762A2 (de)	2024-06-26

Legal Events

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