Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
  • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
  • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
  • H10D30/6739—Conductor-insulator-semiconductor electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0167—Manufacturing their channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

• the present invention relates to a method of manufacturing a semiconductor-on-insulator substrate for radiofrequency applications.
• Radio frequency electronic components formed in or on semiconductor substrates are particularly sensitive to attenuation phenomena caused by the properties of said substrates.
• semiconductor substrates in particular solid silicon, having a high electrical resistivity, that is to say greater than 500 Q.cm.
• semiconductor-on-insulator substrates of the FDSOI type appear to be interesting alternatives to semi-conductor substrates.
• the FDSOI substrates successively comprise a support substrate, an electrically insulating layer and a thin semiconductor layer in or on which electronic components can be manufactured.
• the semiconductor layer has a sufficiently thin thickness to allow complete depletion of the conduction channel of a transistor formed in said layer.
• Such a layer typically has a thickness of a few tens of nanometers.
• the electrically insulating layer which generally consists of an oxide, is also frequently called BOX (acronym for the English term “Buried OXide” or buried oxide).
• BOX acronym for the English term "Buried OXide” or buried oxide.
• the manufacturing process for FDSOI substrates aims to ensure high precision of the thickness of the semiconductor layer and of the electrically insulating layer as well as high uniformity of these thicknesses, both within a substrate and a substrate. substrate to another within the same production batch.
• FIGS. 1 A to 1 C The process for manufacturing an FDSOI substrate is shown schematically in FIGS. 1 A to 1 C.
• This process implements a layer transfer from a donor substrate to a support substrate, also known under the name of the Smart Cut TM process.
• a donor substrate for example of silicon
• an electrically insulating layer for example of silicon oxide (S1O2).
• Said weakening zone 11 defines a thin layer 12 to be transferred.
• the donor substrate 1 thus implanted is glued on a support substrate 2 via the electrically insulating layer 10 which then fulfills the function of a bonding layer.
• the support substrate 2 can advantageously be a semiconductor substrate, for example of silicon, with high electrical resistivity.
• the bonding can be reinforced by heat treatment.
• the donor substrate 1 is detached along the weakening zone 11, which leads to the transfer of the thin layer 12 onto the support substrate 2.
• the initiation of the detachment can be carried out by means of 'heat treatment.
• a finishing treatment is then carried out on the transferred layer, so as to cure the defects associated with the implantation and to smooth the free surface of said layer.
• a semiconductor-on-insulator substrate is thus obtained.
• the target thickness for the transferred semiconductor layer is between 4 nm and 100 nm, with a maximum variation of ⁇ 5 ⁇ from the target value, within each substrate and between the different substrates produced by the process.
• Such uniformity and a very low roughness of the transferred layer can be obtained by a so-called “batch anneal” finishing process, which is a long smoothing process, at high temperature, advantageously carried out in an oven making it possible to treat a plurality of substrates. the same time.
• Such a “batch anneal” is typically carried out at a temperature of between 1150 and 1200 ° C., for a period of several minutes, generally greater than 15 minutes. This smoothing makes it possible to bring the transferred semiconductor layer to a level of surface roughness compatible with the subsequent manufacture of transistors.
• this method is penalizing for radiofrequency applications, in particular for extremely high frequency applications, that is to say in a frequency band between 30 and 300 GHz.
• This frequency band is also called "mmWave”.
• the support substrate has high electrical resistivity and therefore lightly doped.
• the support substrate is generally substantially less doped (for example doped with boron) than the donor substrate, in other words, less doped than the transferred thin film.
• the boron atoms diffuse through the electrically insulating layer in the support substrate, leading to a reduction in the electrical resistivity in a surface portion extending from the electrically insulating layer.
• An aim of the invention is to define a method for manufacturing a semiconductor-on-insulator substrate of the FDSOI type suitable for radiofrequency applications, making it possible to maintain a high resistivity of the support substrate even in the vicinity of the electrically insulating layer.
• the invention provides a method of manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications, comprising the following steps:
• the thin semiconductor layer and the electrically insulating layer being at the bonding interface
• formation of the sacrificial layer includes oxidation of the material of the donor substrate.
• the removal of the sacrificial layer comprises wet etching of said layer.
• the removal of the sacrificial layer can further comprise the removal of a surface portion of the thin layer to be transferred from the donor substrate.
• the donor substrate is doped with boron.
• forming the electrically insulating layer includes depositing an oxide on the support substrate.
• the formation of the electrically insulating layer is accomplished by oxidation of the support substrate.
• the electrically insulating layer has a thickness between 10 and 150 nm.
• the transferred semiconductor layer has a thickness between 4 and 100 nm.
• FIG. 1A is a schematic sectional view of the implantation of atomic species through an electrically insulating layer arranged on a donor substrate;
• Figure 1B is a schematic sectional view of the bonding of the donor substrate having undergone the implantation of Figure 1A on a support substrate;
• Figure 1C is a schematic sectional view of the transfer of a thin layer from the donor substrate to the support substrate of Figure 1B;
• FIG. 2 is a schematic sectional view of the formation of a sacrificial layer on a donor substrate
• FIG. 3 is a schematic sectional view of the implantation of atomic species in the donor substrate of Figure 2 through the sacrificial layer;
• Figure 4 is a schematic sectional view of the removal of the sacrificial layer from the donor substrate after the implantation of Figure 3;
• FIG. 5 is a schematic sectional view of the formation of an electrically insulating layer on a support substrate
• - Figure 6 is a schematic sectional view of the bonding of the donor substrate of Figure 4 and the support substrate of Figure 5;
• FIG. 7 is a schematic sectional view of the transfer of a thin layer of the donor substrate on the support substrate to form an FDSOI substrate.
• the method of manufacturing an FDSOI substrate is modified to achieve bonding of the donor substrate on the support substrate by means of an electrically insulating layer formed on the support substrate and not on the donor substrate.
• the support substrate is not doped or at least has a concentration of P-type dopants less than or equal to 1 E 13 at / cm 3 .
• the electrically insulating layer does not contain a significant concentration of dopants capable of diffusing into the support substrate during subsequent heat treatments.
• An electrically insulating layer remains useful on the surface of the donor substrate to reduce the impact of direct trajectories of atomic species during implantation (a phenomenon known as "channeling").
• this layer is sacrificial in that it is removed after implantation, before bonding.
• Figure 2 illustrates the formation of such a sacrificial layer 13 on the donor substrate 1.
• the donor substrate is a monocrystalline semiconductor substrate, for example of silicon.
• the donor substrate is lightly doped P.
• the donor substrate contains boron atoms with a concentration less than or equal to 1 E 15 at / cm 3 .
• a donor substrate thus doped is in fact less expensive and more standard than an undoped donor substrate.
• the sacrificial layer 13 is an electrically conductive layer, in particular of an oxide of the material of the donor substrate 1.
• the sacrificial layer 13 is advantageously formed by thermal oxidation of the donor substrate 1. Such thermal oxidation consumes a surface portion of the material of the donor substrate. .
• the sacrificial layer advantageously has a thickness of between 4 and 150 nm and preferably between 10 and 40 nm.
• an implantation of ionic species shown diagrammatically by the arrows) in the donor substrate 1 is implemented through the sacrificial layer.
• the implanted species usually include hydrogen and / or helium.
• the dose and energy of the implanted species is chosen to form a weakening zone 11 in the donor substrate 1, at a determined depth to define, between the sacrificial layer 13 and the weakening zone 11, a thin layer 12 to be transferred.
• the sacrificial layer 13 is then removed. Thus, even if the sacrificial layer contains dopants originating from the donor substrate, it is not present during the subsequent bonding.
• the removal of the sacrificial layer can be carried out, for example, by wet etching. Those skilled in the art are able to choose the appropriate engraving solution. This etching leaves the surface of the donor substrate sufficiently smooth and free from defects to allow subsequent bonding of good quality.
• the removal of the sacrificial layer can optionally be followed by the removal of a surface portion of the thin layer 12 to be transferred.
• the removal of this surface portion can be carried out by any suitable means, for example by thermal oxidation or by chemical etching, which makes it possible not to degrade the uniformity of the transferred layer. Less preferably, chemical mechanical polishing could be used.
• an electrically insulating layer 20 is also formed on the support substrate 2.
• the support substrate 2 is a semiconductor substrate, for example of silicon, having a high electrical resistivity, for example greater than 500 Q.cm, preferably greater than or equal to 1000 Q.cm.
• the support substrate is a silicon substrate having a high content of interstitial oxygen, that is to say a content greater than 20 old ppma (for the definition of the old ppma unit, reference may be made to to the memoir of Robert Kurt Graupner, “A Study of Oxygen Precipitation in Heavily Doped Silicon” (1989), Dissertations and Theses, Paper 1218).
• Such a substrate is generally designated by the abbreviation “HiOi”.
• the interstitial oxygen atoms are liable to precipitate under the effect of a heat treatment so as to form a large quantity of defects, called “Bulk Micro Defects" (BMD), formed by the oxygen precipitates, which block the particles.
• the method comprises, prior to bonding, a step of heat treatment of the support substrate at a temperature sufficient to precipitate the interstitial oxygen and form said BMDs.
• a heat treatment can typically by a thermal cycle reaching a temperature of the order of 1000 ° C for 12 hours.
• a HiOi substrate generally comprises a large quantity of crystal defects called COPs (acronym for the English term “crystal originated particles”), which are undesirable in an FDSOI substrate.
• the manufacturing process therefore comprises a heat treatment of the "depletion" type, aimed at diffusing the oxygen out of the support substrate.
• this treatment can be carried out simultaneously with the heat treatment for precipitation of the interstitial oxygen, provided that the surface of the support substrate is free, that is to say not oxidized, to allow the oxygen to diffuse out. of the substrate.
• this precipitation / diffusion heat treatment must be carried out prior to the formation of the electrically insulating layer on the support substrate.
• the support substrate a silicon substrate having a low or medium content of interstitial oxygen, that is to say a content of less than 10, respectively between 10 and 20 old ppma.
• a silicon substrate having a low or medium content of interstitial oxygen, that is to say a content of less than 10, respectively between 10 and 20 old ppma.
• Such a substrate is generally designated by the abbreviation "LowOi”, respectively "MidOi”.
• the aforementioned precipitation and / or diffusion heat treatments are not necessary.
• the electrically insulating layer 20 is advantageously an oxide layer, in order to ensure good quality bonding with the semiconductor material of the donor substrate 1.
• the electrically insulating layer can be formed by a deposition process, in particular chemical vapor deposition (CVD, acronym for the English term “Chemical Vapor Deposition”) or by thermal oxidation treatment of the support substrate.
• CVD chemical vapor deposition
• thermal oxidation treatment of the support substrate in particular thermal oxidation treatment
• the thickness of the electrically insulating layer 20 is between 10 and 150 nm.
• the donor substrate 1 and the recipient substrate 2 are brought into contact, the thin layer 12 to be transferred and the electrically insulating layer 20 being at the bonding interface. There is then a bonding by molecular adhesion between the oxide of the layer 20 and the semiconductor material of the layer 12.
• the bonding can optionally be reinforced by a method of preparing the electrically insulating surface, for example by an oxygen plasma.
• the manufacturing steps subsequent to bonding remain unchanged from the existing FDSOI substrate manufacturing process, the process thus being compatible with existing industrial manufacturing lines and not affecting the physical and electrical properties of the product.
• the donor substrate 1 is detached along the weakening zone 11.
• said detachment can be caused by the application of a mechanical stress in the vicinity of the zone of weakening. embrittlement, by heat treatment or by any other suitable means.
• the thin layer 12 has been transferred from the donor substrate to the support substrate and an FDSOI structure is obtained comprising the support substrate 2, the electrically insulating bonding layer 2 and the transferred layer 12 (cf. figure 7).
• finishing treatment includes in particular thermal smoothing of the transferred layer (“batch anneal”) as mentioned in the introduction.
• this smoothing process consists of placing a batch of FDSOI structures in an oven, in carrying out a slow rise in temperature from room temperature (20 ° C) to a temperature of the order of 1500 to 1200 ° C, then maintaining the structures at this temperature for a period of several minutes, preferably greater than 15 minutes.
• the inventors consider that the formation of the protective oxide layer on the donor substrate could be the cause of a phenomenon of accumulation of dopants at the interface between the donor substrate and said oxide layer, which would diffuse after bonding the donor substrate to the support substrate.
• the removal of this layer which is made sacrificial (and possibly the surface portion of the underlying thin layer to be transferred) thus seems to eliminate or at least reduce this accumulation of dopants.
• the thermal budget of this smoothing process is high enough to allow diffusion of the dopants present in the structure, the dopants of the donor substrate are sufficiently removed from the support substrate by the electrically insulating layer (which does not contain such dopants) to do not diffuse into the support substrate. Therefore, the electrical resistivity of the support substrate is not affected, even in its portion near the bonding interface.
• the FDSOI structure thus formed is therefore fully functional for radiofrequency applications, in particular in the mmWave band.

Landscapes

• Element Separation (AREA)
• Thin Film Transistor (AREA)
• Recrystallisation Techniques (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=72178708

Family Applications (1)

Country Status (8)

Family Cites Families (21)

• 2020
  • 2020-05-18 FR FR2004970A patent/FR3110282B1/fr active Active
• 2021
  • 2021-05-13 TW TW110117326A patent/TWI911218B/zh active
  • 2021-05-18 WO PCT/FR2021/050874 patent/WO2021234280A1/fr not_active Ceased
  • 2021-05-18 JP JP2022528094A patent/JP7634008B2/ja active Active
  • 2021-05-18 CN CN202180006687.8A patent/CN114730732B/zh active Active
  • 2021-05-18 KR KR1020227013366A patent/KR102948024B1/ko active Active
  • 2021-05-18 EP EP21732484.7A patent/EP4154307A1/de active Pending
  • 2021-05-18 US US17/998,894 patent/US20230215760A1/en active Pending

Also Published As

Similar Documents

Legal Events