EP4241382A4 - Variationstolerante latch-basierte taktung - Google Patents
Variationstolerante latch-basierte taktung Download PDFInfo
- Publication number
- EP4241382A4 EP4241382A4 EP21889982.1A EP21889982A EP4241382A4 EP 4241382 A4 EP4241382 A4 EP 4241382A4 EP 21889982 A EP21889982 A EP 21889982A EP 4241382 A4 EP4241382 A4 EP 4241382A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- variation
- tolerant latch
- based clocking
- clocking
- tolerant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
- H04L9/3239—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/50—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using hash chains, e.g. blockchains or hash trees
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202063110274P | 2020-11-05 | 2020-11-05 | |
| PCT/US2021/057890 WO2022098753A1 (en) | 2020-11-05 | 2021-11-03 | Variation tolerant latch-based clocking |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP4241382A1 EP4241382A1 (de) | 2023-09-13 |
| EP4241382A4 true EP4241382A4 (de) | 2024-09-04 |
Family
ID=81458220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP21889982.1A Pending EP4241382A4 (de) | 2020-11-05 | 2021-11-03 | Variationstolerante latch-basierte taktung |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP4241382A4 (de) |
| WO (1) | WO2022098753A1 (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12430623B1 (en) * | 2023-07-25 | 2025-09-30 | Auradine, Inc. | Overclocking system for digital currency mining and method of operation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200103930A1 (en) * | 2018-09-29 | 2020-04-02 | Intel Corporation | Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6731138B2 (en) * | 2002-07-31 | 2004-05-04 | Intel Corporatioin | Circuits and methods for selectively latching the output of an adder |
| CN105226986B (zh) * | 2015-11-02 | 2018-01-09 | 南京航空航天大学 | 一种消除输入侧二次功率脉动的逆变器及其控制方法 |
| US20180004242A1 (en) | 2016-06-29 | 2018-01-04 | Intel Corporation | Low clock-energy 3-phase latch-based clocking scheme |
| US10164773B2 (en) | 2016-09-30 | 2018-12-25 | Intel Corporation | Energy-efficient dual-rail keeperless domino datapath circuits |
| US11379263B2 (en) * | 2018-08-13 | 2022-07-05 | Ares Technologies, Inc. | Systems, devices, and methods for selecting a distributed framework |
-
2021
- 2021-11-03 EP EP21889982.1A patent/EP4241382A4/de active Pending
- 2021-11-03 WO PCT/US2021/057890 patent/WO2022098753A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200103930A1 (en) * | 2018-09-29 | 2020-04-02 | Intel Corporation | Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022098753A1 (en) | 2022-05-12 |
| EP4241382A1 (de) | 2023-09-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
| 17P | Request for examination filed |
Effective date: 20230425 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
| DAV | Request for validation of the european patent (deleted) | ||
| DAX | Request for extension of the european patent (deleted) | ||
| A4 | Supplementary search report drawn up and despatched |
Effective date: 20240801 |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: G06F 1/06 20060101ALI20240726BHEP Ipc: G06Q 20/06 20120101ALI20240726BHEP Ipc: H04L 9/06 20060101ALI20240726BHEP Ipc: H03K 19/17736 20200101ALI20240726BHEP Ipc: H03K 19/17728 20200101AFI20240726BHEP |