EP4244726A4 - Hochparallele verarbeitungsarchitektur mit compiler - Google Patents

Hochparallele verarbeitungsarchitektur mit compiler Download PDF

Info

Publication number
EP4244726A4
EP4244726A4 EP21892956.0A EP21892956A EP4244726A4 EP 4244726 A4 EP4244726 A4 EP 4244726A4 EP 21892956 A EP21892956 A EP 21892956A EP 4244726 A4 EP4244726 A4 EP 4244726A4
Authority
EP
European Patent Office
Prior art keywords
compiler
parallel processing
processing architecture
highly parallel
highly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP21892956.0A
Other languages
English (en)
French (fr)
Other versions
EP4244726A1 (de
Inventor
Øyvind HARBOE
Tore Bastiansen
Peter Foley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ascenium Inc
Original Assignee
Ascenium Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascenium Inc filed Critical Ascenium Inc
Publication of EP4244726A1 publication Critical patent/EP4244726A1/de
Publication of EP4244726A4 publication Critical patent/EP4244726A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Devices For Executing Special Programs (AREA)
EP21892956.0A 2020-11-16 2021-11-15 Hochparallele verarbeitungsarchitektur mit compiler Withdrawn EP4244726A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063114003P 2020-11-16 2020-11-16
PCT/US2021/059304 WO2022104176A1 (en) 2020-11-16 2021-11-15 Highly parallel processing architecture with compiler

Publications (2)

Publication Number Publication Date
EP4244726A1 EP4244726A1 (de) 2023-09-20
EP4244726A4 true EP4244726A4 (de) 2024-08-21

Family

ID=81602646

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21892956.0A Withdrawn EP4244726A4 (de) 2020-11-16 2021-11-15 Hochparallele verarbeitungsarchitektur mit compiler

Country Status (3)

Country Link
EP (1) EP4244726A4 (de)
KR (1) KR20230101851A (de)
WO (1) WO2022104176A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024044150A1 (en) * 2022-08-23 2024-02-29 Ascenium, Inc. Parallel processing architecture with bin packing
US12436695B1 (en) * 2024-07-19 2025-10-07 Arm Limited Re-accessing data

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060004997A1 (en) * 2001-05-04 2006-01-05 Robert Keith Mykland Method and apparatus for computing
US20100122105A1 (en) * 2005-04-28 2010-05-13 The University Court Of The University Of Edinburgh Reconfigurable instruction cell array

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8250556B1 (en) * 2007-02-07 2012-08-21 Tilera Corporation Distributing parallelism for parallel processing architectures
US9152427B2 (en) * 2008-10-15 2015-10-06 Hyperion Core, Inc. Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file
KR102174335B1 (ko) * 2013-11-01 2020-11-04 삼성전자주식회사 재구성 가능 프로세서, 재구성 가능 프로세서의 구성 메모리의 사용을 최적화하는 방법 및 장치
US9785423B2 (en) * 2015-04-23 2017-10-10 Google Inc. Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
US11373266B2 (en) * 2017-05-05 2022-06-28 Intel Corporation Data parallelism and halo exchange for distributed machine learning

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060004997A1 (en) * 2001-05-04 2006-01-05 Robert Keith Mykland Method and apparatus for computing
US20100122105A1 (en) * 2005-04-28 2010-05-13 The University Court Of The University Of Edinburgh Reconfigurable instruction cell array

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PIERRE SYLVAIN ET AL: "The design and evaluation of the array machine", COMPUTER ARCHITECTURE, ACM, 2 PENN PLAZA, SUITE 701 NEW YORK NY 10121-0701 USA, 1 December 1974 (1974-12-01), pages 119 - 125, XP058196325, DOI: 10.1145/642089.642110 *
See also references of WO2022104176A1 *

Also Published As

Publication number Publication date
WO2022104176A1 (en) 2022-05-19
EP4244726A1 (de) 2023-09-20
KR20230101851A (ko) 2023-07-06

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