EP4282010A1 - Procédé de fabrication d'une cellule solaire - Google Patents

Procédé de fabrication d'une cellule solaire

Info

Publication number
EP4282010A1
EP4282010A1 EP22709584.1A EP22709584A EP4282010A1 EP 4282010 A1 EP4282010 A1 EP 4282010A1 EP 22709584 A EP22709584 A EP 22709584A EP 4282010 A1 EP4282010 A1 EP 4282010A1
Authority
EP
European Patent Office
Prior art keywords
wafer
polycrystalline
slm
front side
amorphous layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22709584.1A
Other languages
German (de)
English (en)
Inventor
Marc Hofmann
Sebastian Mack
Bishal Kafle
Jochen Rentsch
Nabeel Wahab KHAN
Laurent Clochard
Edward Duffy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ultra High Vacuum Solutions Ltd T/a Nines Photovoltaics
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Nines Photovoltaics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV, Nines Photovoltaics filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Publication of EP4282010A1 publication Critical patent/EP4282010A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only

Definitions

  • the invention relates to a method for producing a solar cell with a rear-side contact with a tunnel barrier, containing the following steps: providing a monocrystalline wafer with a front side and a rear side, the wafer containing or consisting of silicon and a dopant, producing a tunnel barrier on the wafer, depositing a polycrystalline or amorphous layer on the tunnel barrier, the polycrystalline or amorphous layer containing or consisting of silicon and a dopant, and removing the polycrystalline or amorphous layer on the front side.
  • Solar cells manufactured in this way are known as tunnel passivated contact solar cells (TOPcon solar cells).
  • the disadvantage of these solar cells lies in the complex production process.
  • the usual production of the layer of polycrystalline or amorphous doped silicon is by low-pressure synthesis using chemical vapor deposition. In this way, however, both the front and the back of the wafer are coated. Therefore the polycrystalline or amorphous doped silicon has to be removed again from the front side. According to the state of the art, this is done by means of wet-chemical etching in HF and/or HNO3 and/or an alkaline solution. However, this also etches the layer on the back and, in some cases, the tunnel barrier, so that the yield of functional cells is low.
  • the invention is based on the object of specifying a method for producing the rear side contact of a TOPcon solar cell, which reliably leads to predictable results.
  • the wafer can consist of monocrystalline silicon or contain monocrystalline silicon.
  • the wafer can be manufactured from an ingot by sawing.
  • the wafer may have a thickness of from about 50 ⁇ m to about 200 ⁇ m or from about 60 ⁇ m to about 120 ⁇ m.
  • the wafer can optionally contain a dopant which brings about a first conductivity.
  • the first conductivity can be an n-conductivity, for example.
  • the dopant f be selected from phosphorus, nitrogen and/or arsenic.
  • the wafer can be polygonal or round and, for example, have a diameter or have a circumference with a diameter of from about 100 mm to about 200 mm or from about 150 mm to about 300 mm.
  • the wafer has a front side and an opposite back side, with the front side being designed as the light entry surface of the finished solar cell for the purposes of the present description.
  • the front side can be provided with an emitter which contains at least one pn junction.
  • at least one front-side contact can be attached to the front side.
  • the front can be provided with reflection-reducing coating layers and/or structuring in order to increase the efficiency.
  • the rear is provided with a rear contact so that when light falls on the solar cell, an electrical voltage is generated between the front contact and the rear contact and a current can be tapped off.
  • a tunnel barrier is produced on the wafer to produce the rear-side contact.
  • the tunnel barrier can have an isolator or contain a dielectric.
  • the tunnel barrier may be a ceramic. contain a pottery.
  • the tunnel barrier can be a nitride or an oxide.
  • the tunnel barrier may contain or consist of silicon oxide.
  • the tunnel barrier can be produced by chemical vapor deposition, sputtering processes or tempering the wafer in an oxidizing atmosphere.
  • the tunnel barrier can have a thickness of about 1 nm to about 5 nm or about 1.5 nm. Depending on the selected manufacturing Depending on the method, the tunnel barrier can be generated exclusively on the rear side or both on the rear and on the front side of the wafer.
  • a polycrystalline or amorphous layer refers to a layer which appears amorphous, crystalline or partially crystalline in an X-ray structure analysis.
  • the polycrystalline or amorphous layer can optionally also contain a dopant.
  • the dopant can be selected from nitrogen, phosphorus or arsenic and in this respect bring about n-conductivity in the polycrystalline or amorphous layer.
  • the polycrystalline or amorphous layer can also contain a dopant which is selected from boron, aluminum or gallium and insofar causes p-type conductivity in the polycrystalline or amorphous layer.
  • the polycrystalline or amorphous layer may have a thickness of from about 50 nm to about 150 nm, or from about 100 to about 120 nm, or from about 50 to about 70 nm.
  • the polycrystalline or amorphous layer can preferably be produced by means of chemical vapor deposition, for example by means of low-pressure synthesis (LPCVD) or by plasma deposition (PECVD).
  • LPCVD low-pressure synthesis
  • PECVD plasma deposition
  • the polycrystalline or amorphous layer can also be deposited at atmospheric pressure (APCVD).
  • APCVD atmospheric pressure
  • the polycrystalline or amorphous layer can be formed by vapor deposition or physical vapor deposition (PVD) are generated.
  • the polycrystalline or amorphous layer does not form exclusively or exclusively. not predominantly on the backside of the wafer. Rather, a deposition of the polycrystalline or amorphous layer on the front side, which is undesirable per se, can be unavoidable.
  • the invention it is therefore proposed to remove the polycrystalline or amorphous layer on the front side of the wafer.
  • this is done by gas-phase etching, the etchant containing at least fluorine (F 2 ) or consisting of it.
  • F 2 fluorine
  • the wafer can be exposed to a corrosive gas atmosphere with its back resting on a holder, without the polycrystalline or amorphous layer being removed from the back.
  • the etchant attacks predominantly on the front side facing the open hemisphere, although the diffusion coefficient in the gas phase is several orders of magnitude greater than in liquids. Nevertheless, the selectivity of the etching process is significantly improved compared to a wet-chemical etching step used according to the prior art.
  • the wafer may be brought to a temperature of from about 120° C. to about 230° C. or from about 150° C. to about 260° C. for the gas phase etching. On the one hand, this temperature range allows the wafer to be processed sufficiently quickly so that the solar cell can be produced economically. On the other hand, the etching proceeds sufficiently slowly to enable good controllability of the etching depth. In other embodiments of the invention, the wafer may be brought to a temperature of about 170° C. to about 220° C. for the gas phase etching. In yet another embodiment, the wafer can be heated to a temperature of about 180°C to about 210°C.
  • the wafer can be heated to a temperature of from about 190°C to about 200°C. Lower temperatures enable better control and higher temperatures enable a faster etching rate, so that the process conditions can be adapted to the desired process control within the limits mentioned.
  • the wafer can rest on a conveyor belt for gas phase etching.
  • the conveyor belt can be mechanically driven. In this way, an exact control of the speed and, for a given length of the conveyor belt, an exact control of the etching time can be achieved, so that the method according to the invention has good reproducibility.
  • the gas phase etching is performed with a gas phase having a fluorine concentration of about 20% by volume to about 30% by volume.
  • the fluorine concentration may be from about 23% to about 27% by volume.
  • the fluorine concentration can be from about 1% to about 100% by volume.
  • the fluorine concentration may be about 25.7% by volume.
  • the remaining portions of the gas phase can form at least one inert gas, for example nitrogen and/or an inert gas.
  • the gas phase etch may be performed with a gas phase supplied with fluorine at a flow rate of from about 0.1 slm to about 100 slm.
  • the gas phase etching can be performed with a gas phase containing fluorine with a flow of about 3 slm to about 10 slm is supplied.
  • gaseous fluorine can be supplied at a flow rate of from about 5 slm to about 7 slm.
  • fluorine can be delivered at a flow rate of from about 5.5 slm to about 6.5 slm.
  • gaseous nitrogen can be supplied to the gas phase during the gas phase etching of the wafer at a flow rate of about 0 slm to about 100 slm. In some embodiments of the invention, gaseous nitrogen can be supplied to the gas phase during the gas phase etching of the wafer at a flow rate of about 0.5 slm to about 1.5 slm. In other embodiments of the invention, nitrogen can be supplied at a flow rate of from about 0.75 slm to about 1.25 slm. In yet another embodiment, nitrogen can be supplied at a flow rate of from about 0.9 slm to about 1.1 slm.
  • the gas phase etch can last from about 3 seconds to about 35 seconds. In some embodiments of the invention, the gas phase etch can last from about 15 seconds to about 35 seconds. This enables reliable removal of the polycrystalline or amorphous layer on the front side and optional structuring of the front side of the wafer. In other embodiments of the invention, the gas phase etch may last from about 20 seconds to about 22 seconds. This enables the polycrystalline or amorphous layer to be reliably removed without etching the wafer. In some embodiments of the invention, the gas phase etch can last from about 27 seconds to about 30 seconds. In addition to removing the polycrystalline or amorphous layer, this enables structuring of the front side of the wafer used as the light entry surface.
  • the gas phase etching can be carried out in a gas phase which has a pressure of approximately 950 mbar to approximately 1050 mbar. In other embodiments of the invention, the gas phase can have a pressure of about 960 mbar to about 1040 mbar during the gas phase etching. In still other embodiments of the invention, the pressure during the gas phase etching can be between about 980 mbar and about 1020 mbar. If the gas-phase etching is carried out at atmospheric pressure or at a pressure close to atmospheric pressure, the outlay on equipment is reduced so that the method according to the invention can be easily integrated into an existing production line.
  • the gas phase etching is terminated upon reaching the tunnel barrier at the front. It has been shown that the etch rate of silicon oxide is only about 0.012 nm/s to 0.016 nm/s, while the polycrystalline or amorphous layer has an etch rate of about 17.0 nm/s to about 25 nm/s. s is removed.
  • a tunnel barrier deposited on all sides on the front side can serve as an etch stop layer and simplify the process, since the tolerances of the etching time that must be maintained are increased.
  • the gas-phase etching can be continued on the front side when the tunnel barrier is reached, so that surface structuring is produced on the front side of the wafer. This process allows for surface structuring that improves the absorption behavior of the solar cell and to carry out the removal of the polycrystalline or amorphous layer in one operation, so that the production of the solar cell is further simplified.
  • the surface structuring can contain or consist of structures from about 1 ⁇ m to about 5 ⁇ m. In some embodiments of the invention, the surface structuring can contain or consist of structures from about 0.5 ⁇ m to about 1.5 ⁇ m. In some embodiments of the invention, the surface structuring can contain or consist of structures in the range from about 0.25 ⁇ m to about 1 ⁇ m. In some embodiments of the invention, the surface structuring can contain or consist of structures from about 0.1 ⁇ m to about 0.4 ⁇ m.
  • the size of the surface structure can be determined in each case using a scanning electron microscope. The surface structuring can be irregular and in this respect have a size distribution.
  • the method can also have the following steps: diffusing boron into the wafer and removing the boron-containing layer on the rear side. It has been shown that the pn junction serving as an emitter can be produced in a simple manner by diffusing boron into a wafer which has an n conductivity. Due to the manufacturing process, such a pn junction forms both on the front and on the back. The undesired pn junction on the rear side can be removed by wet or dry chemical etching in order in this way to prepare the rear side for the production of the rear side contact.
  • Wafer together with the material of the wafer in some
  • a borosilicate glass at the form surface can be removed on the back together with the undesired pn junction by wet or dry chemical etching.
  • the borosilicate glass can remain on the front side of the wafer in order to form an additional etch stop layer in this way.
  • the borosilicate glass after the removal of the polycrystalline or amorphous layer, can also be removed wet-chemically on the front side of the wafer.
  • the borosilicate glass can be removed wet-chemically even on the front side of the wafer before the polycrystalline or amorphous layer is deposited.
  • two different approaches are therefore proposed for protecting the boron emitter on the front side of the solar cell during the etching of the polycrystalline or amorphous layer.
  • One alternative is to use a thin tunnel oxide between the polycrystalline or amorphous layer and the emitter as a barrier layer. With this method, the borosilicate glass can be etched from the front and back after the emitter formation process, since this is not used as a barrier layer.
  • the other alternative is to use the borosilicate glass on the front side as a barrier against attack by the F 2 used as an etchant. In this case the borosilicate glass is left on the front but etched on the back.
  • FIG. 1 shows a cross section through a solar cell according to the invention.
  • FIG. 2 shows a flow chart of a method according to the invention in a first embodiment.
  • FIG. 3 shows a flow chart of a method according to the invention in a second embodiment.
  • FIG. 4 shows a flow chart of a method according to the invention in a third embodiment.
  • FIG. 5 shows a scanning electron micrograph of a front side of a wafer before the gas-phase etching according to the invention is carried out.
  • FIG. 6 shows a scanning electron micrograph of the front side of a wafer after the gas-phase etching proposed according to the invention.
  • the solar cell 1 consists of a wafer 2 with a front side 21 and a back side 22 .
  • the wafer 2 can contain or consist of silicon, for example.
  • the wafer 2 can additionally be provided with a dopant, for example phosphorus, arsenic, antimony or bismuth.
  • a dopant for example phosphorus, arsenic, antimony or bismuth.
  • the wafer 2 can have an n-type conductivity.
  • the wafer can have a p-conductivity.
  • the front side 21 of the wafer 2 is used as the light entry surface when the solar cell is operated as intended.
  • the front page 21 therefore a surface structuring 25 on .
  • the front side 21 can have a [100] orientation, which has been provided with a surface structure 25 by wet or dry chemical etching, which comprises a plurality of pyramids whose side surfaces each have a [111] orientation.
  • Adjacent to the front side 21 is an emitter 6, which is essentially formed by a pn junction.
  • the pn junction can be produced by injecting a dopant, for example boron.
  • the wafer 2 can be introduced into a boron-containing atmosphere and brought to an increased temperature, so that boron is introduced into the wafer 2 at least via the front side 21 .
  • the solar cell has front-side contacts 7, which can be produced in a manner known per se, for example by screen printing.
  • a rear-side contact is available for generating an electrical useful voltage, which is arranged on the rear side 22 of the wafer 2 and has a three-layer structure.
  • the rear contact initially consists of a tunnel barrier 3, which contains or consists of an oxide with a larger band gap than silicon.
  • the tunnel barrier 3 can contain or consist of SiO x with 1 ⁇ x ⁇ 2. This is arranged directly on the rear side 22 of the wafer 2 .
  • a metal layer 9 is applied directly or by means of at least one intermediate layer to the polycrystalline or amorphous layer 4, for example by PVD or CVD methods or by screen printing.
  • the Intermediate layer can be deposited by CVD or PVD and the metallization can be done by screen printing.
  • the metallization can be applied over the entire surface.
  • the metallization can be applied in partial areas, e.g. B. in point or line form.
  • the tunnel barrier 3 can be produced, for example, by thermal oxidation or by wet or dry chemical oxidation of the wafer 2 . As a result, the tunnel barrier 3 forms not only on the rear side 22 but also on the front side 21 and can be used there as an etching stop layer 35 .
  • the polycrystalline or amorphous layer 4 is deposited, for example, by chemical vapor deposition (CVD) or physical vapor deposition (PVD). This leads to the polycrystalline or amorphous layer 4 also being deposited on the front side 21 in an undesired manner. This can be removed quickly and, above all, selectively from the front side 21 by the gas-phase etching proposed according to the invention, with the polycrystalline or amorphous layer 4 remaining on the rear side 22 .
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • a monocrystalline silicon wafer which contains a dopant, resulting in an n-type conductivity of the wafer.
  • the wafer can be made from an ingot by sawing.
  • the wafer can have a polygonal or round cross-section.
  • a polygonal cross section can in particular be square or octagonal.
  • the wafer can have a diameter between about 100 mm and about 200 mm, or between about 150 mm and about 300 mm, or between about 200 mm and about 310 mm exhibit .
  • the wafer may have a thickness of from about 50 ⁇ m to about 150 ⁇ m or from about 50 ⁇ m to about 200 ⁇ m.
  • a defective surface layer of the wafer can be removed by wet or dry chemical etching, for example using an alkaline solution.
  • the etch can be done in a solution of HF and HNO3.
  • the defect-rich surface layer can have a thickness of about 1 ⁇ m to about 10 ⁇ m.
  • the wafer is heated to an elevated temperature in an oxidizing atmosphere, so that both the front and the back are provided with an oxide layer.
  • the oxide formed in method step 56 can have a thickness of about 1 nm to about 5 nm or of about 1.5 nm to about 3 nm. This oxide forms the tunnel barrier of the rear contact on the rear.
  • the wafer prepared in this way is provided with a polycrystalline or amorphous layer, which contains silicon and a dopant, by means of LPCVD.
  • the dopant can be chosen so that the polycrystalline or amorphous layer has the same conductivity type as the wafer.
  • the polycrystalline or amorphous layer can be doped with phosphorus, for example, in order to bring about n-conductivity.
  • the polycrystalline or amorphous layer can have a thickness of from about 30 nm to about 300 nm or from about 40 nm to about 150 nm.
  • the CVD method used means that both the front and the back of the wafer be provided with the polycrystalline or amorphous layer.
  • the wafer is etched at a temperature of approximately 195° C. for approximately 28 seconds in a gas phase which contains approximately 25.7% by volume fluorine and the remainder nitrogen.
  • gaseous fluorine is supplied via a mass flow controller with a flow rate of about 6 slm.
  • nitrogen is supplied with a flow of about 1 slm.
  • the back of the wafer rests on a conveyor belt, which transports the wafer through the reactor used for gas-phase etching within 28 seconds.
  • the polycrystalline or amorphous layer on the front side is completely removed in the illustrated embodiment.
  • the tunnel barrier on the front side of the wafer is also completely removed.
  • the wafer itself is partially attacked by the gas phase etching, so that a surface structure 25 arises on the front side. This can reduce the degree of reflection of the wafer, so that a higher proportion of the incident light is absorbed in the volume of the wafer or at the emitter during later operation of the solar cell.
  • a hydrogen-rich dielectric layer e.g. B. amorphous silicon nitride (SiNx), deposited on the doped silicon layer.
  • SiNx amorphous silicon nitride
  • the SiNx layer increases the passivation quality of the rear side through the diffusion of hydrogen species to the rear silicon surface during silicon-metal contact formation.
  • it acts as a barrier against the boron atoms during the subsequent boron diffusion step 54.
  • the wafer is then exposed to a boron-containing gas atmosphere at an elevated temperature in method step 54 .
  • boron diffuses into the wafer 2 via the front side 21, with the SiNx layer on the rear acting as a barrier against the diffusion of boron atoms.
  • a pn junction is thus formed adjacent to the front side.
  • the pn junction adjacent to the front is used as the emitter 6, i. H .
  • Incoming electromagnetic radiation is absorbed with the formation of electron-hole pairs, which can be tapped off as electrical energy via the front and rear contacts of the solar cell.
  • the polycrystalline or amorphous silicon layer on the back of the wafer is also recrystallized as an optimal passivation layer. The crystallization of this layer occurs due to the high temperature budget used in the diffusion process.
  • the undesired layer of borosilicate glass formed on the surfaces of the wafer is removed in the next method step 552 by wet or dry chemical etching.
  • At least one optional passivation and/or coating layer is applied to the front side.
  • This can contain or consist of sapphire, silicon nitrite and/or magnesium fluoride, for example. These layers improve the long-term stability of the solar cell by preventing the ingress of atmospheric oxygen. In addition, these layers can act as optical coating layers, which improve the absorption behavior and reduce the degree of reflection.
  • a wafer 2 is provided, as described above.
  • the front side 21 is provided with a surface structure 25 by wet-chemical etching.
  • the front side 21 of the wafer 2 can have a [100] orientation, in which pyramids are introduced by etching, the side faces of which have a
  • the front side 21 structured in this way can have a lower degree of reflection, since light reflected at the boundary surface between air and silicon is not reflected into the surroundings, but at least partially strikes the silicon surface again.
  • method step 54 boron is diffused in, so that a pn junction is formed both on the front and on the back, as described above.
  • the pn junction on the back is removed again.
  • the borosilicate glass formed from silicon and boron on the surface of the wafer is completely removed from both the front and the back. This is also preferably done by wet or dry chemical etching. However, in particular the removal of the pn junction on the rear side can also be done by laser material processing, micro-grinding or similar methods known per se.
  • the tunnel barrier is formed by thermal oxidation of the wafer. The polycrystalline or amorphous layer is then deposited on the tunnel barrier, as described above. Because of the manufacturing process, at least partial coating of the front side with the tunnel barrier and the polycrystalline or amorphous layer cannot be ruled out.
  • the wafer is positioned on a conveyor belt, with the rear side lying on the conveyor belt.
  • the wafer is then heated to 195° C. and transported within 21 seconds through the reactor, which contains a gas phase consisting of 25.7 vol. -% is composed of fluorine and nitrogen. Fluorine is supplied with a flow of 6 slm and nitrogen with a flow of 1 slm.
  • the polycrystalline or amorphous layer on the front side is removed and only the tunnel barrier on the front side of the wafer remains at least partially.
  • An attack of the etchant on the front side of the wafer was prevented by the tunnel barrier on the front side acting as an etch stop layer. Surprisingly, the etchant does not attack the back.
  • the rear side is adequately protected from attack by the etching agent by lying on the conveyor belt.
  • the solar cell is then completed in method steps 592, 591 and 593 by applying the passivation layers on the front and forming the metal contacts 7 and 9 on the front and back, as described above with reference to the first exemplary embodiment.
  • a dielectric layer e.g. B. SiNx, can also be deposited on the backside polycrystalline layer before the metallization step 593 .
  • a third alternative of the method according to the invention is described with reference to FIG. In this case, too, the same method steps are provided with the same reference symbols, so that the following description can be limited to the essential differences.
  • a wafer 2 is again provided, as described above. This is provided with a surface structure 25 in method step 52, as has already been explained with reference to FIG.
  • boron is injected into the wafer, as described with reference to FIG. 3 in the second exemplary embodiment.
  • the pn junction forming on the back is removed, as already explained with reference to the second exemplary embodiment and FIG.
  • the borosilicate glass that forms is only removed on the back together with the pn junction. This remains on the wafer on the front side.
  • the borosilicate glass will later be used as an additional etch stop layer in order to prevent the etchant from attacking the front side 21 of the wafer 2 when the polycrystalline or amorphous layer is removed.
  • the tunnel barrier 3 is formed by thermally producing an SiO 2 layer at least on the rear side 22, as described above.
  • the polycrystalline or amorphous layer 4 is again deposited on the tunnel barrier 3 in method step 57 by means of an LPCVD method.
  • the polycrystalline or amorphous layer 4 on the front side is removed by gas phase etching with fluorine as described above.
  • the borosilicate glass on the front side is now available as an etching stop layer. This prevents the etchant from attacking the material of the wafer and thus destroying the front side and the emitter with even greater reliability.
  • the parameters of the etching process in particular the fluorine concentration, the temperature and the time, can be set with larger tolerances, or the etching process can be carried out with greater reliability, and thus increase the yield of functional solar cells.
  • the borosilicate glass remaining on the front side is removed in process step 554 .
  • This can also be done wet or dry chemically by selective etching so that the etching process stops automatically when the silicon surface is reached.
  • the solar cell is then completed in method steps 591, 592 and 593 by producing the passivation and tempering layers and applying the metallic contacts 7 and 9.
  • the sequence of the method steps can also be changed.
  • the annealing can take place before the etching.
  • doping for example with POCl3, can take place before this layer is removed on one side.
  • FIG. 5 shows the interface after method step 57 according to FIG. 4 has been completed and before method step 58 has been carried out.
  • FIG. 6 shows the interface after method step 58 has been carried out and before method step 554 has been carried out.
  • the layer of borosilicate glass acting as an etching stop layer 35 is located on the silicon of the wafer 2 and is inevitably produced when the wafer 2 is doped with boron.
  • the etching stop layer 35 would be the tunnel barrier formed from SiO 2 .
  • the polycrystalline or amorphous layer 4 which contains silicon and at least one dopant, is located on the etch stop layer 35 .
  • FIG. 6 shows the surface after method step 58 has been carried out. It can be seen that the polycrystalline or amorphous layer 4 was removed in only 21 seconds by the attack of the fluorine gas (F 2 ) used as an etchant. Only the etch stop layer 35 consisting of borosilicate glass remains on the surface of the wafer 2 and is removed in the subsequent method step.
  • F 2 fluorine gas

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  • Photovoltaic Devices (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Sustainable Energy (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une cellule solaire (1) comprenant un contact arrière (9) muni d'une barrière tunnel (4), lequel procédé comprend les étapes suivantes consistant à : fournir une tranche monocristalline (2) présentant une face avant (21) et une face arrière (22), la tranche (2) contenant du silicium et un dopant ou étant constituée de ceux-ci, réaliser une barrière tunnel (3) sur la tranche (2), déposer une couche polycristalline ou amorphe (4) sur la barrière tunnel (3), la couche polycristalline ou amorphe (4) contenant du silicium et un dopant ou étant constituée de ceux-ci, éliminer la couche polycristalline ou amorphe (4) sur la face avant (21) par gravure en phase vapeur, l'agent de gravure contenant du F2 ou étant constitué de celui-ci.
EP22709584.1A 2021-01-25 2022-01-24 Procédé de fabrication d'une cellule solaire Pending EP4282010A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102021200627.2A DE102021200627A1 (de) 2021-01-25 2021-01-25 Verfahren zur Herstellung einer Solarzelle
PCT/EP2022/051446 WO2022157346A1 (fr) 2021-01-25 2022-01-24 Procédé de fabrication d'une cellule solaire

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US (1) US20230361237A1 (fr)
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CN (1) CN117941079A (fr)
DE (1) DE102021200627A1 (fr)
WO (1) WO2022157346A1 (fr)

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4340031B2 (ja) * 2001-09-26 2009-10-07 京セラ株式会社 太陽電池用基板の粗面化方法
JP4104320B2 (ja) * 2001-11-16 2008-06-18 セントラル硝子株式会社 二フッ化カルボニルの製造方法
US10453986B2 (en) * 2008-01-23 2019-10-22 Solvay Fluor Gmbh Process for the manufacture of solar cells
US9054255B2 (en) * 2012-03-23 2015-06-09 Sunpower Corporation Solar cell having an emitter region with wide bandgap semiconductor material
KR20140021096A (ko) * 2012-08-07 2014-02-20 한국전자통신연구원 도핑 베리어를 가지는 자기 정렬 박막 트랜지스터 및 그 제조 방법
CN102856328B (zh) * 2012-10-10 2015-06-10 友达光电股份有限公司 太阳能电池及其制作方法
KR102045001B1 (ko) * 2013-06-05 2019-12-02 엘지전자 주식회사 태양 전지 및 이의 제조 방법
KR102098100B1 (ko) * 2013-09-17 2020-04-08 엘지이노텍 주식회사 태양전지 및 이의 제조 방법
JP6107767B2 (ja) * 2013-12-27 2017-04-05 トヨタ自動車株式会社 半導体装置とその製造方法
US9257298B2 (en) * 2014-03-28 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods for in situ maintenance of a thin hardmask during an etch process
KR102244838B1 (ko) * 2014-04-28 2021-04-26 엘지전자 주식회사 태양 전지 및 이의 제조 방법
EP3038169A1 (fr) 2014-12-22 2016-06-29 Solvay SA Processus de fabrication de cellules solaires
KR102317141B1 (ko) * 2015-02-10 2021-10-22 엘지전자 주식회사 태양 전지
CN105374882A (zh) * 2015-12-21 2016-03-02 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制备方法
US9954128B2 (en) * 2016-01-12 2018-04-24 The Boeing Company Structures for increased current generation and collection in solar cells with low absorptance and/or low diffusion length
NL2016382B1 (en) * 2016-03-07 2017-09-19 Stichting Energieonderzoek Centrum Nederland Method for manufacturing a solar cell with doped polysilicon surface areas
JP6689159B2 (ja) * 2016-08-22 2020-04-28 東京エレクトロン株式会社 エッチング方法およびｄｒａｍキャパシタの製造方法
JP6673232B2 (ja) * 2017-01-17 2020-03-25 株式会社デンソー 炭化珪素半導体装置
JP6820775B2 (ja) * 2017-03-17 2021-01-27 株式会社日立ハイテク エッチング方法及びプラズマ処理装置
WO2019059765A1 (fr) 2017-09-22 2019-03-28 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Cellule solaire à contact arrière interdigité à conductivité du type p
DE102017219312A1 (de) 2017-10-27 2019-05-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 2-stufiger Trockenätzprozess zur Texturierung kristalliner Siliziumscheiben
US20190326401A1 (en) * 2018-04-20 2019-10-24 Qualcomm Incorporated Body connection for a silicon-on-insulator device
WO2019213207A1 (fr) * 2018-05-01 2019-11-07 Applied Materials, Inc. Procédés d'augmentation de la sélectivité pour des procédés de gravure sélective
CN109256440A (zh) * 2018-09-17 2019-01-22 浙江爱旭太阳能科技有限公司 一种选择性钝化接触晶体硅太阳能电池及其制备方法
JP7149788B2 (ja) * 2018-09-21 2022-10-07 東京エレクトロン株式会社 成膜方法及び成膜装置
CN109524300B (zh) * 2018-11-28 2021-08-03 上海华力微电子有限公司 一种刻蚀方法及半导体器件
US11289578B2 (en) * 2019-04-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Selective etching to increase threshold voltage spread
US11522096B2 (en) * 2020-03-03 2022-12-06 King Fahd University Of Petroleum And Minerals Perovskite-silicon tandem structure and photon upconverters
FR3112428A1 (fr) * 2020-07-13 2022-01-14 Semco Smartech France Procédé de formation de contacts passivés pour cellules solaires IBC
US11538690B2 (en) * 2021-02-09 2022-12-27 Tokyo Electron Limited Plasma etching techniques
US20220301887A1 (en) * 2021-03-16 2022-09-22 Applied Materials, Inc. Ruthenium etching process
JP7391064B2 (ja) * 2021-03-22 2023-12-04 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理システム、およびプログラム

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US20230361237A1 (en) 2023-11-09
DE102021200627A1 (de) 2022-08-25
CN117941079A (zh) 2024-04-26
WO2022157346A1 (fr) 2022-07-28

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